From cc96daeac919cdf77e3f0339cfb0b975682365b2 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 10 Apr 2023 16:02:53 -0300 Subject: [PATCH 01/24] afc_ref_fofb_ctrl_gen.vhd: remove unused record definition This should have been removed on 8f39e0bb42eb26eec7fca571b2c8f594edbe2de5. --- hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 9fda8de2..dd83cdc3 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -371,15 +371,6 @@ architecture top of afc_ref_fofb_ctrl_gen is max_fp_p2p_gts : integer; end record; - type t_serialize_data_state is - ( - IDLE, - DRIVE_X_DATA_OR_TIMEFRAME_END, - LOWER_VALID_X_DATA_OR_TIMEFRAME_END, - DRIVE_Y_DATA, - LOWER_VALID_Y_DATA - ); - function f_extract_gt_cfg(num_p2p : integer) return t_gt_cfg is variable rv : t_gt_cfg; begin From aeaad377ed3f7c0d9c77088af61a228df94974a1 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 14 Feb 2023 18:21:53 -0300 Subject: [PATCH 02/24] fofb_processing/cheby: clean registers api By the time this layout was drawn, cheby had a bug that didn't allow the usage of 'repeat' statements if the design contained memories. The workaround was to flatenize the per-channel registers/memories declarations. The issue mentioned above doesn't appear on cheby 1.4.0. So, this commit cleans up the registers api. --- hdl/ip_cores/general-cores | 2 +- .../fofb_processing/cheby/build_cheby.sh | 2 +- .../cheby/wb_fofb_processing_regs.cheby | 1504 +--- .../cheby/wb_fofb_processing_regs.h | 686 +- .../cheby/wb_fofb_processing_regs.vhd | 6430 +++++++---------- .../fofb_processing_dcc_adapter.vhd | 1 - .../fofb_processing/xwb_fofb_processing.vhd | 491 +- .../wb_fofb_processing_regs_consts_pkg.vhd | 401 +- .../xwb_fofb_processing_tb.vhd | 209 +- 9 files changed, 3681 insertions(+), 6045 deletions(-) diff --git a/hdl/ip_cores/general-cores b/hdl/ip_cores/general-cores index 20ade77c..4cd50a34 160000 --- a/hdl/ip_cores/general-cores +++ b/hdl/ip_cores/general-cores @@ -1 +1 @@ -Subproject commit 20ade77c41bcb981276a3980858fc5574f12460f +Subproject commit 4cd50a34faa3c640084e4b0af28717ea0312d6c8 diff --git a/hdl/modules/fofb_processing/cheby/build_cheby.sh b/hdl/modules/fofb_processing/cheby/build_cheby.sh index e95965fe..0b5b96f1 100755 --- a/hdl/modules/fofb_processing/cheby/build_cheby.sh +++ b/hdl/modules/fofb_processing/cheby/build_cheby.sh @@ -1,3 +1,3 @@ #!/bin/bash -cheby -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd +cheby -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby index ebb2746f..9c3c2b5a 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby @@ -1,1334 +1,200 @@ memory-map: bus: wb-32-be name: wb_fofb_processing_regs - description: interface to internal regs and coefficient ram banks - x-wbgen: - hdl_entity: wb_fofb_processing_regs + description: interface to internal regs + x-hdl: + busgroup: True children: - - reg: - name: coeffs_fixed_point_pos - width: 32 - access: rw + - block: + name: fixed_point_pos + description: fofb processing fixed-point position constants + size: 64 address: 0x00000000 - description: fofb processing coefficients fixed-point position constant children: - - field: - name: val - range: 31-0 - description: fixed-point position constant value - x-wbgen: - type: SLV - access_dev: WRITE_ONLY - access_bus: READ_ONLY - clock: wb_fofb_processing_regs_clk_i - - reg: - name: accs_gains_fixed_point_pos - width: 32 - access: ro - address: 0x00000004 - description: fofb processing accumulators' gains fixed-point position register - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: WRITE_ONLY - access_bus: READ_ONLY - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_0 - width: 32 - access: rw - address: 0x00000008 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_0 - width: 32 - access: rw - address: 0x0000000C - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_1 - width: 32 - access: rw - address: 0x00000010 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_1 - width: 32 - access: rw - address: 0x00000014 - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_2 - width: 32 - access: rw - address: 0x00000018 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_2 - width: 32 - access: rw - address: 0x0000001C - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_3 - width: 32 - access: rw - address: 0x00000020 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_3 - width: 32 - access: rw - address: 0x00000024 - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_4 - width: 32 - access: rw - address: 0x00000028 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_4 - width: 32 - access: rw - address: 0x0000002C - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_5 - width: 32 - access: rw - address: 0x00000030 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_5 - width: 32 - access: rw - address: 0x00000034 - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_6 - width: 32 - access: rw - address: 0x00000038 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_6 - width: 32 - access: rw - address: 0x0000003C - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_7 - width: 32 - access: rw - address: 0x00000040 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_7 - width: 32 - access: rw - address: 0x00000044 - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_8 - width: 32 - access: rw - address: 0x00000048 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_8 - width: 32 - access: rw - address: 0x0000004C - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_9 - width: 32 - access: rw - address: 0x00000050 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_9 - width: 32 - access: rw - address: 0x00000054 - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_10 - width: 32 - access: rw - address: 0x00000058 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_10 - width: 32 - access: rw - address: 0x0000005C - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_gain_11 - width: 32 - access: rw - address: 0x00000060 - description: fofb processing accumulator gain register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: acc_ctl_11 - width: 32 - access: rw - address: 0x00000064 - description: fofb processing accumulator control register (per channel) - children: - - field: - name: clear - range: 0 - description: clear accumulator bit - comment: | - write 0: no effect - write 1: clears accumulator (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: freeze - range: 1 - description: freeze accumulator bit - comment: | - write 0: no effect on accumulator - write 1: freezes accumulator - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_0 - width: 32 - access: rw - address: 0x00000068 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_0 - width: 32 - access: rw - address: 0x0000006C - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_1 - width: 32 - access: rw - address: 0x00000070 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_1 - width: 32 - access: rw - address: 0x00000074 - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_2 - width: 32 - access: rw - address: 0x00000078 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_2 - width: 32 - access: rw - address: 0x0000007C - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_3 - width: 32 - access: rw - address: 0x00000080 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_3 - width: 32 - access: rw - address: 0x00000084 - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_4 - width: 32 - access: rw - address: 0x00000088 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_4 - width: 32 - access: rw - address: 0x0000008C - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_5 - width: 32 - access: rw - address: 0x00000090 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_5 - width: 32 - access: rw - address: 0x00000094 - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_6 - width: 32 - access: rw - address: 0x00000098 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_6 - width: 32 - access: rw - address: 0x0000009C - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_7 - width: 32 - access: rw - address: 0x000000A0 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_7 - width: 32 - access: rw - address: 0x000000A4 - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_8 - width: 32 - access: rw - address: 0x000000A8 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_8 - width: 32 - access: rw - address: 0x000000AC - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_9 - width: 32 - access: rw - address: 0x000000B0 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_9 - width: 32 - access: rw - address: 0x000000B4 - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_10 - width: 32 - access: rw - address: 0x000000B8 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_10 - width: 32 - access: rw - address: 0x000000BC - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_max_11 - width: 32 - access: rw - address: 0x000000C0 - description: fofb processing maximum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: sp_min_11 - width: 32 - access: rw - address: 0x000000C4 - description: fofb processing minimum saturation value register (per channel) - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: loop_intlk_src_en_ctl - width: 32 - access: rw - address: 0x000000C8 - description: fofb processing loop interlock sources enable control register - children: - - field: - name: orb_distort_en - range: 0 - description: orbit distortion source enable - comment: | - write 0: disables source - write 1: enables source - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - field: - name: packet_loss_en - range: 1 - description: packet loss source enable - comment: | - write 0: disables source - write 1: enables source - x-wbgen: - type: BIT - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: loop_intlk_ctl - width: 32 - access: rw - address: 0x000000CC - description: fofb processing loop interlock control register - children: - - field: - name: clr - range: 0 - description: clears loop interlock status - comment: | - write 0: no effect - write 1: clears loop interlock status (this bit autoclears) - x-wbgen: - type: MONOSTABLE - access_dev: READ_ONLY - access_bus: WRITE_ONLY - clock: wb_fofb_processing_regs_clk_i - - reg: - name: loop_intlk_sta - width: 32 - access: rw - address: 0x000000D0 - description: fofb processing loop interlock status register - children: - - field: - name: orb_distort - range: 0 - description: orbit distortion loop interlock flag - comment: | - read 0: not interlocked - read 1: interlocked - x-wbgen: - type: BIT - access_dev: WRITE_ONLY - access_bus: READ_ONLY - clock: wb_fofb_processing_regs_clk_i - - field: - name: packet_loss - range: 1 - description: packet loss loop interlock flag - comment: | - read 0: not interlocked - read 1: interlocked - x-wbgen: - type: BIT - access_dev: WRITE_ONLY - access_bus: READ_ONLY - clock: wb_fofb_processing_regs_clk_i - - reg: - name: orb_distort_limit - width: 32 - access: rw - address: 0x000000D4 - description: fofb processing loop interlock orbit distortion limit value register - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - reg: - name: min_num_pkts - width: 32 - access: rw - address: 0x000000D8 - description: fofb processing loop interlock minimum number of packets per timeframe value register - children: - - field: - name: val - range: 31-0 - description: value - x-wbgen: - type: SLV - access_dev: READ_ONLY - access_bus: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - - memory: - name: coeffs_ram_bank_0 - memsize: 2k - address: 0x00000800 - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_1 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_2 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_3 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_4 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_5 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_6 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_7 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_8 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_9 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_10 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw - - memory: - name: coeffs_ram_bank_11 - memsize: 2k - address: next - description: fofb processing coefficients ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True - children: - - reg: - name: data - width: 32 - access: rw + - reg: + name: coeff + width: 32 + access: ro + address: next + description: fofb processing coefficients fixed-point position constant + children: + - field: + name: val + range: 31-0 + description: fixed-point position constant value + - reg: + name: accs_gains + width: 32 + access: ro + address: next + description: fofb processing accumulators' gains fixed-point position register + children: + - field: + name: val + range: 31-0 + description: value + - block: + name: loop_intlk + description: fofb processing loop interlock registers + size: 64 + children: + - reg: + name: ctl + width: 32 + access: rw + address: next + description: fofb processing loop interlock control register + children: + - field: + name: sta_clr + x-hdl: + type: autoclear + range: 0 + description: clears loop interlock status + comment: | + write 0: no effect + write 1: clears loop interlock status (this bit autoclears) + - field: + name: src_en_orb_distort + range: 1 + description: orbit distortion source enable + comment: | + write 0: disables source + write 1: enables source + - field: + name: src_en_packet_loss + range: 2 + description: packet loss source enable + comment: | + write 0: disables source + write 1: enables source + - reg: + name: sta + width: 32 + access: ro + address: next + description: fofb processing loop interlock status register + children: + - field: + name: orb_distort + range: 0 + description: orbit distortion loop interlock flag + comment: | + read 0: not interlocked + read 1: interlocked + - field: + name: packet_loss + range: 1 + description: packet loss loop interlock flag + comment: | + read 0: not interlocked + read 1: interlocked + - reg: + name: orb_distort_limit + width: 32 + access: rw + address: next + description: fofb processing loop interlock orbit distortion limit value register + children: + - field: + name: val + range: 31-0 + description: value + - reg: + name: min_num_pkts + width: 32 + access: rw + address: next + description: fofb processing loop interlock minimum number of packets per timeframe value register + children: + - field: + name: val + range: 31-0 + description: value - memory: - name: setpoints_ram_bank + name: sps_ram_bank memsize: 2k address: next description: fofb processing setpoints ram bank - align: True - x-wbgen: - kind: ram - access_bus: READ_WRITE - access_dev: READ_WRITE - clock: wb_fofb_processing_regs_clk_i - x-hdl: - dual-clock: True children: - reg: name: data width: 32 access: rw + - repeat: + name: ch + count: 12 + size: 4096 + align : False + children: + - memory: + name: coeff_ram_bank + memsize: 2k + description: fofb processing coefficients ram bank (per channel) + children: + - reg: + name: data + width: 32 + access: rw + - block: + name: acc + description: fofb processing accumulator registers (per channel) + size: 64 + children: + - reg: + name: ctl + width: 32 + access: rw + description: fofb processing accumulator control register (per channel) + children: + - field: + name: clear + x-hdl: + type: autoclear + range: 0 + description: clear accumulator bit + comment: | + write 0: no effect + write 1: clears accumulator (this bit autoclears) + - field: + name: freeze + range: 1 + description: freeze accumulator bit + comment: | + write 0: no effect on accumulator + write 1: freezes accumulator + - reg: + name: gain + width: 32 + access: rw + description: fofb processing accumulator gain register (per channel) + children: + - field: + name: val + range: 31-0 + description: value + - block: + name: sp_limits + description: fofb processing saturation limits registers (per channel) + align: False + children: + - reg: + name: max + width: 32 + access: rw + description: fofb processing maximum saturation value register (per channel) + children: + - field: + name: val + range: 31-0 + description: value + - reg: + name: min + width: 32 + access: rw + description: fofb processing minimum saturation value register (per channel) + children: + - field: + name: val + range: 31-0 + description: value diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h index 274c01c6..b0d123a4 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h @@ -1,618 +1,164 @@ #ifndef __CHEBY__WB_FOFB_PROCESSING_REGS__H__ #define __CHEBY__WB_FOFB_PROCESSING_REGS__H__ -#define WB_FOFB_PROCESSING_REGS_SIZE 28672 /* 0x7000 = 28KB */ +#define WB_FOFB_PROCESSING_REGS_SIZE 53248 /* 0xd000 = 52KB */ + +/* fofb processing fixed-point position constants */ +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS 0x0UL +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_SIZE 64 /* 0x40 */ /* fofb processing coefficients fixed-point position constant */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_FIXED_POINT_POS 0x0UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_FIXED_POINT_POS_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_COEFFS_FIXED_POINT_POS_VAL_SHIFT 0 +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_COEFF 0x0UL +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_COEFF_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_COEFF_VAL_SHIFT 0 /* fofb processing accumulators' gains fixed-point position register */ -#define WB_FOFB_PROCESSING_REGS_ACCS_GAINS_FIXED_POINT_POS 0x4UL -#define WB_FOFB_PROCESSING_REGS_ACCS_GAINS_FIXED_POINT_POS_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACCS_GAINS_FIXED_POINT_POS_VAL_SHIFT 0 - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_0 0x8UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_0 0xcUL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_0_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_0_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_1 0x10UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_1_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_1_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_1 0x14UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_1_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_1_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_2 0x18UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_2_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_2_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_2 0x1cUL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_2_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_2_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_3 0x20UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_3_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_3_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_3 0x24UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_3_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_3_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_4 0x28UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_4_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_4_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_4 0x2cUL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_4_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_4_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_5 0x30UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_5_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_5_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_5 0x34UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_5_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_5_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_6 0x38UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_6_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_6_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_6 0x3cUL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_6_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_6_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_7 0x40UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_7_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_7_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_7 0x44UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_7_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_7_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_8 0x48UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_8_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_8_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_8 0x4cUL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_8_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_8_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_9 0x50UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_9_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_9_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_9 0x54UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_9_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_9_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_10 0x58UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_10_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_10_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_10 0x5cUL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_10_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_10_FREEZE 0x2UL - -/* fofb processing accumulator gain register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_11 0x60UL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_11_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ACC_GAIN_11_VAL_SHIFT 0 - -/* fofb processing accumulator control register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_11 0x64UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_11_CLEAR 0x1UL -#define WB_FOFB_PROCESSING_REGS_ACC_CTL_11_FREEZE 0x2UL - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_0 0x68UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_0_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_0_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_0 0x6cUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_0_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_0_VAL_SHIFT 0 +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ACCS_GAINS 0x4UL +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ACCS_GAINS_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ACCS_GAINS_VAL_SHIFT 0 -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_1 0x70UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_1_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_1_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_1 0x74UL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_1_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_1_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_2 0x78UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_2_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_2_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_2 0x7cUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_2_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_2_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_3 0x80UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_3_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_3_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_3 0x84UL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_3_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_3_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_4 0x88UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_4_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_4_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_4 0x8cUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_4_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_4_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_5 0x90UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_5_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_5_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_5 0x94UL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_5_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_5_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_6 0x98UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_6_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_6_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_6 0x9cUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_6_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_6_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_7 0xa0UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_7_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_7_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_7 0xa4UL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_7_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_7_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_8 0xa8UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_8_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_8_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_8 0xacUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_8_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_8_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_9 0xb0UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_9_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_9_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_9 0xb4UL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_9_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_9_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_10 0xb8UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_10_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_10_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_10 0xbcUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_10_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_10_VAL_SHIFT 0 - -/* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MAX_11 0xc0UL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_11_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MAX_11_VAL_SHIFT 0 - -/* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_SP_MIN_11 0xc4UL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_11_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_SP_MIN_11_VAL_SHIFT 0 - -/* fofb processing loop interlock sources enable control register */ -#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL 0xc8UL -#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN 0x1UL -#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN 0x2UL +/* fofb processing loop interlock registers */ +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK 0x40UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SIZE 64 /* 0x40 */ /* fofb processing loop interlock control register */ -#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL 0xccUL -#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_CLR 0x1UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL 0x40UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_STA_CLR 0x1UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT 0x2UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS 0x4UL /* fofb processing loop interlock status register */ -#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA 0xd0UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA 0x44UL #define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ORB_DISTORT 0x1UL #define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_PACKET_LOSS 0x2UL /* fofb processing loop interlock orbit distortion limit value register */ -#define WB_FOFB_PROCESSING_REGS_ORB_DISTORT_LIMIT 0xd4UL -#define WB_FOFB_PROCESSING_REGS_ORB_DISTORT_LIMIT_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_ORB_DISTORT_LIMIT_VAL_SHIFT 0 +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT 0x48UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT_VAL_SHIFT 0 /* fofb processing loop interlock minimum number of packets per timeframe value register */ -#define WB_FOFB_PROCESSING_REGS_MIN_NUM_PKTS 0xd8UL -#define WB_FOFB_PROCESSING_REGS_MIN_NUM_PKTS_VAL_MASK 0xffffffffUL -#define WB_FOFB_PROCESSING_REGS_MIN_NUM_PKTS_VAL_SHIFT 0 - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0 0x800UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1 0x1000UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_2 0x1800UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_2_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_2_DATA 0x0UL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS 0x4cUL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_VAL_SHIFT 0 -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_3 0x2000UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_3_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_3_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_4 0x2800UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_4_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_4_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_5 0x3000UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_5_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_5_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_6 0x3800UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_6_SIZE 4 /* 0x4 */ - -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_6_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_7 0x4000UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_7_SIZE 4 /* 0x4 */ +/* fofb processing setpoints ram bank */ +#define WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK 0x800UL +#define WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_SIZE 4 /* 0x4 */ /* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_7_DATA 0x0UL - -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_8 0x4800UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_8_SIZE 4 /* 0x4 */ +#define WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_DATA 0x0UL /* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_8_DATA 0x0UL +#define WB_FOFB_PROCESSING_REGS_CH 0x1000UL +#define WB_FOFB_PROCESSING_REGS_CH_SIZE 4096 /* 0x1000 = 4KB */ -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_9 0x5000UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_9_SIZE 4 /* 0x4 */ +/* fofb processing coefficients ram bank (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_COEFF_RAM_BANK 0x0UL +#define WB_FOFB_PROCESSING_REGS_CH_COEFF_RAM_BANK_SIZE 4 /* 0x4 */ /* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_9_DATA 0x0UL +#define WB_FOFB_PROCESSING_REGS_CH_COEFF_RAM_BANK_DATA 0x0UL -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_10 0x5800UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_10_SIZE 4 /* 0x4 */ +/* fofb processing accumulator registers (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_ACC 0x800UL +#define WB_FOFB_PROCESSING_REGS_CH_ACC_SIZE 64 /* 0x40 */ -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_10_DATA 0x0UL +/* fofb processing accumulator control register (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_ACC_CTL 0x800UL +#define WB_FOFB_PROCESSING_REGS_CH_ACC_CTL_CLEAR 0x1UL +#define WB_FOFB_PROCESSING_REGS_CH_ACC_CTL_FREEZE 0x2UL -/* fofb processing coefficients ram bank */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_11 0x6000UL -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_11_SIZE 4 /* 0x4 */ +/* fofb processing accumulator gain register (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_ACC_GAIN 0x804UL +#define WB_FOFB_PROCESSING_REGS_CH_ACC_GAIN_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_CH_ACC_GAIN_VAL_SHIFT 0 -/* None */ -#define WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_11_DATA 0x0UL +/* fofb processing saturation limits registers (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS 0x840UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_SIZE 8 /* 0x8 */ -/* fofb processing setpoints ram bank */ -#define WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK 0x6800UL -#define WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_SIZE 4 /* 0x4 */ +/* fofb processing maximum saturation value register (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX 0x840UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX_VAL_SHIFT 0 -/* None */ -#define WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_DATA 0x0UL +/* fofb processing minimum saturation value register (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN 0x844UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN_VAL_SHIFT 0 struct wb_fofb_processing_regs { - /* [0x0]: REG (rw) fofb processing coefficients fixed-point position constant */ - uint32_t coeffs_fixed_point_pos; - - /* [0x4]: REG (ro) fofb processing accumulators' gains fixed-point position register */ - uint32_t accs_gains_fixed_point_pos; - - /* [0x8]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_0; - - /* [0xc]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_0; - - /* [0x10]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_1; - - /* [0x14]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_1; - - /* [0x18]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_2; - - /* [0x1c]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_2; - - /* [0x20]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_3; - - /* [0x24]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_3; - - /* [0x28]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_4; - - /* [0x2c]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_4; - - /* [0x30]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_5; - - /* [0x34]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_5; - - /* [0x38]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_6; - - /* [0x3c]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_6; - - /* [0x40]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_7; - - /* [0x44]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_7; - - /* [0x48]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_8; - - /* [0x4c]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_8; - - /* [0x50]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_9; - - /* [0x54]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_9; - - /* [0x58]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_10; - - /* [0x5c]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_10; - - /* [0x60]: REG (rw) fofb processing accumulator gain register (per channel) */ - uint32_t acc_gain_11; - - /* [0x64]: REG (rw) fofb processing accumulator control register (per channel) */ - uint32_t acc_ctl_11; - - /* [0x68]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_0; - - /* [0x6c]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_0; - - /* [0x70]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_1; - - /* [0x74]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_1; - - /* [0x78]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_2; - - /* [0x7c]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_2; + /* [0x0]: BLOCK fofb processing fixed-point position constants */ + struct fixed_point_pos { + /* [0x0]: REG (ro) fofb processing coefficients fixed-point position constant */ + uint32_t coeff; - /* [0x80]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_3; + /* [0x4]: REG (ro) fofb processing accumulators' gains fixed-point position register */ + uint32_t accs_gains; - /* [0x84]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_3; + /* padding to: 1 words */ + uint32_t __padding_0[14]; + } fixed_point_pos; - /* [0x88]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_4; + /* [0x40]: BLOCK fofb processing loop interlock registers */ + struct loop_intlk { + /* [0x0]: REG (rw) fofb processing loop interlock control register */ + uint32_t ctl; - /* [0x8c]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_4; + /* [0x4]: REG (ro) fofb processing loop interlock status register */ + uint32_t sta; - /* [0x90]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_5; + /* [0x8]: REG (rw) fofb processing loop interlock orbit distortion limit value register */ + uint32_t orb_distort_limit; - /* [0x94]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_5; + /* [0xc]: REG (rw) fofb processing loop interlock minimum number of packets per timeframe value register */ + uint32_t min_num_pkts; - /* [0x98]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_6; - - /* [0x9c]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_6; - - /* [0xa0]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_7; - - /* [0xa4]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_7; - - /* [0xa8]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_8; - - /* [0xac]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_8; - - /* [0xb0]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_9; - - /* [0xb4]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_9; - - /* [0xb8]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_10; - - /* [0xbc]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_10; - - /* [0xc0]: REG (rw) fofb processing maximum saturation value register (per channel) */ - uint32_t sp_max_11; - - /* [0xc4]: REG (rw) fofb processing minimum saturation value register (per channel) */ - uint32_t sp_min_11; - - /* [0xc8]: REG (rw) fofb processing loop interlock sources enable control register */ - uint32_t loop_intlk_src_en_ctl; - - /* [0xcc]: REG (rw) fofb processing loop interlock control register */ - uint32_t loop_intlk_ctl; - - /* [0xd0]: REG (rw) fofb processing loop interlock status register */ - uint32_t loop_intlk_sta; - - /* [0xd4]: REG (rw) fofb processing loop interlock orbit distortion limit value register */ - uint32_t orb_distort_limit; - - /* [0xd8]: REG (rw) fofb processing loop interlock minimum number of packets per timeframe value register */ - uint32_t min_num_pkts; + /* padding to: 3 words */ + uint32_t __padding_0[12]; + } loop_intlk; /* padding to: 512 words */ - uint32_t __padding_0[457]; - - /* [0x800]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_0 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_0[512]; - - /* [0x1000]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_1 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_1[512]; - - /* [0x1800]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_2 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_2[512]; - - /* [0x2000]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_3 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_3[512]; - - /* [0x2800]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_4 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_4[512]; - - /* [0x3000]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_5 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_5[512]; - - /* [0x3800]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_6 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_6[512]; - - /* [0x4000]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_7 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_7[512]; - - /* [0x4800]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_8 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_8[512]; - - /* [0x5000]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_9 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_9[512]; - - /* [0x5800]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_10 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_10[512]; - - /* [0x6000]: MEMORY fofb processing coefficients ram bank */ - struct coeffs_ram_bank_11 { - /* [0x0]: REG (rw) (no description) */ - uint32_t data; - } coeffs_ram_bank_11[512]; + uint32_t __padding_0[480]; - /* [0x6800]: MEMORY fofb processing setpoints ram bank */ - struct setpoints_ram_bank { + /* [0x800]: MEMORY fofb processing setpoints ram bank */ + struct sps_ram_bank { /* [0x0]: REG (rw) (no description) */ uint32_t data; - } setpoints_ram_bank[512]; + } sps_ram_bank[512]; + + /* [0x1000]: REPEAT (no description) */ + struct ch { + /* [0x0]: MEMORY fofb processing coefficients ram bank (per channel) */ + struct coeff_ram_bank { + /* [0x0]: REG (rw) (no description) */ + uint32_t data; + } coeff_ram_bank[512]; + + /* [0x800]: BLOCK fofb processing accumulator registers (per channel) */ + struct acc { + /* [0x0]: REG (rw) fofb processing accumulator control register (per channel) */ + uint32_t ctl; + + /* [0x4]: REG (rw) fofb processing accumulator gain register (per channel) */ + uint32_t gain; + + /* padding to: 1 words */ + uint32_t __padding_0[14]; + } acc; + + /* [0x840]: BLOCK fofb processing saturation limits registers (per channel) */ + struct sp_limits { + /* [0x0]: REG (rw) fofb processing maximum saturation value register (per channel) */ + uint32_t max; + + /* [0x4]: REG (rw) fofb processing minimum saturation value register (per channel) */ + uint32_t min; + } sp_limits; + + /* padding to: 528 words */ + uint32_t __padding_0[494]; + } ch[12]; }; #endif /* __CHEBY__WB_FOFB_PROCESSING_REGS__H__ */ diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd index 3cc0aa36..720f4942 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd @@ -1,3837 +1,2999 @@ -------------------------------------------------------------------------------- --- Title : Wishbone slave core for interface to internal regs and coefficient ram banks -------------------------------------------------------------------------------- --- File : wb_fofb_processing_regs.vhdl --- Author : auto-generated by wbgen2 from wb_fofb_processing_regs.wb --- Created : Mon Nov 07 08:28:21 2022 --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fofb_processing_regs.wb --- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -------------------------------------------------------------------------------- +-- Do not edit. Generated on Tue Feb 14 18:19:12 2023 by guilherme.ricioli +-- With Cheby 1.4.0 and these options: +-- -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.wbgen2_pkg.all; +use work.wishbone_pkg.all; +use work.cheby_pkg.all; entity wb_fofb_processing_regs is port ( rst_n_i : in std_logic; - clk_sys_i : in std_logic; - wb_adr_i : in std_logic_vector(12 downto 0); - wb_dat_i : in std_logic_vector(31 downto 0); - wb_dat_o : out std_logic_vector(31 downto 0); - wb_cyc_i : in std_logic; - wb_sel_i : in std_logic_vector(3 downto 0); - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_ack_o : out std_logic; - wb_stall_o : out std_logic; - wb_fofb_processing_regs_clk_i : in std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'fixed-point position constant value' in reg: 'fofb processing coefficients fixed-point position constant' - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_i : in std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulators' gains fixed-point position register' - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_i : in std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_0_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_0_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_0_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_1_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_1_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_1_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_2_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_2_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_2_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_3_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_3_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_3_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_4_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_4_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_4_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_5_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_5_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_5_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_6_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_6_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_6_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_7_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_7_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_7_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_8_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_8_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_8_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_9_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_9_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_9_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_10_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_10_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_10_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing accumulator gain register (per channel)' - wb_fofb_processing_regs_acc_gain_11_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clear accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_11_clear_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'freeze accumulator bit' in reg: 'fofb processing accumulator control register (per channel)' - wb_fofb_processing_regs_acc_ctl_11_freeze_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_0_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_0_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_1_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_1_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_2_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_2_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_3_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_3_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_4_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_4_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_5_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_5_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_6_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_6_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_7_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_7_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_8_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_8_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_9_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_9_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_10_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_10_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing maximum saturation value register (per channel)' - wb_fofb_processing_regs_sp_max_11_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing minimum saturation value register (per channel)' - wb_fofb_processing_regs_sp_min_11_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'orbit distortion source enable' in reg: 'fofb processing loop interlock sources enable control register' - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'packet loss source enable' in reg: 'fofb processing loop interlock sources enable control register' - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) MONOSTABLE field: 'clears loop interlock status' in reg: 'fofb processing loop interlock control register' - wb_fofb_processing_regs_loop_intlk_ctl_clr_o : out std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'orbit distortion loop interlock flag' in reg: 'fofb processing loop interlock status register' - wb_fofb_processing_regs_loop_intlk_sta_orb_distort_i : in std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) BIT field: 'packet loss loop interlock flag' in reg: 'fofb processing loop interlock status register' - wb_fofb_processing_regs_loop_intlk_sta_packet_loss_i : in std_logic; - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing loop interlock orbit distortion limit value register' - wb_fofb_processing_regs_orb_distort_limit_val_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: wb_fofb_processing_regs_clk_i) std_logic_vector field: 'value' in reg: 'fofb processing loop interlock minimum number of packets per timeframe value register' - wb_fofb_processing_regs_min_num_pkts_val_o : out std_logic_vector(31 downto 0); - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_0_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_0_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_0_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_0_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_0_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_1_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_1_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_1_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_1_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_1_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_2_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_2_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_2_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_2_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_2_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_3_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_3_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_3_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_3_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_3_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_4_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_4_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_4_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_4_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_4_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_5_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_5_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_5_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_5_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_5_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_6_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_6_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_6_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_6_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_6_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_7_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_7_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_7_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_7_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_7_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_8_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_8_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_8_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_8_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_8_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_9_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_9_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_9_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_9_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_9_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_10_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_10_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_10_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_10_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_10_wr_i : in std_logic; - -- Ports for RAM: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_11_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_coeffs_ram_bank_11_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_coeffs_ram_bank_11_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_coeffs_ram_bank_11_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_coeffs_ram_bank_11_wr_i : in std_logic; - -- Ports for RAM: fofb processing setpoints ram bank - wb_fofb_processing_regs_setpoints_ram_bank_addr_i : in std_logic_vector(8 downto 0); - -- Read data output - wb_fofb_processing_regs_setpoints_ram_bank_data_o : out std_logic_vector(31 downto 0); - -- Read strobe input (active high) - wb_fofb_processing_regs_setpoints_ram_bank_rd_i : in std_logic; - -- Write data input - wb_fofb_processing_regs_setpoints_ram_bank_data_i : in std_logic_vector(31 downto 0); - -- Write strobe (active high) - wb_fofb_processing_regs_setpoints_ram_bank_wr_i : in std_logic + clk_i : in std_logic; + wb_i : in t_wishbone_slave_in; + wb_o : out t_wishbone_slave_out; + + -- fofb processing coefficients fixed-point position constant + -- fixed-point position constant value + fixed_point_pos_coeff_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing accumulators' gains fixed-point position register + -- value + fixed_point_pos_accs_gains_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing loop interlock control register + -- write 0: no effect + -- write 1: clears loop interlock status (this bit autoclears) + loop_intlk_ctl_sta_clr_o : out std_logic; + -- write 0: disables source + -- write 1: enables source + loop_intlk_ctl_src_en_orb_distort_o : out std_logic; + -- write 0: disables source + -- write 1: enables source + loop_intlk_ctl_src_en_packet_loss_o : out std_logic; + + -- fofb processing loop interlock status register + -- read 0: not interlocked + -- read 1: interlocked + loop_intlk_sta_orb_distort_i : in std_logic; + -- read 0: not interlocked + -- read 1: interlocked + loop_intlk_sta_packet_loss_i : in std_logic; + + -- fofb processing loop interlock orbit distortion limit value register + -- value + loop_intlk_orb_distort_limit_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing loop interlock minimum number of packets per timeframe value register + -- value + loop_intlk_min_num_pkts_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for sps_ram_bank + sps_ram_bank_adr_i : in std_logic_vector(8 downto 0); + sps_ram_bank_data_rd_i : in std_logic; + sps_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_0_coeff_ram_bank + ch_0_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_0_coeff_ram_bank_data_rd_i : in std_logic; + ch_0_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_0_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_0_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_0_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_0_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_0_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_1_coeff_ram_bank + ch_1_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_1_coeff_ram_bank_data_rd_i : in std_logic; + ch_1_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_1_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_1_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_1_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_1_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_1_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_2_coeff_ram_bank + ch_2_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_2_coeff_ram_bank_data_rd_i : in std_logic; + ch_2_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_2_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_2_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_2_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_2_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_2_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_3_coeff_ram_bank + ch_3_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_3_coeff_ram_bank_data_rd_i : in std_logic; + ch_3_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_3_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_3_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_3_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_3_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_3_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_4_coeff_ram_bank + ch_4_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_4_coeff_ram_bank_data_rd_i : in std_logic; + ch_4_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_4_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_4_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_4_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_4_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_4_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_5_coeff_ram_bank + ch_5_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_5_coeff_ram_bank_data_rd_i : in std_logic; + ch_5_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_5_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_5_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_5_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_5_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_5_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_6_coeff_ram_bank + ch_6_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_6_coeff_ram_bank_data_rd_i : in std_logic; + ch_6_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_6_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_6_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_6_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_6_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_6_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_7_coeff_ram_bank + ch_7_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_7_coeff_ram_bank_data_rd_i : in std_logic; + ch_7_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_7_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_7_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_7_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_7_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_7_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_8_coeff_ram_bank + ch_8_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_8_coeff_ram_bank_data_rd_i : in std_logic; + ch_8_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_8_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_8_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_8_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_8_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_8_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_9_coeff_ram_bank + ch_9_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_9_coeff_ram_bank_data_rd_i : in std_logic; + ch_9_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_9_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_9_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_9_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_9_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_9_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_10_coeff_ram_bank + ch_10_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_10_coeff_ram_bank_data_rd_i : in std_logic; + ch_10_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_10_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_10_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_10_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_10_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_10_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- RAM port for ch_11_coeff_ram_bank + ch_11_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); + ch_11_coeff_ram_bank_data_rd_i : in std_logic; + ch_11_coeff_ram_bank_data_dat_o : out std_logic_vector(31 downto 0); + + -- fofb processing accumulator control register (per channel) + -- write 0: no effect + -- write 1: clears accumulator (this bit autoclears) + ch_11_acc_ctl_clear_o : out std_logic; + -- write 0: no effect on accumulator + -- write 1: freezes accumulator + ch_11_acc_ctl_freeze_o : out std_logic; + + -- fofb processing accumulator gain register (per channel) + -- value + ch_11_acc_gain_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing maximum saturation value register (per channel) + -- value + ch_11_sp_limits_max_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing minimum saturation value register (per channel) + -- value + ch_11_sp_limits_min_val_o : out std_logic_vector(31 downto 0) ); end wb_fofb_processing_regs; architecture syn of wb_fofb_processing_regs is + signal adr_int : std_logic_vector(15 downto 2); + signal rd_req_int : std_logic; + signal wr_req_int : std_logic; + signal rd_ack_int : std_logic; + signal wr_ack_int : std_logic; + signal wb_en : std_logic; + signal ack_int : std_logic; + signal wb_rip : std_logic; + signal wb_wip : std_logic; + signal loop_intlk_ctl_sta_clr_reg : std_logic; + signal loop_intlk_ctl_src_en_orb_distort_reg : std_logic; + signal loop_intlk_ctl_src_en_packet_loss_reg : std_logic; + signal loop_intlk_ctl_wreq : std_logic; + signal loop_intlk_ctl_wack : std_logic; + signal loop_intlk_orb_distort_limit_val_reg : std_logic_vector(31 downto 0); + signal loop_intlk_orb_distort_limit_wreq : std_logic; + signal loop_intlk_orb_distort_limit_wack : std_logic; + signal loop_intlk_min_num_pkts_val_reg : std_logic_vector(31 downto 0); + signal loop_intlk_min_num_pkts_wreq : std_logic; + signal loop_intlk_min_num_pkts_wack : std_logic; + signal sps_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal sps_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal sps_ram_bank_data_rreq : std_logic; + signal sps_ram_bank_data_rack : std_logic; + signal sps_ram_bank_data_int_wr : std_logic; + signal ch_0_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_0_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_0_coeff_ram_bank_data_rreq : std_logic; + signal ch_0_coeff_ram_bank_data_rack : std_logic; + signal ch_0_coeff_ram_bank_data_int_wr : std_logic; + signal ch_0_acc_ctl_clear_reg : std_logic; + signal ch_0_acc_ctl_freeze_reg : std_logic; + signal ch_0_acc_ctl_wreq : std_logic; + signal ch_0_acc_ctl_wack : std_logic; + signal ch_0_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_0_acc_gain_wreq : std_logic; + signal ch_0_acc_gain_wack : std_logic; + signal ch_0_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_0_sp_limits_max_wreq : std_logic; + signal ch_0_sp_limits_max_wack : std_logic; + signal ch_0_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_0_sp_limits_min_wreq : std_logic; + signal ch_0_sp_limits_min_wack : std_logic; + signal ch_1_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_1_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_1_coeff_ram_bank_data_rreq : std_logic; + signal ch_1_coeff_ram_bank_data_rack : std_logic; + signal ch_1_coeff_ram_bank_data_int_wr : std_logic; + signal ch_1_acc_ctl_clear_reg : std_logic; + signal ch_1_acc_ctl_freeze_reg : std_logic; + signal ch_1_acc_ctl_wreq : std_logic; + signal ch_1_acc_ctl_wack : std_logic; + signal ch_1_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_1_acc_gain_wreq : std_logic; + signal ch_1_acc_gain_wack : std_logic; + signal ch_1_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_1_sp_limits_max_wreq : std_logic; + signal ch_1_sp_limits_max_wack : std_logic; + signal ch_1_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_1_sp_limits_min_wreq : std_logic; + signal ch_1_sp_limits_min_wack : std_logic; + signal ch_2_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_2_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_2_coeff_ram_bank_data_rreq : std_logic; + signal ch_2_coeff_ram_bank_data_rack : std_logic; + signal ch_2_coeff_ram_bank_data_int_wr : std_logic; + signal ch_2_acc_ctl_clear_reg : std_logic; + signal ch_2_acc_ctl_freeze_reg : std_logic; + signal ch_2_acc_ctl_wreq : std_logic; + signal ch_2_acc_ctl_wack : std_logic; + signal ch_2_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_2_acc_gain_wreq : std_logic; + signal ch_2_acc_gain_wack : std_logic; + signal ch_2_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_2_sp_limits_max_wreq : std_logic; + signal ch_2_sp_limits_max_wack : std_logic; + signal ch_2_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_2_sp_limits_min_wreq : std_logic; + signal ch_2_sp_limits_min_wack : std_logic; + signal ch_3_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_3_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_3_coeff_ram_bank_data_rreq : std_logic; + signal ch_3_coeff_ram_bank_data_rack : std_logic; + signal ch_3_coeff_ram_bank_data_int_wr : std_logic; + signal ch_3_acc_ctl_clear_reg : std_logic; + signal ch_3_acc_ctl_freeze_reg : std_logic; + signal ch_3_acc_ctl_wreq : std_logic; + signal ch_3_acc_ctl_wack : std_logic; + signal ch_3_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_3_acc_gain_wreq : std_logic; + signal ch_3_acc_gain_wack : std_logic; + signal ch_3_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_3_sp_limits_max_wreq : std_logic; + signal ch_3_sp_limits_max_wack : std_logic; + signal ch_3_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_3_sp_limits_min_wreq : std_logic; + signal ch_3_sp_limits_min_wack : std_logic; + signal ch_4_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_4_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_4_coeff_ram_bank_data_rreq : std_logic; + signal ch_4_coeff_ram_bank_data_rack : std_logic; + signal ch_4_coeff_ram_bank_data_int_wr : std_logic; + signal ch_4_acc_ctl_clear_reg : std_logic; + signal ch_4_acc_ctl_freeze_reg : std_logic; + signal ch_4_acc_ctl_wreq : std_logic; + signal ch_4_acc_ctl_wack : std_logic; + signal ch_4_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_4_acc_gain_wreq : std_logic; + signal ch_4_acc_gain_wack : std_logic; + signal ch_4_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_4_sp_limits_max_wreq : std_logic; + signal ch_4_sp_limits_max_wack : std_logic; + signal ch_4_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_4_sp_limits_min_wreq : std_logic; + signal ch_4_sp_limits_min_wack : std_logic; + signal ch_5_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_5_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_5_coeff_ram_bank_data_rreq : std_logic; + signal ch_5_coeff_ram_bank_data_rack : std_logic; + signal ch_5_coeff_ram_bank_data_int_wr : std_logic; + signal ch_5_acc_ctl_clear_reg : std_logic; + signal ch_5_acc_ctl_freeze_reg : std_logic; + signal ch_5_acc_ctl_wreq : std_logic; + signal ch_5_acc_ctl_wack : std_logic; + signal ch_5_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_5_acc_gain_wreq : std_logic; + signal ch_5_acc_gain_wack : std_logic; + signal ch_5_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_5_sp_limits_max_wreq : std_logic; + signal ch_5_sp_limits_max_wack : std_logic; + signal ch_5_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_5_sp_limits_min_wreq : std_logic; + signal ch_5_sp_limits_min_wack : std_logic; + signal ch_6_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_6_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_6_coeff_ram_bank_data_rreq : std_logic; + signal ch_6_coeff_ram_bank_data_rack : std_logic; + signal ch_6_coeff_ram_bank_data_int_wr : std_logic; + signal ch_6_acc_ctl_clear_reg : std_logic; + signal ch_6_acc_ctl_freeze_reg : std_logic; + signal ch_6_acc_ctl_wreq : std_logic; + signal ch_6_acc_ctl_wack : std_logic; + signal ch_6_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_6_acc_gain_wreq : std_logic; + signal ch_6_acc_gain_wack : std_logic; + signal ch_6_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_6_sp_limits_max_wreq : std_logic; + signal ch_6_sp_limits_max_wack : std_logic; + signal ch_6_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_6_sp_limits_min_wreq : std_logic; + signal ch_6_sp_limits_min_wack : std_logic; + signal ch_7_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_7_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_7_coeff_ram_bank_data_rreq : std_logic; + signal ch_7_coeff_ram_bank_data_rack : std_logic; + signal ch_7_coeff_ram_bank_data_int_wr : std_logic; + signal ch_7_acc_ctl_clear_reg : std_logic; + signal ch_7_acc_ctl_freeze_reg : std_logic; + signal ch_7_acc_ctl_wreq : std_logic; + signal ch_7_acc_ctl_wack : std_logic; + signal ch_7_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_7_acc_gain_wreq : std_logic; + signal ch_7_acc_gain_wack : std_logic; + signal ch_7_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_7_sp_limits_max_wreq : std_logic; + signal ch_7_sp_limits_max_wack : std_logic; + signal ch_7_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_7_sp_limits_min_wreq : std_logic; + signal ch_7_sp_limits_min_wack : std_logic; + signal ch_8_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_8_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_8_coeff_ram_bank_data_rreq : std_logic; + signal ch_8_coeff_ram_bank_data_rack : std_logic; + signal ch_8_coeff_ram_bank_data_int_wr : std_logic; + signal ch_8_acc_ctl_clear_reg : std_logic; + signal ch_8_acc_ctl_freeze_reg : std_logic; + signal ch_8_acc_ctl_wreq : std_logic; + signal ch_8_acc_ctl_wack : std_logic; + signal ch_8_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_8_acc_gain_wreq : std_logic; + signal ch_8_acc_gain_wack : std_logic; + signal ch_8_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_8_sp_limits_max_wreq : std_logic; + signal ch_8_sp_limits_max_wack : std_logic; + signal ch_8_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_8_sp_limits_min_wreq : std_logic; + signal ch_8_sp_limits_min_wack : std_logic; + signal ch_9_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_9_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_9_coeff_ram_bank_data_rreq : std_logic; + signal ch_9_coeff_ram_bank_data_rack : std_logic; + signal ch_9_coeff_ram_bank_data_int_wr : std_logic; + signal ch_9_acc_ctl_clear_reg : std_logic; + signal ch_9_acc_ctl_freeze_reg : std_logic; + signal ch_9_acc_ctl_wreq : std_logic; + signal ch_9_acc_ctl_wack : std_logic; + signal ch_9_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_9_acc_gain_wreq : std_logic; + signal ch_9_acc_gain_wack : std_logic; + signal ch_9_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_9_sp_limits_max_wreq : std_logic; + signal ch_9_sp_limits_max_wack : std_logic; + signal ch_9_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_9_sp_limits_min_wreq : std_logic; + signal ch_9_sp_limits_min_wack : std_logic; + signal ch_10_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_10_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_10_coeff_ram_bank_data_rreq : std_logic; + signal ch_10_coeff_ram_bank_data_rack : std_logic; + signal ch_10_coeff_ram_bank_data_int_wr : std_logic; + signal ch_10_acc_ctl_clear_reg : std_logic; + signal ch_10_acc_ctl_freeze_reg : std_logic; + signal ch_10_acc_ctl_wreq : std_logic; + signal ch_10_acc_ctl_wack : std_logic; + signal ch_10_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_10_acc_gain_wreq : std_logic; + signal ch_10_acc_gain_wack : std_logic; + signal ch_10_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_10_sp_limits_max_wreq : std_logic; + signal ch_10_sp_limits_max_wack : std_logic; + signal ch_10_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_10_sp_limits_min_wreq : std_logic; + signal ch_10_sp_limits_min_wack : std_logic; + signal ch_11_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); + signal ch_11_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); + signal ch_11_coeff_ram_bank_data_rreq : std_logic; + signal ch_11_coeff_ram_bank_data_rack : std_logic; + signal ch_11_coeff_ram_bank_data_int_wr : std_logic; + signal ch_11_acc_ctl_clear_reg : std_logic; + signal ch_11_acc_ctl_freeze_reg : std_logic; + signal ch_11_acc_ctl_wreq : std_logic; + signal ch_11_acc_ctl_wack : std_logic; + signal ch_11_acc_gain_val_reg : std_logic_vector(31 downto 0); + signal ch_11_acc_gain_wreq : std_logic; + signal ch_11_acc_gain_wack : std_logic; + signal ch_11_sp_limits_max_val_reg : std_logic_vector(31 downto 0); + signal ch_11_sp_limits_max_wreq : std_logic; + signal ch_11_sp_limits_max_wack : std_logic; + signal ch_11_sp_limits_min_val_reg : std_logic_vector(31 downto 0); + signal ch_11_sp_limits_min_wreq : std_logic; + signal ch_11_sp_limits_min_wack : std_logic; + signal rd_ack_d0 : std_logic; + signal rd_dat_d0 : std_logic_vector(31 downto 0); + signal wr_req_d0 : std_logic; + signal wr_adr_d0 : std_logic_vector(15 downto 2); + signal wr_dat_d0 : std_logic_vector(31 downto 0); + signal wr_sel_d0 : std_logic_vector(3 downto 0); + signal sps_ram_bank_wr : std_logic; + signal sps_ram_bank_rr : std_logic; + signal sps_ram_bank_wreq : std_logic; + signal sps_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_0_coeff_ram_bank_wr : std_logic; + signal ch_0_coeff_ram_bank_rr : std_logic; + signal ch_0_coeff_ram_bank_wreq : std_logic; + signal ch_0_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_1_coeff_ram_bank_wr : std_logic; + signal ch_1_coeff_ram_bank_rr : std_logic; + signal ch_1_coeff_ram_bank_wreq : std_logic; + signal ch_1_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_2_coeff_ram_bank_wr : std_logic; + signal ch_2_coeff_ram_bank_rr : std_logic; + signal ch_2_coeff_ram_bank_wreq : std_logic; + signal ch_2_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_3_coeff_ram_bank_wr : std_logic; + signal ch_3_coeff_ram_bank_rr : std_logic; + signal ch_3_coeff_ram_bank_wreq : std_logic; + signal ch_3_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_4_coeff_ram_bank_wr : std_logic; + signal ch_4_coeff_ram_bank_rr : std_logic; + signal ch_4_coeff_ram_bank_wreq : std_logic; + signal ch_4_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_5_coeff_ram_bank_wr : std_logic; + signal ch_5_coeff_ram_bank_rr : std_logic; + signal ch_5_coeff_ram_bank_wreq : std_logic; + signal ch_5_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_6_coeff_ram_bank_wr : std_logic; + signal ch_6_coeff_ram_bank_rr : std_logic; + signal ch_6_coeff_ram_bank_wreq : std_logic; + signal ch_6_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_7_coeff_ram_bank_wr : std_logic; + signal ch_7_coeff_ram_bank_rr : std_logic; + signal ch_7_coeff_ram_bank_wreq : std_logic; + signal ch_7_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_8_coeff_ram_bank_wr : std_logic; + signal ch_8_coeff_ram_bank_rr : std_logic; + signal ch_8_coeff_ram_bank_wreq : std_logic; + signal ch_8_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_9_coeff_ram_bank_wr : std_logic; + signal ch_9_coeff_ram_bank_rr : std_logic; + signal ch_9_coeff_ram_bank_wreq : std_logic; + signal ch_9_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_10_coeff_ram_bank_wr : std_logic; + signal ch_10_coeff_ram_bank_rr : std_logic; + signal ch_10_coeff_ram_bank_wreq : std_logic; + signal ch_10_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); + signal ch_11_coeff_ram_bank_wr : std_logic; + signal ch_11_coeff_ram_bank_rr : std_logic; + signal ch_11_coeff_ram_bank_wreq : std_logic; + signal ch_11_coeff_ram_bank_adr_int : std_logic_vector(8 downto 0); +begin - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb : std_logic; - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_delay : std_logic; - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_in_progress : std_logic; - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s0 : std_logic; - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s1 : std_logic; - signal wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s2 : std_logic; - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb : std_logic; - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_delay : std_logic; - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_in_progress : std_logic; - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s0 : std_logic; - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s1 : std_logic; - signal wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_gain_0_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_0_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_0_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_0_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_0_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_0_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_0_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_1_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_1_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_1_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_1_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_1_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_1_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_1_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_2_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_2_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_2_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_2_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_2_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_2_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_2_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_3_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_3_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_3_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_3_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_3_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_3_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_3_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_4_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_4_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_4_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_4_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_4_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_4_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_4_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_5_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_5_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_5_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_5_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_5_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_5_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_5_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_6_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_6_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_6_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_6_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_6_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_6_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_6_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_7_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_7_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_7_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_7_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_7_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_7_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_7_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_8_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_8_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_8_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_8_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_8_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_8_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_8_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_9_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_9_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_9_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_9_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_9_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_9_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_9_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_10_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_10_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_10_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_10_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_10_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_10_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_10_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_11_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_acc_gain_11_val_swb : std_logic; - signal wb_fofb_processing_regs_acc_gain_11_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_acc_gain_11_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_acc_gain_11_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_acc_gain_11_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_clear_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_clear_int_delay : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_clear_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_clear_sync1 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_clear_sync2 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_freeze_int : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_freeze_sync0 : std_logic; - signal wb_fofb_processing_regs_acc_ctl_11_freeze_sync1 : std_logic; - signal wb_fofb_processing_regs_sp_max_0_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_0_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_0_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_0_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_0_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_0_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_0_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_0_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_0_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_0_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_0_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_0_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_1_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_1_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_1_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_1_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_1_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_1_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_1_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_1_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_1_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_1_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_1_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_1_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_2_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_2_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_2_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_2_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_2_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_2_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_2_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_2_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_2_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_2_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_2_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_2_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_3_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_3_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_3_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_3_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_3_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_3_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_3_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_3_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_3_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_3_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_3_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_3_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_4_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_4_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_4_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_4_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_4_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_4_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_4_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_4_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_4_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_4_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_4_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_4_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_5_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_5_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_5_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_5_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_5_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_5_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_5_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_5_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_5_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_5_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_5_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_5_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_6_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_6_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_6_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_6_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_6_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_6_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_6_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_6_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_6_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_6_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_6_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_6_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_7_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_7_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_7_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_7_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_7_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_7_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_7_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_7_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_7_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_7_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_7_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_7_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_8_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_8_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_8_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_8_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_8_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_8_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_8_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_8_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_8_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_8_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_8_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_8_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_9_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_9_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_9_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_9_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_9_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_9_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_9_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_9_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_9_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_9_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_9_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_9_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_10_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_10_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_10_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_10_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_10_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_10_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_10_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_10_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_10_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_10_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_10_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_10_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_max_11_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_max_11_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_max_11_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_max_11_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_max_11_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_max_11_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_sp_min_11_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_sp_min_11_val_swb : std_logic; - signal wb_fofb_processing_regs_sp_min_11_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_sp_min_11_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_sp_min_11_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_sp_min_11_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_int : std_logic; - signal wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync0 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync1 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_int : std_logic; - signal wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync0 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync1 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_ctl_clr_int : std_logic; - signal wb_fofb_processing_regs_loop_intlk_ctl_clr_int_delay : std_logic; - signal wb_fofb_processing_regs_loop_intlk_ctl_clr_sync0 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_ctl_clr_sync1 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_ctl_clr_sync2 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync0 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync1 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync0 : std_logic; - signal wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync1 : std_logic; - signal wb_fofb_processing_regs_orb_distort_limit_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_orb_distort_limit_val_swb : std_logic; - signal wb_fofb_processing_regs_orb_distort_limit_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_orb_distort_limit_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_orb_distort_limit_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_orb_distort_limit_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_min_num_pkts_val_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_min_num_pkts_val_swb : std_logic; - signal wb_fofb_processing_regs_min_num_pkts_val_swb_delay : std_logic; - signal wb_fofb_processing_regs_min_num_pkts_val_swb_s0 : std_logic; - signal wb_fofb_processing_regs_min_num_pkts_val_swb_s1 : std_logic; - signal wb_fofb_processing_regs_min_num_pkts_val_swb_s2 : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_0_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_0_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_0_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_1_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_1_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_1_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_2_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_2_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_2_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_3_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_3_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_3_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_4_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_4_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_4_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_5_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_5_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_5_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_6_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_6_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_6_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_7_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_7_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_7_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_8_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_8_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_8_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_9_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_9_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_9_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_10_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_10_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_10_wr_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_11_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_coeffs_ram_bank_11_rd_int : std_logic; - signal wb_fofb_processing_regs_coeffs_ram_bank_11_wr_int : std_logic; - signal wb_fofb_processing_regs_setpoints_ram_bank_rddata_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_regs_setpoints_ram_bank_rd_int : std_logic; - signal wb_fofb_processing_regs_setpoints_ram_bank_wr_int : std_logic; - signal ack_sreg : std_logic_vector(9 downto 0); - signal rddata_reg : std_logic_vector(31 downto 0); - signal wrdata_reg : std_logic_vector(31 downto 0); - signal bwsel_reg : std_logic_vector(3 downto 0); - signal rwaddr_reg : std_logic_vector(12 downto 0); - signal ack_in_progress : std_logic; - signal wr_int : std_logic; - signal rd_int : std_logic; - signal allones : std_logic_vector(31 downto 0); - signal allzeros : std_logic_vector(31 downto 0); + -- WB decode signals + adr_int <= wb_i.adr(15 downto 2); + wb_en <= wb_i.cyc and wb_i.stb; -begin - -- Some internal signals assignments. For (foreseen) compatibility with other bus standards. - wrdata_reg <= wb_dat_i; - bwsel_reg <= wb_sel_i; - rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); - wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); - allones <= (others => '1'); - allzeros <= (others => '0'); - -- - -- Main register bank access process. - process (clk_sys_i, rst_n_i) - begin - if (rst_n_i = '0') then - ack_sreg <= "0000000000"; - ack_in_progress <= '0'; - rddata_reg <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb <= '0'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_delay <= '0'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_in_progress <= '0'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb <= '0'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_delay <= '0'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_in_progress <= '0'; - wb_fofb_processing_regs_acc_gain_0_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_0_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_0_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_0_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_0_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_0_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_1_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_1_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_1_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_1_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_1_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_1_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_2_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_2_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_2_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_2_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_2_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_2_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_3_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_3_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_3_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_3_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_3_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_3_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_4_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_4_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_4_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_4_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_4_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_4_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_5_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_5_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_5_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_5_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_5_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_5_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_6_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_6_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_6_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_6_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_6_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_6_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_7_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_7_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_7_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_7_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_7_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_7_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_8_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_8_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_8_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_8_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_8_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_8_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_9_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_9_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_9_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_9_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_9_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_9_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_10_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_10_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_10_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_10_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_10_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_10_freeze_int <= '0'; - wb_fofb_processing_regs_acc_gain_11_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_acc_gain_11_val_swb <= '0'; - wb_fofb_processing_regs_acc_gain_11_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_11_clear_int <= '0'; - wb_fofb_processing_regs_acc_ctl_11_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_11_freeze_int <= '0'; - wb_fofb_processing_regs_sp_max_0_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_0_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_0_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_0_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_0_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_0_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_1_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_1_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_1_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_1_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_1_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_1_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_2_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_2_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_2_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_2_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_2_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_2_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_3_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_3_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_3_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_3_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_3_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_3_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_4_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_4_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_4_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_4_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_4_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_4_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_5_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_5_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_5_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_5_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_5_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_5_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_6_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_6_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_6_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_6_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_6_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_6_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_7_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_7_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_7_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_7_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_7_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_7_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_8_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_8_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_8_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_8_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_8_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_8_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_9_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_9_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_9_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_9_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_9_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_9_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_10_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_10_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_10_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_10_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_10_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_10_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_11_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_max_11_val_swb <= '0'; - wb_fofb_processing_regs_sp_max_11_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_11_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_sp_min_11_val_swb <= '0'; - wb_fofb_processing_regs_sp_min_11_val_swb_delay <= '0'; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_int <= '0'; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_int <= '0'; - wb_fofb_processing_regs_loop_intlk_ctl_clr_int <= '0'; - wb_fofb_processing_regs_loop_intlk_ctl_clr_int_delay <= '0'; - wb_fofb_processing_regs_orb_distort_limit_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_orb_distort_limit_val_swb <= '0'; - wb_fofb_processing_regs_orb_distort_limit_val_swb_delay <= '0'; - wb_fofb_processing_regs_min_num_pkts_val_int <= "00000000000000000000000000000000"; - wb_fofb_processing_regs_min_num_pkts_val_swb <= '0'; - wb_fofb_processing_regs_min_num_pkts_val_swb_delay <= '0'; - elsif rising_edge(clk_sys_i) then - -- advance the ACK generator shift register - ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); - ack_sreg(9) <= '0'; - if (ack_in_progress = '1') then - if (ack_sreg(0) = '1') then - ack_in_progress <= '0'; - else - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb <= wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_delay; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_delay <= '0'; - if ((ack_sreg(1) = '1') and (wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_in_progress = '1')) then - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_coeffs_fixed_point_pos_val_int; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_in_progress <= '0'; - end if; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb <= wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_delay; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_delay <= '0'; - if ((ack_sreg(1) = '1') and (wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_in_progress = '1')) then - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_int; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_in_progress <= '0'; - end if; - wb_fofb_processing_regs_acc_gain_0_val_swb <= wb_fofb_processing_regs_acc_gain_0_val_swb_delay; - wb_fofb_processing_regs_acc_gain_0_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_0_clear_int <= wb_fofb_processing_regs_acc_ctl_0_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_0_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_1_val_swb <= wb_fofb_processing_regs_acc_gain_1_val_swb_delay; - wb_fofb_processing_regs_acc_gain_1_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_1_clear_int <= wb_fofb_processing_regs_acc_ctl_1_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_1_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_2_val_swb <= wb_fofb_processing_regs_acc_gain_2_val_swb_delay; - wb_fofb_processing_regs_acc_gain_2_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_2_clear_int <= wb_fofb_processing_regs_acc_ctl_2_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_2_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_3_val_swb <= wb_fofb_processing_regs_acc_gain_3_val_swb_delay; - wb_fofb_processing_regs_acc_gain_3_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_3_clear_int <= wb_fofb_processing_regs_acc_ctl_3_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_3_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_4_val_swb <= wb_fofb_processing_regs_acc_gain_4_val_swb_delay; - wb_fofb_processing_regs_acc_gain_4_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_4_clear_int <= wb_fofb_processing_regs_acc_ctl_4_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_4_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_5_val_swb <= wb_fofb_processing_regs_acc_gain_5_val_swb_delay; - wb_fofb_processing_regs_acc_gain_5_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_5_clear_int <= wb_fofb_processing_regs_acc_ctl_5_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_5_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_6_val_swb <= wb_fofb_processing_regs_acc_gain_6_val_swb_delay; - wb_fofb_processing_regs_acc_gain_6_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_6_clear_int <= wb_fofb_processing_regs_acc_ctl_6_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_6_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_7_val_swb <= wb_fofb_processing_regs_acc_gain_7_val_swb_delay; - wb_fofb_processing_regs_acc_gain_7_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_7_clear_int <= wb_fofb_processing_regs_acc_ctl_7_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_7_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_8_val_swb <= wb_fofb_processing_regs_acc_gain_8_val_swb_delay; - wb_fofb_processing_regs_acc_gain_8_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_8_clear_int <= wb_fofb_processing_regs_acc_ctl_8_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_8_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_9_val_swb <= wb_fofb_processing_regs_acc_gain_9_val_swb_delay; - wb_fofb_processing_regs_acc_gain_9_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_9_clear_int <= wb_fofb_processing_regs_acc_ctl_9_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_9_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_10_val_swb <= wb_fofb_processing_regs_acc_gain_10_val_swb_delay; - wb_fofb_processing_regs_acc_gain_10_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_10_clear_int <= wb_fofb_processing_regs_acc_ctl_10_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_10_clear_int_delay <= '0'; - wb_fofb_processing_regs_acc_gain_11_val_swb <= wb_fofb_processing_regs_acc_gain_11_val_swb_delay; - wb_fofb_processing_regs_acc_gain_11_val_swb_delay <= '0'; - wb_fofb_processing_regs_acc_ctl_11_clear_int <= wb_fofb_processing_regs_acc_ctl_11_clear_int_delay; - wb_fofb_processing_regs_acc_ctl_11_clear_int_delay <= '0'; - wb_fofb_processing_regs_sp_max_0_val_swb <= wb_fofb_processing_regs_sp_max_0_val_swb_delay; - wb_fofb_processing_regs_sp_max_0_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_0_val_swb <= wb_fofb_processing_regs_sp_min_0_val_swb_delay; - wb_fofb_processing_regs_sp_min_0_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_1_val_swb <= wb_fofb_processing_regs_sp_max_1_val_swb_delay; - wb_fofb_processing_regs_sp_max_1_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_1_val_swb <= wb_fofb_processing_regs_sp_min_1_val_swb_delay; - wb_fofb_processing_regs_sp_min_1_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_2_val_swb <= wb_fofb_processing_regs_sp_max_2_val_swb_delay; - wb_fofb_processing_regs_sp_max_2_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_2_val_swb <= wb_fofb_processing_regs_sp_min_2_val_swb_delay; - wb_fofb_processing_regs_sp_min_2_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_3_val_swb <= wb_fofb_processing_regs_sp_max_3_val_swb_delay; - wb_fofb_processing_regs_sp_max_3_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_3_val_swb <= wb_fofb_processing_regs_sp_min_3_val_swb_delay; - wb_fofb_processing_regs_sp_min_3_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_4_val_swb <= wb_fofb_processing_regs_sp_max_4_val_swb_delay; - wb_fofb_processing_regs_sp_max_4_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_4_val_swb <= wb_fofb_processing_regs_sp_min_4_val_swb_delay; - wb_fofb_processing_regs_sp_min_4_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_5_val_swb <= wb_fofb_processing_regs_sp_max_5_val_swb_delay; - wb_fofb_processing_regs_sp_max_5_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_5_val_swb <= wb_fofb_processing_regs_sp_min_5_val_swb_delay; - wb_fofb_processing_regs_sp_min_5_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_6_val_swb <= wb_fofb_processing_regs_sp_max_6_val_swb_delay; - wb_fofb_processing_regs_sp_max_6_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_6_val_swb <= wb_fofb_processing_regs_sp_min_6_val_swb_delay; - wb_fofb_processing_regs_sp_min_6_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_7_val_swb <= wb_fofb_processing_regs_sp_max_7_val_swb_delay; - wb_fofb_processing_regs_sp_max_7_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_7_val_swb <= wb_fofb_processing_regs_sp_min_7_val_swb_delay; - wb_fofb_processing_regs_sp_min_7_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_8_val_swb <= wb_fofb_processing_regs_sp_max_8_val_swb_delay; - wb_fofb_processing_regs_sp_max_8_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_8_val_swb <= wb_fofb_processing_regs_sp_min_8_val_swb_delay; - wb_fofb_processing_regs_sp_min_8_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_9_val_swb <= wb_fofb_processing_regs_sp_max_9_val_swb_delay; - wb_fofb_processing_regs_sp_max_9_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_9_val_swb <= wb_fofb_processing_regs_sp_min_9_val_swb_delay; - wb_fofb_processing_regs_sp_min_9_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_10_val_swb <= wb_fofb_processing_regs_sp_max_10_val_swb_delay; - wb_fofb_processing_regs_sp_max_10_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_10_val_swb <= wb_fofb_processing_regs_sp_min_10_val_swb_delay; - wb_fofb_processing_regs_sp_min_10_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_max_11_val_swb <= wb_fofb_processing_regs_sp_max_11_val_swb_delay; - wb_fofb_processing_regs_sp_max_11_val_swb_delay <= '0'; - wb_fofb_processing_regs_sp_min_11_val_swb <= wb_fofb_processing_regs_sp_min_11_val_swb_delay; - wb_fofb_processing_regs_sp_min_11_val_swb_delay <= '0'; - wb_fofb_processing_regs_loop_intlk_ctl_clr_int <= wb_fofb_processing_regs_loop_intlk_ctl_clr_int_delay; - wb_fofb_processing_regs_loop_intlk_ctl_clr_int_delay <= '0'; - wb_fofb_processing_regs_orb_distort_limit_val_swb <= wb_fofb_processing_regs_orb_distort_limit_val_swb_delay; - wb_fofb_processing_regs_orb_distort_limit_val_swb_delay <= '0'; - wb_fofb_processing_regs_min_num_pkts_val_swb <= wb_fofb_processing_regs_min_num_pkts_val_swb_delay; - wb_fofb_processing_regs_min_num_pkts_val_swb_delay <= '0'; - end if; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_rip <= '0'; else - if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then - case rwaddr_reg(12 downto 9) is - when "0000" => - case rwaddr_reg(5 downto 0) is - when "000000" => - if (wb_we_i = '1') then - end if; - if (wb_we_i = '0') then - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb <= '1'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_delay <= '1'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_in_progress <= '1'; - end if; - ack_sreg(5) <= '1'; - ack_in_progress <= '1'; - when "000001" => - if (wb_we_i = '1') then - end if; - if (wb_we_i = '0') then - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb <= '1'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_delay <= '1'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_in_progress <= '1'; - end if; - ack_sreg(5) <= '1'; - ack_in_progress <= '1'; - when "000010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_0_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_0_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_0_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_0_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "000011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_0_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_0_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_0_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_0_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "000100" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_1_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_1_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_1_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_1_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "000101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_1_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_1_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_1_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_1_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "000110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_2_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_2_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_2_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_2_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "000111" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_2_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_2_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_2_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_2_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "001000" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_3_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_3_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_3_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_3_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "001001" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_3_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_3_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_3_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_3_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "001010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_4_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_4_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_4_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_4_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "001011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_4_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_4_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_4_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_4_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "001100" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_5_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_5_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_5_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_5_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "001101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_5_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_5_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_5_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_5_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "001110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_6_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_6_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_6_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_6_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "001111" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_6_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_6_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_6_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_6_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "010000" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_7_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_7_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_7_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_7_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "010001" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_7_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_7_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_7_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_7_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "010010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_8_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_8_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_8_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_8_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "010011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_8_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_8_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_8_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_8_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "010100" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_9_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_9_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_9_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_9_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "010101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_9_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_9_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_9_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_9_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "010110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_10_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_10_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_10_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_10_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "010111" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_10_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_10_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_10_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_10_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "011000" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_gain_11_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_acc_gain_11_val_swb <= '1'; - wb_fofb_processing_regs_acc_gain_11_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_acc_gain_11_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "011001" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_acc_ctl_11_clear_int <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_11_clear_int_delay <= wrdata_reg(0); - wb_fofb_processing_regs_acc_ctl_11_freeze_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= wb_fofb_processing_regs_acc_ctl_11_freeze_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "011010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_0_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_0_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_0_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_0_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "011011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_0_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_0_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_0_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_0_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "011100" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_1_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_1_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_1_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_1_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "011101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_1_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_1_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_1_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_1_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "011110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_2_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_2_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_2_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_2_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "011111" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_2_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_2_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_2_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_2_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100000" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_3_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_3_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_3_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_3_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100001" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_3_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_3_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_3_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_3_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_4_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_4_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_4_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_4_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_4_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_4_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_4_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_4_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100100" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_5_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_5_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_5_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_5_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_5_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_5_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_5_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_5_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_6_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_6_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_6_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_6_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "100111" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_6_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_6_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_6_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_6_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101000" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_7_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_7_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_7_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_7_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101001" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_7_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_7_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_7_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_7_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_8_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_8_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_8_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_8_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_8_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_8_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_8_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_8_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101100" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_9_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_9_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_9_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_9_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_9_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_9_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_9_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_9_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_10_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_10_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_10_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_10_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "101111" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_10_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_10_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_10_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_10_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "110000" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_max_11_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_max_11_val_swb <= '1'; - wb_fofb_processing_regs_sp_max_11_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_max_11_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "110001" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_sp_min_11_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_sp_min_11_val_swb <= '1'; - wb_fofb_processing_regs_sp_min_11_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_sp_min_11_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "110010" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_int <= wrdata_reg(0); - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_int <= wrdata_reg(1); - end if; - rddata_reg(0) <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_int; - rddata_reg(1) <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_int; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "110011" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_loop_intlk_ctl_clr_int <= wrdata_reg(0); - wb_fofb_processing_regs_loop_intlk_ctl_clr_int_delay <= wrdata_reg(0); - end if; - rddata_reg(0) <= '0'; - rddata_reg(1) <= 'X'; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when "110100" => - if (wb_we_i = '1') then - end if; - rddata_reg(0) <= wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync1; - rddata_reg(1) <= wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync1; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(0) <= '1'; - ack_in_progress <= '1'; - when "110101" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_orb_distort_limit_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_orb_distort_limit_val_swb <= '1'; - wb_fofb_processing_regs_orb_distort_limit_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_orb_distort_limit_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "110110" => - if (wb_we_i = '1') then - wb_fofb_processing_regs_min_num_pkts_val_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_regs_min_num_pkts_val_swb <= '1'; - wb_fofb_processing_regs_min_num_pkts_val_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_regs_min_num_pkts_val_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when others => - -- prevent the slave from hanging the bus on invalid address - ack_in_progress <= '1'; - ack_sreg(0) <= '1'; - end case; - when "0001" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "0010" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "0011" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "0100" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "0101" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "0110" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "0111" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "1000" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "1001" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "1010" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "1011" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "1100" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when "1101" => - if (rd_int = '1') then - ack_sreg(0) <= '1'; - else - ack_sreg(0) <= '1'; - end if; - ack_in_progress <= '1'; - when others => - -- prevent the slave from hanging the bus on invalid address - ack_in_progress <= '1'; - ack_sreg(0) <= '1'; - end case; - end if; + wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int; end if; end if; end process; + rd_req_int <= (wb_en and not wb_i.we) and not wb_rip; - - -- Data output multiplexer process - process (rddata_reg, rwaddr_reg, wb_fofb_processing_regs_coeffs_ram_bank_0_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_1_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_2_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_3_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_4_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_5_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_6_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_7_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_8_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_9_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_10_rddata_int, wb_fofb_processing_regs_coeffs_ram_bank_11_rddata_int, wb_fofb_processing_regs_setpoints_ram_bank_rddata_int, wb_adr_i ) - begin - case rwaddr_reg(12 downto 9) is - when "0001" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_0_rddata_int; - when "0010" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_1_rddata_int; - when "0011" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_2_rddata_int; - when "0100" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_3_rddata_int; - when "0101" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_4_rddata_int; - when "0110" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_5_rddata_int; - when "0111" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_6_rddata_int; - when "1000" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_7_rddata_int; - when "1001" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_8_rddata_int; - when "1010" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_9_rddata_int; - when "1011" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_10_rddata_int; - when "1100" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_coeffs_ram_bank_11_rddata_int; - when "1101" => - wb_dat_o(31 downto 0) <= wb_fofb_processing_regs_setpoints_ram_bank_rddata_int; - when others => - wb_dat_o <= rddata_reg; - end case; - end process; - - - -- Read & write lines decoder for RAMs - process (wb_adr_i, rd_int, wr_int ) - begin - if (wb_adr_i(12 downto 9) = "0001") then - wb_fofb_processing_regs_coeffs_ram_bank_0_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_0_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_0_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_0_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "0010") then - wb_fofb_processing_regs_coeffs_ram_bank_1_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_1_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_1_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_1_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "0011") then - wb_fofb_processing_regs_coeffs_ram_bank_2_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_2_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_2_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_2_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "0100") then - wb_fofb_processing_regs_coeffs_ram_bank_3_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_3_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_3_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_3_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "0101") then - wb_fofb_processing_regs_coeffs_ram_bank_4_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_4_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_4_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_4_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "0110") then - wb_fofb_processing_regs_coeffs_ram_bank_5_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_5_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_5_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_5_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "0111") then - wb_fofb_processing_regs_coeffs_ram_bank_6_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_6_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_6_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_6_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "1000") then - wb_fofb_processing_regs_coeffs_ram_bank_7_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_7_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_7_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_7_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "1001") then - wb_fofb_processing_regs_coeffs_ram_bank_8_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_8_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_8_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_8_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "1010") then - wb_fofb_processing_regs_coeffs_ram_bank_9_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_9_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_9_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_9_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "1011") then - wb_fofb_processing_regs_coeffs_ram_bank_10_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_10_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_10_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_10_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "1100") then - wb_fofb_processing_regs_coeffs_ram_bank_11_rd_int <= rd_int; - wb_fofb_processing_regs_coeffs_ram_bank_11_wr_int <= wr_int; - else - wb_fofb_processing_regs_coeffs_ram_bank_11_wr_int <= '0'; - wb_fofb_processing_regs_coeffs_ram_bank_11_rd_int <= '0'; - end if; - if (wb_adr_i(12 downto 9) = "1101") then - wb_fofb_processing_regs_setpoints_ram_bank_rd_int <= rd_int; - wb_fofb_processing_regs_setpoints_ram_bank_wr_int <= wr_int; - else - wb_fofb_processing_regs_setpoints_ram_bank_wr_int <= '0'; - wb_fofb_processing_regs_setpoints_ram_bank_rd_int <= '0'; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_wip <= '0'; + else + wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int; + end if; end if; end process; + wr_req_int <= (wb_en and wb_i.we) and not wb_wip; + ack_int <= rd_ack_int or wr_ack_int; + wb_o.ack <= ack_int; + wb_o.stall <= not ack_int and wb_en; + wb_o.rty <= '0'; + wb_o.err <= '0'; - -- fixed-point position constant value - -- asynchronous std_logic_vector register : fixed-point position constant value (type RO/WO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s0 <= '0'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s1 <= '0'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s2 <= '0'; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_int <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s0 <= wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s1 <= wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s0; - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s2 <= wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s1; - if ((wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s1 = '1') and (wb_fofb_processing_regs_coeffs_fixed_point_pos_val_lwb_s2 = '0')) then - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_int <= wb_fofb_processing_regs_coeffs_fixed_point_pos_val_i; + -- pipelining for wr-in+rd-out + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + rd_ack_int <= '0'; + wr_req_d0 <= '0'; + else + rd_ack_int <= rd_ack_d0; + wb_o.dat <= rd_dat_d0; + wr_req_d0 <= wr_req_int; + wr_adr_d0 <= adr_int; + wr_dat_d0 <= wb_i.dat; + wr_sel_d0 <= wb_i.sel; end if; end if; end process; + -- Register fixed_point_pos_coeff + + -- Register fixed_point_pos_accs_gains - -- value - -- asynchronous std_logic_vector register : value (type RO/WO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s0 <= '0'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s1 <= '0'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s2 <= '0'; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_int <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s0 <= wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s1 <= wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s0; - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s2 <= wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s1; - if ((wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s1 = '1') and (wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_lwb_s2 = '0')) then - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_int <= wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_i; + -- Register loop_intlk_ctl + loop_intlk_ctl_sta_clr_o <= loop_intlk_ctl_sta_clr_reg; + loop_intlk_ctl_src_en_orb_distort_o <= loop_intlk_ctl_src_en_orb_distort_reg; + loop_intlk_ctl_src_en_packet_loss_o <= loop_intlk_ctl_src_en_packet_loss_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + loop_intlk_ctl_sta_clr_reg <= '0'; + loop_intlk_ctl_src_en_orb_distort_reg <= '0'; + loop_intlk_ctl_src_en_packet_loss_reg <= '0'; + loop_intlk_ctl_wack <= '0'; + else + if loop_intlk_ctl_wreq = '1' then + loop_intlk_ctl_sta_clr_reg <= wr_dat_d0(0); + loop_intlk_ctl_src_en_orb_distort_reg <= wr_dat_d0(1); + loop_intlk_ctl_src_en_packet_loss_reg <= wr_dat_d0(2); + else + loop_intlk_ctl_sta_clr_reg <= '0'; + end if; + loop_intlk_ctl_wack <= loop_intlk_ctl_wreq; end if; end if; end process; + -- Register loop_intlk_sta - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_0_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_0_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_0_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_0_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_0_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_0_val_swb; - wb_fofb_processing_regs_acc_gain_0_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_0_val_swb_s0; - wb_fofb_processing_regs_acc_gain_0_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_0_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_0_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_0_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_0_val_o <= wb_fofb_processing_regs_acc_gain_0_val_int; + -- Register loop_intlk_orb_distort_limit + loop_intlk_orb_distort_limit_val_o <= loop_intlk_orb_distort_limit_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + loop_intlk_orb_distort_limit_val_reg <= "00000000000000000000000000000000"; + loop_intlk_orb_distort_limit_wack <= '0'; + else + if loop_intlk_orb_distort_limit_wreq = '1' then + loop_intlk_orb_distort_limit_val_reg <= wr_dat_d0; + end if; + loop_intlk_orb_distort_limit_wack <= loop_intlk_orb_distort_limit_wreq; end if; end if; end process; - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_0_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_0_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_0_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_0_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_0_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_0_clear_int; - wb_fofb_processing_regs_acc_ctl_0_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_0_clear_sync0; - wb_fofb_processing_regs_acc_ctl_0_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_0_clear_sync1; - wb_fofb_processing_regs_acc_ctl_0_clear_o <= wb_fofb_processing_regs_acc_ctl_0_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_0_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_0_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_0_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_0_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_0_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_0_freeze_int; - wb_fofb_processing_regs_acc_ctl_0_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_0_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_0_freeze_o <= wb_fofb_processing_regs_acc_ctl_0_freeze_sync1; + -- Register loop_intlk_min_num_pkts + loop_intlk_min_num_pkts_val_o <= loop_intlk_min_num_pkts_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + loop_intlk_min_num_pkts_val_reg <= "00000000000000000000000000000000"; + loop_intlk_min_num_pkts_wack <= '0'; + else + if loop_intlk_min_num_pkts_wreq = '1' then + loop_intlk_min_num_pkts_val_reg <= wr_dat_d0; + end if; + loop_intlk_min_num_pkts_wack <= loop_intlk_min_num_pkts_wreq; + end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_1_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_1_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_1_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_1_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_1_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_1_val_swb; - wb_fofb_processing_regs_acc_gain_1_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_1_val_swb_s0; - wb_fofb_processing_regs_acc_gain_1_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_1_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_1_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_1_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_1_val_o <= wb_fofb_processing_regs_acc_gain_1_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_1_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_1_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_1_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_1_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_1_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_1_clear_int; - wb_fofb_processing_regs_acc_ctl_1_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_1_clear_sync0; - wb_fofb_processing_regs_acc_ctl_1_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_1_clear_sync1; - wb_fofb_processing_regs_acc_ctl_1_clear_o <= wb_fofb_processing_regs_acc_ctl_1_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_1_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_1_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_1_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_1_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_1_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_1_freeze_int; - wb_fofb_processing_regs_acc_ctl_1_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_1_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_1_freeze_o <= wb_fofb_processing_regs_acc_ctl_1_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_2_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_2_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_2_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_2_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_2_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_2_val_swb; - wb_fofb_processing_regs_acc_gain_2_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_2_val_swb_s0; - wb_fofb_processing_regs_acc_gain_2_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_2_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_2_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_2_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_2_val_o <= wb_fofb_processing_regs_acc_gain_2_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_2_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_2_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_2_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_2_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_2_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_2_clear_int; - wb_fofb_processing_regs_acc_ctl_2_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_2_clear_sync0; - wb_fofb_processing_regs_acc_ctl_2_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_2_clear_sync1; - wb_fofb_processing_regs_acc_ctl_2_clear_o <= wb_fofb_processing_regs_acc_ctl_2_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_2_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_2_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_2_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_2_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_2_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_2_freeze_int; - wb_fofb_processing_regs_acc_ctl_2_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_2_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_2_freeze_o <= wb_fofb_processing_regs_acc_ctl_2_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_3_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_3_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_3_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_3_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_3_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_3_val_swb; - wb_fofb_processing_regs_acc_gain_3_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_3_val_swb_s0; - wb_fofb_processing_regs_acc_gain_3_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_3_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_3_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_3_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_3_val_o <= wb_fofb_processing_regs_acc_gain_3_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_3_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_3_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_3_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_3_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_3_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_3_clear_int; - wb_fofb_processing_regs_acc_ctl_3_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_3_clear_sync0; - wb_fofb_processing_regs_acc_ctl_3_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_3_clear_sync1; - wb_fofb_processing_regs_acc_ctl_3_clear_o <= wb_fofb_processing_regs_acc_ctl_3_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_3_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_3_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_3_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_3_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_3_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_3_freeze_int; - wb_fofb_processing_regs_acc_ctl_3_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_3_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_3_freeze_o <= wb_fofb_processing_regs_acc_ctl_3_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_4_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_4_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_4_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_4_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_4_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_4_val_swb; - wb_fofb_processing_regs_acc_gain_4_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_4_val_swb_s0; - wb_fofb_processing_regs_acc_gain_4_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_4_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_4_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_4_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_4_val_o <= wb_fofb_processing_regs_acc_gain_4_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_4_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_4_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_4_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_4_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_4_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_4_clear_int; - wb_fofb_processing_regs_acc_ctl_4_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_4_clear_sync0; - wb_fofb_processing_regs_acc_ctl_4_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_4_clear_sync1; - wb_fofb_processing_regs_acc_ctl_4_clear_o <= wb_fofb_processing_regs_acc_ctl_4_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_4_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_4_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_4_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_4_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_4_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_4_freeze_int; - wb_fofb_processing_regs_acc_ctl_4_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_4_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_4_freeze_o <= wb_fofb_processing_regs_acc_ctl_4_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_5_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_5_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_5_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_5_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_5_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_5_val_swb; - wb_fofb_processing_regs_acc_gain_5_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_5_val_swb_s0; - wb_fofb_processing_regs_acc_gain_5_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_5_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_5_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_5_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_5_val_o <= wb_fofb_processing_regs_acc_gain_5_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_5_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_5_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_5_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_5_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_5_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_5_clear_int; - wb_fofb_processing_regs_acc_ctl_5_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_5_clear_sync0; - wb_fofb_processing_regs_acc_ctl_5_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_5_clear_sync1; - wb_fofb_processing_regs_acc_ctl_5_clear_o <= wb_fofb_processing_regs_acc_ctl_5_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_5_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_5_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_5_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_5_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_5_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_5_freeze_int; - wb_fofb_processing_regs_acc_ctl_5_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_5_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_5_freeze_o <= wb_fofb_processing_regs_acc_ctl_5_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_6_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_6_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_6_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_6_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_6_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_6_val_swb; - wb_fofb_processing_regs_acc_gain_6_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_6_val_swb_s0; - wb_fofb_processing_regs_acc_gain_6_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_6_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_6_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_6_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_6_val_o <= wb_fofb_processing_regs_acc_gain_6_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_6_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_6_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_6_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_6_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_6_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_6_clear_int; - wb_fofb_processing_regs_acc_ctl_6_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_6_clear_sync0; - wb_fofb_processing_regs_acc_ctl_6_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_6_clear_sync1; - wb_fofb_processing_regs_acc_ctl_6_clear_o <= wb_fofb_processing_regs_acc_ctl_6_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_6_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_6_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_6_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_6_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_6_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_6_freeze_int; - wb_fofb_processing_regs_acc_ctl_6_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_6_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_6_freeze_o <= wb_fofb_processing_regs_acc_ctl_6_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_7_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_7_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_7_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_7_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_7_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_7_val_swb; - wb_fofb_processing_regs_acc_gain_7_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_7_val_swb_s0; - wb_fofb_processing_regs_acc_gain_7_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_7_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_7_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_7_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_7_val_o <= wb_fofb_processing_regs_acc_gain_7_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_7_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_7_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_7_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_7_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_7_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_7_clear_int; - wb_fofb_processing_regs_acc_ctl_7_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_7_clear_sync0; - wb_fofb_processing_regs_acc_ctl_7_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_7_clear_sync1; - wb_fofb_processing_regs_acc_ctl_7_clear_o <= wb_fofb_processing_regs_acc_ctl_7_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_7_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_7_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_7_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_7_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_7_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_7_freeze_int; - wb_fofb_processing_regs_acc_ctl_7_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_7_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_7_freeze_o <= wb_fofb_processing_regs_acc_ctl_7_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_8_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_8_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_8_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_8_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_8_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_8_val_swb; - wb_fofb_processing_regs_acc_gain_8_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_8_val_swb_s0; - wb_fofb_processing_regs_acc_gain_8_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_8_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_8_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_8_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_8_val_o <= wb_fofb_processing_regs_acc_gain_8_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_8_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_8_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_8_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_8_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_8_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_8_clear_int; - wb_fofb_processing_regs_acc_ctl_8_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_8_clear_sync0; - wb_fofb_processing_regs_acc_ctl_8_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_8_clear_sync1; - wb_fofb_processing_regs_acc_ctl_8_clear_o <= wb_fofb_processing_regs_acc_ctl_8_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_8_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_8_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_8_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_8_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_8_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_8_freeze_int; - wb_fofb_processing_regs_acc_ctl_8_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_8_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_8_freeze_o <= wb_fofb_processing_regs_acc_ctl_8_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_9_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_9_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_9_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_9_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_9_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_9_val_swb; - wb_fofb_processing_regs_acc_gain_9_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_9_val_swb_s0; - wb_fofb_processing_regs_acc_gain_9_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_9_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_9_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_9_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_9_val_o <= wb_fofb_processing_regs_acc_gain_9_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_9_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_9_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_9_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_9_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_9_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_9_clear_int; - wb_fofb_processing_regs_acc_ctl_9_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_9_clear_sync0; - wb_fofb_processing_regs_acc_ctl_9_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_9_clear_sync1; - wb_fofb_processing_regs_acc_ctl_9_clear_o <= wb_fofb_processing_regs_acc_ctl_9_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_9_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_9_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_9_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_9_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_9_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_9_freeze_int; - wb_fofb_processing_regs_acc_ctl_9_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_9_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_9_freeze_o <= wb_fofb_processing_regs_acc_ctl_9_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_10_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_10_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_10_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_10_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_10_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_10_val_swb; - wb_fofb_processing_regs_acc_gain_10_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_10_val_swb_s0; - wb_fofb_processing_regs_acc_gain_10_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_10_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_10_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_10_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_10_val_o <= wb_fofb_processing_regs_acc_gain_10_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_10_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_10_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_10_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_10_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_10_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_10_clear_int; - wb_fofb_processing_regs_acc_ctl_10_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_10_clear_sync0; - wb_fofb_processing_regs_acc_ctl_10_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_10_clear_sync1; - wb_fofb_processing_regs_acc_ctl_10_clear_o <= wb_fofb_processing_regs_acc_ctl_10_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_10_clear_sync1); - end if; - end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_10_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_10_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_10_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_10_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_10_freeze_int; - wb_fofb_processing_regs_acc_ctl_10_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_10_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_10_freeze_o <= wb_fofb_processing_regs_acc_ctl_10_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_gain_11_val_swb_s0 <= '0'; - wb_fofb_processing_regs_acc_gain_11_val_swb_s1 <= '0'; - wb_fofb_processing_regs_acc_gain_11_val_swb_s2 <= '0'; - wb_fofb_processing_regs_acc_gain_11_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_gain_11_val_swb_s0 <= wb_fofb_processing_regs_acc_gain_11_val_swb; - wb_fofb_processing_regs_acc_gain_11_val_swb_s1 <= wb_fofb_processing_regs_acc_gain_11_val_swb_s0; - wb_fofb_processing_regs_acc_gain_11_val_swb_s2 <= wb_fofb_processing_regs_acc_gain_11_val_swb_s1; - if ((wb_fofb_processing_regs_acc_gain_11_val_swb_s2 = '0') and (wb_fofb_processing_regs_acc_gain_11_val_swb_s1 = '1')) then - wb_fofb_processing_regs_acc_gain_11_val_o <= wb_fofb_processing_regs_acc_gain_11_val_int; - end if; - end if; - end process; - - - -- clear accumulator bit - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_11_clear_o <= '0'; - wb_fofb_processing_regs_acc_ctl_11_clear_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_11_clear_sync1 <= '0'; - wb_fofb_processing_regs_acc_ctl_11_clear_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_11_clear_sync0 <= wb_fofb_processing_regs_acc_ctl_11_clear_int; - wb_fofb_processing_regs_acc_ctl_11_clear_sync1 <= wb_fofb_processing_regs_acc_ctl_11_clear_sync0; - wb_fofb_processing_regs_acc_ctl_11_clear_sync2 <= wb_fofb_processing_regs_acc_ctl_11_clear_sync1; - wb_fofb_processing_regs_acc_ctl_11_clear_o <= wb_fofb_processing_regs_acc_ctl_11_clear_sync2 and (not wb_fofb_processing_regs_acc_ctl_11_clear_sync1); + -- Memory sps_ram_bank + process (adr_int, wr_adr_d0, sps_ram_bank_wr) begin + if sps_ram_bank_wr = '1' then + sps_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + sps_ram_bank_adr_int <= adr_int(10 downto 2); end if; end process; - - - -- freeze accumulator bit - -- synchronizer chain for field : freeze accumulator bit (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_acc_ctl_11_freeze_o <= '0'; - wb_fofb_processing_regs_acc_ctl_11_freeze_sync0 <= '0'; - wb_fofb_processing_regs_acc_ctl_11_freeze_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_acc_ctl_11_freeze_sync0 <= wb_fofb_processing_regs_acc_ctl_11_freeze_int; - wb_fofb_processing_regs_acc_ctl_11_freeze_sync1 <= wb_fofb_processing_regs_acc_ctl_11_freeze_sync0; - wb_fofb_processing_regs_acc_ctl_11_freeze_o <= wb_fofb_processing_regs_acc_ctl_11_freeze_sync1; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_0_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_0_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_0_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_0_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_0_val_swb_s0 <= wb_fofb_processing_regs_sp_max_0_val_swb; - wb_fofb_processing_regs_sp_max_0_val_swb_s1 <= wb_fofb_processing_regs_sp_max_0_val_swb_s0; - wb_fofb_processing_regs_sp_max_0_val_swb_s2 <= wb_fofb_processing_regs_sp_max_0_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_0_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_0_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_0_val_o <= wb_fofb_processing_regs_sp_max_0_val_int; - end if; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_0_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_0_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_0_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_0_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_0_val_swb_s0 <= wb_fofb_processing_regs_sp_min_0_val_swb; - wb_fofb_processing_regs_sp_min_0_val_swb_s1 <= wb_fofb_processing_regs_sp_min_0_val_swb_s0; - wb_fofb_processing_regs_sp_min_0_val_swb_s2 <= wb_fofb_processing_regs_sp_min_0_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_0_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_0_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_0_val_o <= wb_fofb_processing_regs_sp_min_0_val_int; - end if; - end if; - end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_1_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_1_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_1_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_1_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_1_val_swb_s0 <= wb_fofb_processing_regs_sp_max_1_val_swb; - wb_fofb_processing_regs_sp_max_1_val_swb_s1 <= wb_fofb_processing_regs_sp_max_1_val_swb_s0; - wb_fofb_processing_regs_sp_max_1_val_swb_s2 <= wb_fofb_processing_regs_sp_max_1_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_1_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_1_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_1_val_o <= wb_fofb_processing_regs_sp_max_1_val_int; - end if; + sps_ram_bank_wreq <= sps_ram_bank_data_int_wr; + sps_ram_bank_rr <= sps_ram_bank_data_rreq and not sps_ram_bank_wreq; + sps_ram_bank_wr <= sps_ram_bank_wreq; + sps_ram_bank_data_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 512, + g_addr_width => 9, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => sps_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => sps_ram_bank_data_int_dato, + rd_a_i => sps_ram_bank_data_rreq, + wr_a_i => sps_ram_bank_data_int_wr, + addr_b_i => sps_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => sps_ram_bank_data_ext_dat, + data_b_o => sps_ram_bank_data_dat_o, + rd_b_i => sps_ram_bank_data_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + sps_ram_bank_data_rack <= '0'; + else + sps_ram_bank_data_rack <= sps_ram_bank_data_rreq; + end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_1_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_1_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_1_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_1_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_1_val_swb_s0 <= wb_fofb_processing_regs_sp_min_1_val_swb; - wb_fofb_processing_regs_sp_min_1_val_swb_s1 <= wb_fofb_processing_regs_sp_min_1_val_swb_s0; - wb_fofb_processing_regs_sp_min_1_val_swb_s2 <= wb_fofb_processing_regs_sp_min_1_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_1_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_1_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_1_val_o <= wb_fofb_processing_regs_sp_min_1_val_int; - end if; + -- Memory ch_0_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_0_coeff_ram_bank_wr) begin + if ch_0_coeff_ram_bank_wr = '1' then + ch_0_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_0_coeff_ram_bank_adr_int <= adr_int(10 downto 2); end if; end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_2_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_2_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_2_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_2_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_2_val_swb_s0 <= wb_fofb_processing_regs_sp_max_2_val_swb; - wb_fofb_processing_regs_sp_max_2_val_swb_s1 <= wb_fofb_processing_regs_sp_max_2_val_swb_s0; - wb_fofb_processing_regs_sp_max_2_val_swb_s2 <= wb_fofb_processing_regs_sp_max_2_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_2_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_2_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_2_val_o <= wb_fofb_processing_regs_sp_max_2_val_int; + ch_0_coeff_ram_bank_wreq <= ch_0_coeff_ram_bank_data_int_wr; + ch_0_coeff_ram_bank_rr <= ch_0_coeff_ram_bank_data_rreq and not ch_0_coeff_ram_bank_wreq; + ch_0_coeff_ram_bank_wr <= ch_0_coeff_ram_bank_wreq; + ch_0_coeff_ram_bank_data_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 512, + g_addr_width => 9, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_0_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_0_coeff_ram_bank_data_int_dato, + rd_a_i => ch_0_coeff_ram_bank_data_rreq, + wr_a_i => ch_0_coeff_ram_bank_data_int_wr, + addr_b_i => ch_0_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_0_coeff_ram_bank_data_ext_dat, + data_b_o => ch_0_coeff_ram_bank_data_dat_o, + rd_b_i => ch_0_coeff_ram_bank_data_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_coeff_ram_bank_data_rack <= '0'; + else + ch_0_coeff_ram_bank_data_rack <= ch_0_coeff_ram_bank_data_rreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_2_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_2_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_2_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_2_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_2_val_swb_s0 <= wb_fofb_processing_regs_sp_min_2_val_swb; - wb_fofb_processing_regs_sp_min_2_val_swb_s1 <= wb_fofb_processing_regs_sp_min_2_val_swb_s0; - wb_fofb_processing_regs_sp_min_2_val_swb_s2 <= wb_fofb_processing_regs_sp_min_2_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_2_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_2_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_2_val_o <= wb_fofb_processing_regs_sp_min_2_val_int; + -- Register ch_0_acc_ctl + ch_0_acc_ctl_clear_o <= ch_0_acc_ctl_clear_reg; + ch_0_acc_ctl_freeze_o <= ch_0_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_acc_ctl_clear_reg <= '0'; + ch_0_acc_ctl_freeze_reg <= '0'; + ch_0_acc_ctl_wack <= '0'; + else + if ch_0_acc_ctl_wreq = '1' then + ch_0_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_0_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_0_acc_ctl_clear_reg <= '0'; + end if; + ch_0_acc_ctl_wack <= ch_0_acc_ctl_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_3_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_3_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_3_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_3_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_3_val_swb_s0 <= wb_fofb_processing_regs_sp_max_3_val_swb; - wb_fofb_processing_regs_sp_max_3_val_swb_s1 <= wb_fofb_processing_regs_sp_max_3_val_swb_s0; - wb_fofb_processing_regs_sp_max_3_val_swb_s2 <= wb_fofb_processing_regs_sp_max_3_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_3_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_3_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_3_val_o <= wb_fofb_processing_regs_sp_max_3_val_int; + -- Register ch_0_acc_gain + ch_0_acc_gain_val_o <= ch_0_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_0_acc_gain_wack <= '0'; + else + if ch_0_acc_gain_wreq = '1' then + ch_0_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_0_acc_gain_wack <= ch_0_acc_gain_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_3_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_3_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_3_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_3_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_3_val_swb_s0 <= wb_fofb_processing_regs_sp_min_3_val_swb; - wb_fofb_processing_regs_sp_min_3_val_swb_s1 <= wb_fofb_processing_regs_sp_min_3_val_swb_s0; - wb_fofb_processing_regs_sp_min_3_val_swb_s2 <= wb_fofb_processing_regs_sp_min_3_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_3_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_3_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_3_val_o <= wb_fofb_processing_regs_sp_min_3_val_int; + -- Register ch_0_sp_limits_max + ch_0_sp_limits_max_val_o <= ch_0_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_0_sp_limits_max_wack <= '0'; + else + if ch_0_sp_limits_max_wreq = '1' then + ch_0_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_0_sp_limits_max_wack <= ch_0_sp_limits_max_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_4_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_4_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_4_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_4_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_4_val_swb_s0 <= wb_fofb_processing_regs_sp_max_4_val_swb; - wb_fofb_processing_regs_sp_max_4_val_swb_s1 <= wb_fofb_processing_regs_sp_max_4_val_swb_s0; - wb_fofb_processing_regs_sp_max_4_val_swb_s2 <= wb_fofb_processing_regs_sp_max_4_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_4_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_4_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_4_val_o <= wb_fofb_processing_regs_sp_max_4_val_int; + -- Register ch_0_sp_limits_min + ch_0_sp_limits_min_val_o <= ch_0_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_0_sp_limits_min_wack <= '0'; + else + if ch_0_sp_limits_min_wreq = '1' then + ch_0_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_0_sp_limits_min_wack <= ch_0_sp_limits_min_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_4_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_4_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_4_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_4_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_4_val_swb_s0 <= wb_fofb_processing_regs_sp_min_4_val_swb; - wb_fofb_processing_regs_sp_min_4_val_swb_s1 <= wb_fofb_processing_regs_sp_min_4_val_swb_s0; - wb_fofb_processing_regs_sp_min_4_val_swb_s2 <= wb_fofb_processing_regs_sp_min_4_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_4_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_4_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_4_val_o <= wb_fofb_processing_regs_sp_min_4_val_int; - end if; + -- Memory ch_1_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_1_coeff_ram_bank_wr) begin + if ch_1_coeff_ram_bank_wr = '1' then + ch_1_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_1_coeff_ram_bank_adr_int <= adr_int(10 downto 2); end if; end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_5_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_5_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_5_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_5_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_5_val_swb_s0 <= wb_fofb_processing_regs_sp_max_5_val_swb; - wb_fofb_processing_regs_sp_max_5_val_swb_s1 <= wb_fofb_processing_regs_sp_max_5_val_swb_s0; - wb_fofb_processing_regs_sp_max_5_val_swb_s2 <= wb_fofb_processing_regs_sp_max_5_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_5_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_5_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_5_val_o <= wb_fofb_processing_regs_sp_max_5_val_int; + ch_1_coeff_ram_bank_wreq <= ch_1_coeff_ram_bank_data_int_wr; + ch_1_coeff_ram_bank_rr <= ch_1_coeff_ram_bank_data_rreq and not ch_1_coeff_ram_bank_wreq; + ch_1_coeff_ram_bank_wr <= ch_1_coeff_ram_bank_wreq; + ch_1_coeff_ram_bank_data_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 512, + g_addr_width => 9, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_1_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_1_coeff_ram_bank_data_int_dato, + rd_a_i => ch_1_coeff_ram_bank_data_rreq, + wr_a_i => ch_1_coeff_ram_bank_data_int_wr, + addr_b_i => ch_1_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_1_coeff_ram_bank_data_ext_dat, + data_b_o => ch_1_coeff_ram_bank_data_dat_o, + rd_b_i => ch_1_coeff_ram_bank_data_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_coeff_ram_bank_data_rack <= '0'; + else + ch_1_coeff_ram_bank_data_rack <= ch_1_coeff_ram_bank_data_rreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_5_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_5_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_5_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_5_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_5_val_swb_s0 <= wb_fofb_processing_regs_sp_min_5_val_swb; - wb_fofb_processing_regs_sp_min_5_val_swb_s1 <= wb_fofb_processing_regs_sp_min_5_val_swb_s0; - wb_fofb_processing_regs_sp_min_5_val_swb_s2 <= wb_fofb_processing_regs_sp_min_5_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_5_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_5_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_5_val_o <= wb_fofb_processing_regs_sp_min_5_val_int; + -- Register ch_1_acc_ctl + ch_1_acc_ctl_clear_o <= ch_1_acc_ctl_clear_reg; + ch_1_acc_ctl_freeze_o <= ch_1_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_acc_ctl_clear_reg <= '0'; + ch_1_acc_ctl_freeze_reg <= '0'; + ch_1_acc_ctl_wack <= '0'; + else + if ch_1_acc_ctl_wreq = '1' then + ch_1_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_1_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_1_acc_ctl_clear_reg <= '0'; + end if; + ch_1_acc_ctl_wack <= ch_1_acc_ctl_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_6_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_6_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_6_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_6_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_6_val_swb_s0 <= wb_fofb_processing_regs_sp_max_6_val_swb; - wb_fofb_processing_regs_sp_max_6_val_swb_s1 <= wb_fofb_processing_regs_sp_max_6_val_swb_s0; - wb_fofb_processing_regs_sp_max_6_val_swb_s2 <= wb_fofb_processing_regs_sp_max_6_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_6_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_6_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_6_val_o <= wb_fofb_processing_regs_sp_max_6_val_int; + -- Register ch_1_acc_gain + ch_1_acc_gain_val_o <= ch_1_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_1_acc_gain_wack <= '0'; + else + if ch_1_acc_gain_wreq = '1' then + ch_1_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_1_acc_gain_wack <= ch_1_acc_gain_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_6_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_6_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_6_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_6_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_6_val_swb_s0 <= wb_fofb_processing_regs_sp_min_6_val_swb; - wb_fofb_processing_regs_sp_min_6_val_swb_s1 <= wb_fofb_processing_regs_sp_min_6_val_swb_s0; - wb_fofb_processing_regs_sp_min_6_val_swb_s2 <= wb_fofb_processing_regs_sp_min_6_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_6_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_6_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_6_val_o <= wb_fofb_processing_regs_sp_min_6_val_int; + -- Register ch_1_sp_limits_max + ch_1_sp_limits_max_val_o <= ch_1_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_1_sp_limits_max_wack <= '0'; + else + if ch_1_sp_limits_max_wreq = '1' then + ch_1_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_1_sp_limits_max_wack <= ch_1_sp_limits_max_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_7_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_7_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_7_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_7_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_7_val_swb_s0 <= wb_fofb_processing_regs_sp_max_7_val_swb; - wb_fofb_processing_regs_sp_max_7_val_swb_s1 <= wb_fofb_processing_regs_sp_max_7_val_swb_s0; - wb_fofb_processing_regs_sp_max_7_val_swb_s2 <= wb_fofb_processing_regs_sp_max_7_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_7_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_7_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_7_val_o <= wb_fofb_processing_regs_sp_max_7_val_int; + -- Register ch_1_sp_limits_min + ch_1_sp_limits_min_val_o <= ch_1_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_1_sp_limits_min_wack <= '0'; + else + if ch_1_sp_limits_min_wreq = '1' then + ch_1_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_1_sp_limits_min_wack <= ch_1_sp_limits_min_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_7_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_7_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_7_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_7_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_7_val_swb_s0 <= wb_fofb_processing_regs_sp_min_7_val_swb; - wb_fofb_processing_regs_sp_min_7_val_swb_s1 <= wb_fofb_processing_regs_sp_min_7_val_swb_s0; - wb_fofb_processing_regs_sp_min_7_val_swb_s2 <= wb_fofb_processing_regs_sp_min_7_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_7_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_7_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_7_val_o <= wb_fofb_processing_regs_sp_min_7_val_int; + -- Memory ch_2_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_2_coeff_ram_bank_wr) begin + if ch_2_coeff_ram_bank_wr = '1' then + ch_2_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_2_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_2_coeff_ram_bank_wreq <= ch_2_coeff_ram_bank_data_int_wr; + ch_2_coeff_ram_bank_rr <= ch_2_coeff_ram_bank_data_rreq and not ch_2_coeff_ram_bank_wreq; + ch_2_coeff_ram_bank_wr <= ch_2_coeff_ram_bank_wreq; + ch_2_coeff_ram_bank_data_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 512, + g_addr_width => 9, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_2_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_2_coeff_ram_bank_data_int_dato, + rd_a_i => ch_2_coeff_ram_bank_data_rreq, + wr_a_i => ch_2_coeff_ram_bank_data_int_wr, + addr_b_i => ch_2_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_2_coeff_ram_bank_data_ext_dat, + data_b_o => ch_2_coeff_ram_bank_data_dat_o, + rd_b_i => ch_2_coeff_ram_bank_data_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_coeff_ram_bank_data_rack <= '0'; + else + ch_2_coeff_ram_bank_data_rack <= ch_2_coeff_ram_bank_data_rreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_8_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_8_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_8_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_8_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_8_val_swb_s0 <= wb_fofb_processing_regs_sp_max_8_val_swb; - wb_fofb_processing_regs_sp_max_8_val_swb_s1 <= wb_fofb_processing_regs_sp_max_8_val_swb_s0; - wb_fofb_processing_regs_sp_max_8_val_swb_s2 <= wb_fofb_processing_regs_sp_max_8_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_8_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_8_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_8_val_o <= wb_fofb_processing_regs_sp_max_8_val_int; + -- Register ch_2_acc_ctl + ch_2_acc_ctl_clear_o <= ch_2_acc_ctl_clear_reg; + ch_2_acc_ctl_freeze_o <= ch_2_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_acc_ctl_clear_reg <= '0'; + ch_2_acc_ctl_freeze_reg <= '0'; + ch_2_acc_ctl_wack <= '0'; + else + if ch_2_acc_ctl_wreq = '1' then + ch_2_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_2_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_2_acc_ctl_clear_reg <= '0'; + end if; + ch_2_acc_ctl_wack <= ch_2_acc_ctl_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_8_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_8_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_8_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_8_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_8_val_swb_s0 <= wb_fofb_processing_regs_sp_min_8_val_swb; - wb_fofb_processing_regs_sp_min_8_val_swb_s1 <= wb_fofb_processing_regs_sp_min_8_val_swb_s0; - wb_fofb_processing_regs_sp_min_8_val_swb_s2 <= wb_fofb_processing_regs_sp_min_8_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_8_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_8_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_8_val_o <= wb_fofb_processing_regs_sp_min_8_val_int; + -- Register ch_2_acc_gain + ch_2_acc_gain_val_o <= ch_2_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_2_acc_gain_wack <= '0'; + else + if ch_2_acc_gain_wreq = '1' then + ch_2_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_2_acc_gain_wack <= ch_2_acc_gain_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_9_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_9_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_9_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_9_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_9_val_swb_s0 <= wb_fofb_processing_regs_sp_max_9_val_swb; - wb_fofb_processing_regs_sp_max_9_val_swb_s1 <= wb_fofb_processing_regs_sp_max_9_val_swb_s0; - wb_fofb_processing_regs_sp_max_9_val_swb_s2 <= wb_fofb_processing_regs_sp_max_9_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_9_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_9_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_9_val_o <= wb_fofb_processing_regs_sp_max_9_val_int; + -- Register ch_2_sp_limits_max + ch_2_sp_limits_max_val_o <= ch_2_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_2_sp_limits_max_wack <= '0'; + else + if ch_2_sp_limits_max_wreq = '1' then + ch_2_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_2_sp_limits_max_wack <= ch_2_sp_limits_max_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_9_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_9_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_9_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_9_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_9_val_swb_s0 <= wb_fofb_processing_regs_sp_min_9_val_swb; - wb_fofb_processing_regs_sp_min_9_val_swb_s1 <= wb_fofb_processing_regs_sp_min_9_val_swb_s0; - wb_fofb_processing_regs_sp_min_9_val_swb_s2 <= wb_fofb_processing_regs_sp_min_9_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_9_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_9_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_9_val_o <= wb_fofb_processing_regs_sp_min_9_val_int; + -- Register ch_2_sp_limits_min + ch_2_sp_limits_min_val_o <= ch_2_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_2_sp_limits_min_wack <= '0'; + else + if ch_2_sp_limits_min_wreq = '1' then + ch_2_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_2_sp_limits_min_wack <= ch_2_sp_limits_min_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_10_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_10_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_10_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_10_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_10_val_swb_s0 <= wb_fofb_processing_regs_sp_max_10_val_swb; - wb_fofb_processing_regs_sp_max_10_val_swb_s1 <= wb_fofb_processing_regs_sp_max_10_val_swb_s0; - wb_fofb_processing_regs_sp_max_10_val_swb_s2 <= wb_fofb_processing_regs_sp_max_10_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_10_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_10_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_10_val_o <= wb_fofb_processing_regs_sp_max_10_val_int; + -- Memory ch_3_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_3_coeff_ram_bank_wr) begin + if ch_3_coeff_ram_bank_wr = '1' then + ch_3_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_3_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_3_coeff_ram_bank_wreq <= ch_3_coeff_ram_bank_data_int_wr; + ch_3_coeff_ram_bank_rr <= ch_3_coeff_ram_bank_data_rreq and not ch_3_coeff_ram_bank_wreq; + ch_3_coeff_ram_bank_wr <= ch_3_coeff_ram_bank_wreq; + ch_3_coeff_ram_bank_data_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 512, + g_addr_width => 9, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_3_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_3_coeff_ram_bank_data_int_dato, + rd_a_i => ch_3_coeff_ram_bank_data_rreq, + wr_a_i => ch_3_coeff_ram_bank_data_int_wr, + addr_b_i => ch_3_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_3_coeff_ram_bank_data_ext_dat, + data_b_o => ch_3_coeff_ram_bank_data_dat_o, + rd_b_i => ch_3_coeff_ram_bank_data_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_coeff_ram_bank_data_rack <= '0'; + else + ch_3_coeff_ram_bank_data_rack <= ch_3_coeff_ram_bank_data_rreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_10_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_10_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_10_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_10_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_10_val_swb_s0 <= wb_fofb_processing_regs_sp_min_10_val_swb; - wb_fofb_processing_regs_sp_min_10_val_swb_s1 <= wb_fofb_processing_regs_sp_min_10_val_swb_s0; - wb_fofb_processing_regs_sp_min_10_val_swb_s2 <= wb_fofb_processing_regs_sp_min_10_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_10_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_10_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_10_val_o <= wb_fofb_processing_regs_sp_min_10_val_int; + -- Register ch_3_acc_ctl + ch_3_acc_ctl_clear_o <= ch_3_acc_ctl_clear_reg; + ch_3_acc_ctl_freeze_o <= ch_3_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_acc_ctl_clear_reg <= '0'; + ch_3_acc_ctl_freeze_reg <= '0'; + ch_3_acc_ctl_wack <= '0'; + else + if ch_3_acc_ctl_wreq = '1' then + ch_3_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_3_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_3_acc_ctl_clear_reg <= '0'; + end if; + ch_3_acc_ctl_wack <= ch_3_acc_ctl_wreq; end if; end if; end process; - - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_max_11_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_max_11_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_max_11_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_max_11_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_max_11_val_swb_s0 <= wb_fofb_processing_regs_sp_max_11_val_swb; - wb_fofb_processing_regs_sp_max_11_val_swb_s1 <= wb_fofb_processing_regs_sp_max_11_val_swb_s0; - wb_fofb_processing_regs_sp_max_11_val_swb_s2 <= wb_fofb_processing_regs_sp_max_11_val_swb_s1; - if ((wb_fofb_processing_regs_sp_max_11_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_max_11_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_max_11_val_o <= wb_fofb_processing_regs_sp_max_11_val_int; + + -- Register ch_3_acc_gain + ch_3_acc_gain_val_o <= ch_3_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_3_acc_gain_wack <= '0'; + else + if ch_3_acc_gain_wreq = '1' then + ch_3_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_3_acc_gain_wack <= ch_3_acc_gain_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_sp_min_11_val_swb_s0 <= '0'; - wb_fofb_processing_regs_sp_min_11_val_swb_s1 <= '0'; - wb_fofb_processing_regs_sp_min_11_val_swb_s2 <= '0'; - wb_fofb_processing_regs_sp_min_11_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_sp_min_11_val_swb_s0 <= wb_fofb_processing_regs_sp_min_11_val_swb; - wb_fofb_processing_regs_sp_min_11_val_swb_s1 <= wb_fofb_processing_regs_sp_min_11_val_swb_s0; - wb_fofb_processing_regs_sp_min_11_val_swb_s2 <= wb_fofb_processing_regs_sp_min_11_val_swb_s1; - if ((wb_fofb_processing_regs_sp_min_11_val_swb_s2 = '0') and (wb_fofb_processing_regs_sp_min_11_val_swb_s1 = '1')) then - wb_fofb_processing_regs_sp_min_11_val_o <= wb_fofb_processing_regs_sp_min_11_val_int; + -- Register ch_3_sp_limits_max + ch_3_sp_limits_max_val_o <= ch_3_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_3_sp_limits_max_wack <= '0'; + else + if ch_3_sp_limits_max_wreq = '1' then + ch_3_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_3_sp_limits_max_wack <= ch_3_sp_limits_max_wreq; end if; end if; end process; - - -- orbit distortion source enable - -- synchronizer chain for field : orbit distortion source enable (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_o <= '0'; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync0 <= '0'; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync0 <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_int; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync1 <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync0; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_o <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_sync1; + -- Register ch_3_sp_limits_min + ch_3_sp_limits_min_val_o <= ch_3_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_3_sp_limits_min_wack <= '0'; + else + if ch_3_sp_limits_min_wreq = '1' then + ch_3_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_3_sp_limits_min_wack <= ch_3_sp_limits_min_wreq; + end if; end if; end process; - - -- packet loss source enable - -- synchronizer chain for field : packet loss source enable (type RW/RO, clk_sys_i <-> wb_fofb_processing_regs_clk_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_o <= '0'; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync0 <= '0'; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync0 <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_int; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync1 <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync0; - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_o <= wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_sync1; + -- Memory ch_4_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_4_coeff_ram_bank_wr) begin + if ch_4_coeff_ram_bank_wr = '1' then + ch_4_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_4_coeff_ram_bank_adr_int <= adr_int(10 downto 2); end if; end process; - - - -- clears loop interlock status - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_loop_intlk_ctl_clr_o <= '0'; - wb_fofb_processing_regs_loop_intlk_ctl_clr_sync0 <= '0'; - wb_fofb_processing_regs_loop_intlk_ctl_clr_sync1 <= '0'; - wb_fofb_processing_regs_loop_intlk_ctl_clr_sync2 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_loop_intlk_ctl_clr_sync0 <= wb_fofb_processing_regs_loop_intlk_ctl_clr_int; - wb_fofb_processing_regs_loop_intlk_ctl_clr_sync1 <= wb_fofb_processing_regs_loop_intlk_ctl_clr_sync0; - wb_fofb_processing_regs_loop_intlk_ctl_clr_sync2 <= wb_fofb_processing_regs_loop_intlk_ctl_clr_sync1; - wb_fofb_processing_regs_loop_intlk_ctl_clr_o <= wb_fofb_processing_regs_loop_intlk_ctl_clr_sync2 and (not wb_fofb_processing_regs_loop_intlk_ctl_clr_sync1); + ch_4_coeff_ram_bank_wreq <= ch_4_coeff_ram_bank_data_int_wr; + ch_4_coeff_ram_bank_rr <= ch_4_coeff_ram_bank_data_rreq and not ch_4_coeff_ram_bank_wreq; + ch_4_coeff_ram_bank_wr <= ch_4_coeff_ram_bank_wreq; + ch_4_coeff_ram_bank_data_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 512, + g_addr_width => 9, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_4_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_4_coeff_ram_bank_data_int_dato, + rd_a_i => ch_4_coeff_ram_bank_data_rreq, + wr_a_i => ch_4_coeff_ram_bank_data_int_wr, + addr_b_i => ch_4_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_4_coeff_ram_bank_data_ext_dat, + data_b_o => ch_4_coeff_ram_bank_data_dat_o, + rd_b_i => ch_4_coeff_ram_bank_data_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_coeff_ram_bank_data_rack <= '0'; + else + ch_4_coeff_ram_bank_data_rack <= ch_4_coeff_ram_bank_data_rreq; + end if; end if; end process; - - -- orbit distortion loop interlock flag - -- synchronizer chain for field : orbit distortion loop interlock flag (type RO/WO, wb_fofb_processing_regs_clk_i -> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync0 <= '0'; - wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync0 <= wb_fofb_processing_regs_loop_intlk_sta_orb_distort_i; - wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync1 <= wb_fofb_processing_regs_loop_intlk_sta_orb_distort_sync0; + -- Register ch_4_acc_ctl + ch_4_acc_ctl_clear_o <= ch_4_acc_ctl_clear_reg; + ch_4_acc_ctl_freeze_o <= ch_4_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_acc_ctl_clear_reg <= '0'; + ch_4_acc_ctl_freeze_reg <= '0'; + ch_4_acc_ctl_wack <= '0'; + else + if ch_4_acc_ctl_wreq = '1' then + ch_4_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_4_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_4_acc_ctl_clear_reg <= '0'; + end if; + ch_4_acc_ctl_wack <= ch_4_acc_ctl_wreq; + end if; end if; end process; - - -- packet loss loop interlock flag - -- synchronizer chain for field : packet loss loop interlock flag (type RO/WO, wb_fofb_processing_regs_clk_i -> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync0 <= '0'; - wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync1 <= '0'; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync0 <= wb_fofb_processing_regs_loop_intlk_sta_packet_loss_i; - wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync1 <= wb_fofb_processing_regs_loop_intlk_sta_packet_loss_sync0; + -- Register ch_4_acc_gain + ch_4_acc_gain_val_o <= ch_4_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_4_acc_gain_wack <= '0'; + else + if ch_4_acc_gain_wreq = '1' then + ch_4_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_4_acc_gain_wack <= ch_4_acc_gain_wreq; + end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_orb_distort_limit_val_swb_s0 <= '0'; - wb_fofb_processing_regs_orb_distort_limit_val_swb_s1 <= '0'; - wb_fofb_processing_regs_orb_distort_limit_val_swb_s2 <= '0'; - wb_fofb_processing_regs_orb_distort_limit_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_orb_distort_limit_val_swb_s0 <= wb_fofb_processing_regs_orb_distort_limit_val_swb; - wb_fofb_processing_regs_orb_distort_limit_val_swb_s1 <= wb_fofb_processing_regs_orb_distort_limit_val_swb_s0; - wb_fofb_processing_regs_orb_distort_limit_val_swb_s2 <= wb_fofb_processing_regs_orb_distort_limit_val_swb_s1; - if ((wb_fofb_processing_regs_orb_distort_limit_val_swb_s2 = '0') and (wb_fofb_processing_regs_orb_distort_limit_val_swb_s1 = '1')) then - wb_fofb_processing_regs_orb_distort_limit_val_o <= wb_fofb_processing_regs_orb_distort_limit_val_int; + -- Register ch_4_sp_limits_max + ch_4_sp_limits_max_val_o <= ch_4_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_4_sp_limits_max_wack <= '0'; + else + if ch_4_sp_limits_max_wreq = '1' then + ch_4_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_4_sp_limits_max_wack <= ch_4_sp_limits_max_wreq; end if; end if; end process; - - -- value - -- asynchronous std_logic_vector register : value (type RW/RO, wb_fofb_processing_regs_clk_i <-> clk_sys_i) - process (wb_fofb_processing_regs_clk_i, rst_n_i) - begin - if (rst_n_i = '0') then - wb_fofb_processing_regs_min_num_pkts_val_swb_s0 <= '0'; - wb_fofb_processing_regs_min_num_pkts_val_swb_s1 <= '0'; - wb_fofb_processing_regs_min_num_pkts_val_swb_s2 <= '0'; - wb_fofb_processing_regs_min_num_pkts_val_o <= "00000000000000000000000000000000"; - elsif rising_edge(wb_fofb_processing_regs_clk_i) then - wb_fofb_processing_regs_min_num_pkts_val_swb_s0 <= wb_fofb_processing_regs_min_num_pkts_val_swb; - wb_fofb_processing_regs_min_num_pkts_val_swb_s1 <= wb_fofb_processing_regs_min_num_pkts_val_swb_s0; - wb_fofb_processing_regs_min_num_pkts_val_swb_s2 <= wb_fofb_processing_regs_min_num_pkts_val_swb_s1; - if ((wb_fofb_processing_regs_min_num_pkts_val_swb_s2 = '0') and (wb_fofb_processing_regs_min_num_pkts_val_swb_s1 = '1')) then - wb_fofb_processing_regs_min_num_pkts_val_o <= wb_fofb_processing_regs_min_num_pkts_val_int; + -- Register ch_4_sp_limits_min + ch_4_sp_limits_min_val_o <= ch_4_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_4_sp_limits_min_wack <= '0'; + else + if ch_4_sp_limits_min_wreq = '1' then + ch_4_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_4_sp_limits_min_wack <= ch_4_sp_limits_min_wreq; end if; end if; end process; - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_0_raminst: wbgen2_dpssram - generic map ( - g_data_width => 32, - g_size => 512, - g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false - ) - port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_0_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_0_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_0_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_0_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_0_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_0_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_0_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_0_wr_int, - bwsel_a_i => allones(3 downto 0) - ); - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_1_raminst: wbgen2_dpssram - generic map ( - g_data_width => 32, - g_size => 512, - g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false - ) - port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_1_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_1_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_1_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_1_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_1_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_1_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_1_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_1_wr_int, - bwsel_a_i => allones(3 downto 0) - ); - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_2_raminst: wbgen2_dpssram - generic map ( - g_data_width => 32, - g_size => 512, - g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false - ) - port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_2_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_2_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_2_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_2_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_2_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_2_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_2_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_2_wr_int, - bwsel_a_i => allones(3 downto 0) - ); - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_3_raminst: wbgen2_dpssram - generic map ( - g_data_width => 32, - g_size => 512, - g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false - ) - port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_3_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_3_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_3_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_3_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_3_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_3_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_3_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_3_wr_int, - bwsel_a_i => allones(3 downto 0) - ); - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_4_raminst: wbgen2_dpssram - generic map ( - g_data_width => 32, - g_size => 512, - g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false - ) - port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_4_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_4_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_4_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_4_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_4_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_4_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_4_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_4_wr_int, - bwsel_a_i => allones(3 downto 0) - ); - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_5_raminst: wbgen2_dpssram - generic map ( - g_data_width => 32, - g_size => 512, - g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false - ) - port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_5_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_5_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_5_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_5_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_5_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_5_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_5_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_5_wr_int, - bwsel_a_i => allones(3 downto 0) - ); - - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_6_raminst: wbgen2_dpssram + -- Memory ch_5_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_5_coeff_ram_bank_wr) begin + if ch_5_coeff_ram_bank_wr = '1' then + ch_5_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_5_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_5_coeff_ram_bank_wreq <= ch_5_coeff_ram_bank_data_int_wr; + ch_5_coeff_ram_bank_rr <= ch_5_coeff_ram_bank_data_rreq and not ch_5_coeff_ram_bank_wreq; + ch_5_coeff_ram_bank_wr <= ch_5_coeff_ram_bank_wreq; + ch_5_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_6_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_6_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_6_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_6_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_6_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_6_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_6_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_6_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_5_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_5_coeff_ram_bank_data_int_dato, + rd_a_i => ch_5_coeff_ram_bank_data_rreq, + wr_a_i => ch_5_coeff_ram_bank_data_int_wr, + addr_b_i => ch_5_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_5_coeff_ram_bank_data_ext_dat, + data_b_o => ch_5_coeff_ram_bank_data_dat_o, + rd_b_i => ch_5_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_7_raminst: wbgen2_dpssram + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_coeff_ram_bank_data_rack <= '0'; + else + ch_5_coeff_ram_bank_data_rack <= ch_5_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_5_acc_ctl + ch_5_acc_ctl_clear_o <= ch_5_acc_ctl_clear_reg; + ch_5_acc_ctl_freeze_o <= ch_5_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_acc_ctl_clear_reg <= '0'; + ch_5_acc_ctl_freeze_reg <= '0'; + ch_5_acc_ctl_wack <= '0'; + else + if ch_5_acc_ctl_wreq = '1' then + ch_5_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_5_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_5_acc_ctl_clear_reg <= '0'; + end if; + ch_5_acc_ctl_wack <= ch_5_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_5_acc_gain + ch_5_acc_gain_val_o <= ch_5_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_5_acc_gain_wack <= '0'; + else + if ch_5_acc_gain_wreq = '1' then + ch_5_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_5_acc_gain_wack <= ch_5_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_5_sp_limits_max + ch_5_sp_limits_max_val_o <= ch_5_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_5_sp_limits_max_wack <= '0'; + else + if ch_5_sp_limits_max_wreq = '1' then + ch_5_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_5_sp_limits_max_wack <= ch_5_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_5_sp_limits_min + ch_5_sp_limits_min_val_o <= ch_5_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_5_sp_limits_min_wack <= '0'; + else + if ch_5_sp_limits_min_wreq = '1' then + ch_5_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_5_sp_limits_min_wack <= ch_5_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Memory ch_6_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_6_coeff_ram_bank_wr) begin + if ch_6_coeff_ram_bank_wr = '1' then + ch_6_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_6_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_6_coeff_ram_bank_wreq <= ch_6_coeff_ram_bank_data_int_wr; + ch_6_coeff_ram_bank_rr <= ch_6_coeff_ram_bank_data_rreq and not ch_6_coeff_ram_bank_wreq; + ch_6_coeff_ram_bank_wr <= ch_6_coeff_ram_bank_wreq; + ch_6_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_7_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_7_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_7_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_7_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_7_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_7_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_7_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_7_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_6_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_6_coeff_ram_bank_data_int_dato, + rd_a_i => ch_6_coeff_ram_bank_data_rreq, + wr_a_i => ch_6_coeff_ram_bank_data_int_wr, + addr_b_i => ch_6_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_6_coeff_ram_bank_data_ext_dat, + data_b_o => ch_6_coeff_ram_bank_data_dat_o, + rd_b_i => ch_6_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_8_raminst: wbgen2_dpssram + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_coeff_ram_bank_data_rack <= '0'; + else + ch_6_coeff_ram_bank_data_rack <= ch_6_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_6_acc_ctl + ch_6_acc_ctl_clear_o <= ch_6_acc_ctl_clear_reg; + ch_6_acc_ctl_freeze_o <= ch_6_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_acc_ctl_clear_reg <= '0'; + ch_6_acc_ctl_freeze_reg <= '0'; + ch_6_acc_ctl_wack <= '0'; + else + if ch_6_acc_ctl_wreq = '1' then + ch_6_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_6_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_6_acc_ctl_clear_reg <= '0'; + end if; + ch_6_acc_ctl_wack <= ch_6_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_6_acc_gain + ch_6_acc_gain_val_o <= ch_6_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_6_acc_gain_wack <= '0'; + else + if ch_6_acc_gain_wreq = '1' then + ch_6_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_6_acc_gain_wack <= ch_6_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_6_sp_limits_max + ch_6_sp_limits_max_val_o <= ch_6_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_6_sp_limits_max_wack <= '0'; + else + if ch_6_sp_limits_max_wreq = '1' then + ch_6_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_6_sp_limits_max_wack <= ch_6_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_6_sp_limits_min + ch_6_sp_limits_min_val_o <= ch_6_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_6_sp_limits_min_wack <= '0'; + else + if ch_6_sp_limits_min_wreq = '1' then + ch_6_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_6_sp_limits_min_wack <= ch_6_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Memory ch_7_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_7_coeff_ram_bank_wr) begin + if ch_7_coeff_ram_bank_wr = '1' then + ch_7_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_7_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_7_coeff_ram_bank_wreq <= ch_7_coeff_ram_bank_data_int_wr; + ch_7_coeff_ram_bank_rr <= ch_7_coeff_ram_bank_data_rreq and not ch_7_coeff_ram_bank_wreq; + ch_7_coeff_ram_bank_wr <= ch_7_coeff_ram_bank_wreq; + ch_7_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_8_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_8_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_8_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_8_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_8_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_8_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_8_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_8_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_7_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_7_coeff_ram_bank_data_int_dato, + rd_a_i => ch_7_coeff_ram_bank_data_rreq, + wr_a_i => ch_7_coeff_ram_bank_data_int_wr, + addr_b_i => ch_7_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_7_coeff_ram_bank_data_ext_dat, + data_b_o => ch_7_coeff_ram_bank_data_dat_o, + rd_b_i => ch_7_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_9_raminst: wbgen2_dpssram + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_coeff_ram_bank_data_rack <= '0'; + else + ch_7_coeff_ram_bank_data_rack <= ch_7_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_7_acc_ctl + ch_7_acc_ctl_clear_o <= ch_7_acc_ctl_clear_reg; + ch_7_acc_ctl_freeze_o <= ch_7_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_acc_ctl_clear_reg <= '0'; + ch_7_acc_ctl_freeze_reg <= '0'; + ch_7_acc_ctl_wack <= '0'; + else + if ch_7_acc_ctl_wreq = '1' then + ch_7_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_7_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_7_acc_ctl_clear_reg <= '0'; + end if; + ch_7_acc_ctl_wack <= ch_7_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_7_acc_gain + ch_7_acc_gain_val_o <= ch_7_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_7_acc_gain_wack <= '0'; + else + if ch_7_acc_gain_wreq = '1' then + ch_7_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_7_acc_gain_wack <= ch_7_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_7_sp_limits_max + ch_7_sp_limits_max_val_o <= ch_7_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_7_sp_limits_max_wack <= '0'; + else + if ch_7_sp_limits_max_wreq = '1' then + ch_7_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_7_sp_limits_max_wack <= ch_7_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_7_sp_limits_min + ch_7_sp_limits_min_val_o <= ch_7_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_7_sp_limits_min_wack <= '0'; + else + if ch_7_sp_limits_min_wreq = '1' then + ch_7_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_7_sp_limits_min_wack <= ch_7_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Memory ch_8_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_8_coeff_ram_bank_wr) begin + if ch_8_coeff_ram_bank_wr = '1' then + ch_8_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_8_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_8_coeff_ram_bank_wreq <= ch_8_coeff_ram_bank_data_int_wr; + ch_8_coeff_ram_bank_rr <= ch_8_coeff_ram_bank_data_rreq and not ch_8_coeff_ram_bank_wreq; + ch_8_coeff_ram_bank_wr <= ch_8_coeff_ram_bank_wreq; + ch_8_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_9_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_9_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_9_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_9_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_9_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_9_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_9_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_9_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_8_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_8_coeff_ram_bank_data_int_dato, + rd_a_i => ch_8_coeff_ram_bank_data_rreq, + wr_a_i => ch_8_coeff_ram_bank_data_int_wr, + addr_b_i => ch_8_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_8_coeff_ram_bank_data_ext_dat, + data_b_o => ch_8_coeff_ram_bank_data_dat_o, + rd_b_i => ch_8_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_10_raminst: wbgen2_dpssram + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_coeff_ram_bank_data_rack <= '0'; + else + ch_8_coeff_ram_bank_data_rack <= ch_8_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_8_acc_ctl + ch_8_acc_ctl_clear_o <= ch_8_acc_ctl_clear_reg; + ch_8_acc_ctl_freeze_o <= ch_8_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_acc_ctl_clear_reg <= '0'; + ch_8_acc_ctl_freeze_reg <= '0'; + ch_8_acc_ctl_wack <= '0'; + else + if ch_8_acc_ctl_wreq = '1' then + ch_8_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_8_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_8_acc_ctl_clear_reg <= '0'; + end if; + ch_8_acc_ctl_wack <= ch_8_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_8_acc_gain + ch_8_acc_gain_val_o <= ch_8_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_8_acc_gain_wack <= '0'; + else + if ch_8_acc_gain_wreq = '1' then + ch_8_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_8_acc_gain_wack <= ch_8_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_8_sp_limits_max + ch_8_sp_limits_max_val_o <= ch_8_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_8_sp_limits_max_wack <= '0'; + else + if ch_8_sp_limits_max_wreq = '1' then + ch_8_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_8_sp_limits_max_wack <= ch_8_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_8_sp_limits_min + ch_8_sp_limits_min_val_o <= ch_8_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_8_sp_limits_min_wack <= '0'; + else + if ch_8_sp_limits_min_wreq = '1' then + ch_8_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_8_sp_limits_min_wack <= ch_8_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Memory ch_9_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_9_coeff_ram_bank_wr) begin + if ch_9_coeff_ram_bank_wr = '1' then + ch_9_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_9_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_9_coeff_ram_bank_wreq <= ch_9_coeff_ram_bank_data_int_wr; + ch_9_coeff_ram_bank_rr <= ch_9_coeff_ram_bank_data_rreq and not ch_9_coeff_ram_bank_wreq; + ch_9_coeff_ram_bank_wr <= ch_9_coeff_ram_bank_wreq; + ch_9_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_10_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_10_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_10_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_10_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_10_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_10_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_10_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_10_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_9_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_9_coeff_ram_bank_data_int_dato, + rd_a_i => ch_9_coeff_ram_bank_data_rreq, + wr_a_i => ch_9_coeff_ram_bank_data_int_wr, + addr_b_i => ch_9_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_9_coeff_ram_bank_data_ext_dat, + data_b_o => ch_9_coeff_ram_bank_data_dat_o, + rd_b_i => ch_9_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - -- extra code for reg/fifo/mem: fofb processing coefficients ram bank - -- RAM block instantiation for memory: fofb processing coefficients ram bank - wb_fofb_processing_regs_coeffs_ram_bank_11_raminst: wbgen2_dpssram + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_coeff_ram_bank_data_rack <= '0'; + else + ch_9_coeff_ram_bank_data_rack <= ch_9_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_9_acc_ctl + ch_9_acc_ctl_clear_o <= ch_9_acc_ctl_clear_reg; + ch_9_acc_ctl_freeze_o <= ch_9_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_acc_ctl_clear_reg <= '0'; + ch_9_acc_ctl_freeze_reg <= '0'; + ch_9_acc_ctl_wack <= '0'; + else + if ch_9_acc_ctl_wreq = '1' then + ch_9_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_9_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_9_acc_ctl_clear_reg <= '0'; + end if; + ch_9_acc_ctl_wack <= ch_9_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_9_acc_gain + ch_9_acc_gain_val_o <= ch_9_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_9_acc_gain_wack <= '0'; + else + if ch_9_acc_gain_wreq = '1' then + ch_9_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_9_acc_gain_wack <= ch_9_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_9_sp_limits_max + ch_9_sp_limits_max_val_o <= ch_9_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_9_sp_limits_max_wack <= '0'; + else + if ch_9_sp_limits_max_wreq = '1' then + ch_9_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_9_sp_limits_max_wack <= ch_9_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_9_sp_limits_min + ch_9_sp_limits_min_val_o <= ch_9_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_9_sp_limits_min_wack <= '0'; + else + if ch_9_sp_limits_min_wreq = '1' then + ch_9_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_9_sp_limits_min_wack <= ch_9_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Memory ch_10_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_10_coeff_ram_bank_wr) begin + if ch_10_coeff_ram_bank_wr = '1' then + ch_10_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_10_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_10_coeff_ram_bank_wreq <= ch_10_coeff_ram_bank_data_int_wr; + ch_10_coeff_ram_bank_rr <= ch_10_coeff_ram_bank_data_rreq and not ch_10_coeff_ram_bank_wreq; + ch_10_coeff_ram_bank_wr <= ch_10_coeff_ram_bank_wreq; + ch_10_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_11_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_coeffs_ram_bank_11_data_o, - rd_b_i => wb_fofb_processing_regs_coeffs_ram_bank_11_rd_i, - data_b_i => wb_fofb_processing_regs_coeffs_ram_bank_11_data_i, - wr_b_i => wb_fofb_processing_regs_coeffs_ram_bank_11_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_coeffs_ram_bank_11_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_coeffs_ram_bank_11_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_coeffs_ram_bank_11_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_10_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_10_coeff_ram_bank_data_int_dato, + rd_a_i => ch_10_coeff_ram_bank_data_rreq, + wr_a_i => ch_10_coeff_ram_bank_data_int_wr, + addr_b_i => ch_10_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_10_coeff_ram_bank_data_ext_dat, + data_b_o => ch_10_coeff_ram_bank_data_dat_o, + rd_b_i => ch_10_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - -- extra code for reg/fifo/mem: fofb processing setpoints ram bank - -- RAM block instantiation for memory: fofb processing setpoints ram bank - wb_fofb_processing_regs_setpoints_ram_bank_raminst: wbgen2_dpssram + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_coeff_ram_bank_data_rack <= '0'; + else + ch_10_coeff_ram_bank_data_rack <= ch_10_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_10_acc_ctl + ch_10_acc_ctl_clear_o <= ch_10_acc_ctl_clear_reg; + ch_10_acc_ctl_freeze_o <= ch_10_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_acc_ctl_clear_reg <= '0'; + ch_10_acc_ctl_freeze_reg <= '0'; + ch_10_acc_ctl_wack <= '0'; + else + if ch_10_acc_ctl_wreq = '1' then + ch_10_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_10_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_10_acc_ctl_clear_reg <= '0'; + end if; + ch_10_acc_ctl_wack <= ch_10_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_10_acc_gain + ch_10_acc_gain_val_o <= ch_10_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_10_acc_gain_wack <= '0'; + else + if ch_10_acc_gain_wreq = '1' then + ch_10_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_10_acc_gain_wack <= ch_10_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_10_sp_limits_max + ch_10_sp_limits_max_val_o <= ch_10_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_10_sp_limits_max_wack <= '0'; + else + if ch_10_sp_limits_max_wreq = '1' then + ch_10_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_10_sp_limits_max_wack <= ch_10_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_10_sp_limits_min + ch_10_sp_limits_min_val_o <= ch_10_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_10_sp_limits_min_wack <= '0'; + else + if ch_10_sp_limits_min_wreq = '1' then + ch_10_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_10_sp_limits_min_wack <= ch_10_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Memory ch_11_coeff_ram_bank + process (adr_int, wr_adr_d0, ch_11_coeff_ram_bank_wr) begin + if ch_11_coeff_ram_bank_wr = '1' then + ch_11_coeff_ram_bank_adr_int <= wr_adr_d0(10 downto 2); + else + ch_11_coeff_ram_bank_adr_int <= adr_int(10 downto 2); + end if; + end process; + ch_11_coeff_ram_bank_wreq <= ch_11_coeff_ram_bank_data_int_wr; + ch_11_coeff_ram_bank_rr <= ch_11_coeff_ram_bank_data_rreq and not ch_11_coeff_ram_bank_wreq; + ch_11_coeff_ram_bank_wr <= ch_11_coeff_ram_bank_wreq; + ch_11_coeff_ram_bank_data_raminst: cheby_dpssram generic map ( g_data_width => 32, g_size => 512, g_addr_width => 9, - g_dual_clock => true, - g_use_bwsel => false + g_dual_clock => '0', + g_use_bwsel => '1' ) port map ( - clk_a_i => clk_sys_i, - clk_b_i => wb_fofb_processing_regs_clk_i, - addr_b_i => wb_fofb_processing_regs_setpoints_ram_bank_addr_i, - addr_a_i => rwaddr_reg(8 downto 0), - data_b_o => wb_fofb_processing_regs_setpoints_ram_bank_data_o, - rd_b_i => wb_fofb_processing_regs_setpoints_ram_bank_rd_i, - data_b_i => wb_fofb_processing_regs_setpoints_ram_bank_data_i, - wr_b_i => wb_fofb_processing_regs_setpoints_ram_bank_wr_i, - bwsel_b_i => allones(3 downto 0), - data_a_o => wb_fofb_processing_regs_setpoints_ram_bank_rddata_int(31 downto 0), - rd_a_i => wb_fofb_processing_regs_setpoints_ram_bank_rd_int, - data_a_i => wrdata_reg(31 downto 0), - wr_a_i => wb_fofb_processing_regs_setpoints_ram_bank_wr_int, - bwsel_a_i => allones(3 downto 0) + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_11_coeff_ram_bank_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_11_coeff_ram_bank_data_int_dato, + rd_a_i => ch_11_coeff_ram_bank_data_rreq, + wr_a_i => ch_11_coeff_ram_bank_data_int_wr, + addr_b_i => ch_11_coeff_ram_bank_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_11_coeff_ram_bank_data_ext_dat, + data_b_o => ch_11_coeff_ram_bank_data_dat_o, + rd_b_i => ch_11_coeff_ram_bank_data_rd_i, + wr_b_i => '0' ); - rwaddr_reg <= wb_adr_i; - wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); - -- ACK signal generation. Just pass the LSB of ACK counter. - wb_ack_o <= ack_sreg(0); + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_coeff_ram_bank_data_rack <= '0'; + else + ch_11_coeff_ram_bank_data_rack <= ch_11_coeff_ram_bank_data_rreq; + end if; + end if; + end process; + + -- Register ch_11_acc_ctl + ch_11_acc_ctl_clear_o <= ch_11_acc_ctl_clear_reg; + ch_11_acc_ctl_freeze_o <= ch_11_acc_ctl_freeze_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_acc_ctl_clear_reg <= '0'; + ch_11_acc_ctl_freeze_reg <= '0'; + ch_11_acc_ctl_wack <= '0'; + else + if ch_11_acc_ctl_wreq = '1' then + ch_11_acc_ctl_clear_reg <= wr_dat_d0(0); + ch_11_acc_ctl_freeze_reg <= wr_dat_d0(1); + else + ch_11_acc_ctl_clear_reg <= '0'; + end if; + ch_11_acc_ctl_wack <= ch_11_acc_ctl_wreq; + end if; + end if; + end process; + + -- Register ch_11_acc_gain + ch_11_acc_gain_val_o <= ch_11_acc_gain_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_acc_gain_val_reg <= "00000000000000000000000000000000"; + ch_11_acc_gain_wack <= '0'; + else + if ch_11_acc_gain_wreq = '1' then + ch_11_acc_gain_val_reg <= wr_dat_d0; + end if; + ch_11_acc_gain_wack <= ch_11_acc_gain_wreq; + end if; + end if; + end process; + + -- Register ch_11_sp_limits_max + ch_11_sp_limits_max_val_o <= ch_11_sp_limits_max_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_sp_limits_max_val_reg <= "00000000000000000000000000000000"; + ch_11_sp_limits_max_wack <= '0'; + else + if ch_11_sp_limits_max_wreq = '1' then + ch_11_sp_limits_max_val_reg <= wr_dat_d0; + end if; + ch_11_sp_limits_max_wack <= ch_11_sp_limits_max_wreq; + end if; + end if; + end process; + + -- Register ch_11_sp_limits_min + ch_11_sp_limits_min_val_o <= ch_11_sp_limits_min_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_sp_limits_min_val_reg <= "00000000000000000000000000000000"; + ch_11_sp_limits_min_wack <= '0'; + else + if ch_11_sp_limits_min_wreq = '1' then + ch_11_sp_limits_min_val_reg <= wr_dat_d0; + end if; + ch_11_sp_limits_min_wack <= ch_11_sp_limits_min_wreq; + end if; + end if; + end process; + + -- Process for write requests. + process (wr_adr_d0, wr_req_d0, loop_intlk_ctl_wack, loop_intlk_orb_distort_limit_wack, loop_intlk_min_num_pkts_wack, ch_0_acc_ctl_wack, ch_0_acc_gain_wack, ch_0_sp_limits_max_wack, ch_0_sp_limits_min_wack, ch_1_acc_ctl_wack, ch_1_acc_gain_wack, ch_1_sp_limits_max_wack, ch_1_sp_limits_min_wack, ch_2_acc_ctl_wack, ch_2_acc_gain_wack, ch_2_sp_limits_max_wack, ch_2_sp_limits_min_wack, ch_3_acc_ctl_wack, ch_3_acc_gain_wack, ch_3_sp_limits_max_wack, ch_3_sp_limits_min_wack, ch_4_acc_ctl_wack, ch_4_acc_gain_wack, ch_4_sp_limits_max_wack, ch_4_sp_limits_min_wack, ch_5_acc_ctl_wack, ch_5_acc_gain_wack, ch_5_sp_limits_max_wack, ch_5_sp_limits_min_wack, ch_6_acc_ctl_wack, ch_6_acc_gain_wack, ch_6_sp_limits_max_wack, ch_6_sp_limits_min_wack, ch_7_acc_ctl_wack, ch_7_acc_gain_wack, ch_7_sp_limits_max_wack, ch_7_sp_limits_min_wack, ch_8_acc_ctl_wack, ch_8_acc_gain_wack, ch_8_sp_limits_max_wack, ch_8_sp_limits_min_wack, ch_9_acc_ctl_wack, ch_9_acc_gain_wack, ch_9_sp_limits_max_wack, ch_9_sp_limits_min_wack, ch_10_acc_ctl_wack, ch_10_acc_gain_wack, ch_10_sp_limits_max_wack, ch_10_sp_limits_min_wack, ch_11_acc_ctl_wack, ch_11_acc_gain_wack, ch_11_sp_limits_max_wack, ch_11_sp_limits_min_wack) begin + loop_intlk_ctl_wreq <= '0'; + loop_intlk_orb_distort_limit_wreq <= '0'; + loop_intlk_min_num_pkts_wreq <= '0'; + sps_ram_bank_data_int_wr <= '0'; + ch_0_coeff_ram_bank_data_int_wr <= '0'; + ch_0_acc_ctl_wreq <= '0'; + ch_0_acc_gain_wreq <= '0'; + ch_0_sp_limits_max_wreq <= '0'; + ch_0_sp_limits_min_wreq <= '0'; + ch_1_coeff_ram_bank_data_int_wr <= '0'; + ch_1_acc_ctl_wreq <= '0'; + ch_1_acc_gain_wreq <= '0'; + ch_1_sp_limits_max_wreq <= '0'; + ch_1_sp_limits_min_wreq <= '0'; + ch_2_coeff_ram_bank_data_int_wr <= '0'; + ch_2_acc_ctl_wreq <= '0'; + ch_2_acc_gain_wreq <= '0'; + ch_2_sp_limits_max_wreq <= '0'; + ch_2_sp_limits_min_wreq <= '0'; + ch_3_coeff_ram_bank_data_int_wr <= '0'; + ch_3_acc_ctl_wreq <= '0'; + ch_3_acc_gain_wreq <= '0'; + ch_3_sp_limits_max_wreq <= '0'; + ch_3_sp_limits_min_wreq <= '0'; + ch_4_coeff_ram_bank_data_int_wr <= '0'; + ch_4_acc_ctl_wreq <= '0'; + ch_4_acc_gain_wreq <= '0'; + ch_4_sp_limits_max_wreq <= '0'; + ch_4_sp_limits_min_wreq <= '0'; + ch_5_coeff_ram_bank_data_int_wr <= '0'; + ch_5_acc_ctl_wreq <= '0'; + ch_5_acc_gain_wreq <= '0'; + ch_5_sp_limits_max_wreq <= '0'; + ch_5_sp_limits_min_wreq <= '0'; + ch_6_coeff_ram_bank_data_int_wr <= '0'; + ch_6_acc_ctl_wreq <= '0'; + ch_6_acc_gain_wreq <= '0'; + ch_6_sp_limits_max_wreq <= '0'; + ch_6_sp_limits_min_wreq <= '0'; + ch_7_coeff_ram_bank_data_int_wr <= '0'; + ch_7_acc_ctl_wreq <= '0'; + ch_7_acc_gain_wreq <= '0'; + ch_7_sp_limits_max_wreq <= '0'; + ch_7_sp_limits_min_wreq <= '0'; + ch_8_coeff_ram_bank_data_int_wr <= '0'; + ch_8_acc_ctl_wreq <= '0'; + ch_8_acc_gain_wreq <= '0'; + ch_8_sp_limits_max_wreq <= '0'; + ch_8_sp_limits_min_wreq <= '0'; + ch_9_coeff_ram_bank_data_int_wr <= '0'; + ch_9_acc_ctl_wreq <= '0'; + ch_9_acc_gain_wreq <= '0'; + ch_9_sp_limits_max_wreq <= '0'; + ch_9_sp_limits_min_wreq <= '0'; + ch_10_coeff_ram_bank_data_int_wr <= '0'; + ch_10_acc_ctl_wreq <= '0'; + ch_10_acc_gain_wreq <= '0'; + ch_10_sp_limits_max_wreq <= '0'; + ch_10_sp_limits_min_wreq <= '0'; + ch_11_coeff_ram_bank_data_int_wr <= '0'; + ch_11_acc_ctl_wreq <= '0'; + ch_11_acc_gain_wreq <= '0'; + ch_11_sp_limits_max_wreq <= '0'; + ch_11_sp_limits_min_wreq <= '0'; + case wr_adr_d0(15 downto 11) is + when "00000" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg fixed_point_pos_coeff + wr_ack_int <= wr_req_d0; + when "000000001" => + -- Reg fixed_point_pos_accs_gains + wr_ack_int <= wr_req_d0; + when "000010000" => + -- Reg loop_intlk_ctl + loop_intlk_ctl_wreq <= wr_req_d0; + wr_ack_int <= loop_intlk_ctl_wack; + when "000010001" => + -- Reg loop_intlk_sta + wr_ack_int <= wr_req_d0; + when "000010010" => + -- Reg loop_intlk_orb_distort_limit + loop_intlk_orb_distort_limit_wreq <= wr_req_d0; + wr_ack_int <= loop_intlk_orb_distort_limit_wack; + when "000010011" => + -- Reg loop_intlk_min_num_pkts + loop_intlk_min_num_pkts_wreq <= wr_req_d0; + wr_ack_int <= loop_intlk_min_num_pkts_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "00001" => + -- Memory sps_ram_bank + sps_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00010" => + -- Memory ch_0_coeff_ram_bank + ch_0_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00011" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_0_acc_ctl + ch_0_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_0_acc_ctl_wack; + when "000000001" => + -- Reg ch_0_acc_gain + ch_0_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_0_acc_gain_wack; + when "000010000" => + -- Reg ch_0_sp_limits_max + ch_0_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_0_sp_limits_max_wack; + when "000010001" => + -- Reg ch_0_sp_limits_min + ch_0_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_0_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "00100" => + -- Memory ch_1_coeff_ram_bank + ch_1_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00101" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_1_acc_ctl + ch_1_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_1_acc_ctl_wack; + when "000000001" => + -- Reg ch_1_acc_gain + ch_1_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_1_acc_gain_wack; + when "000010000" => + -- Reg ch_1_sp_limits_max + ch_1_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_1_sp_limits_max_wack; + when "000010001" => + -- Reg ch_1_sp_limits_min + ch_1_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_1_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "00110" => + -- Memory ch_2_coeff_ram_bank + ch_2_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00111" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_2_acc_ctl + ch_2_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_2_acc_ctl_wack; + when "000000001" => + -- Reg ch_2_acc_gain + ch_2_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_2_acc_gain_wack; + when "000010000" => + -- Reg ch_2_sp_limits_max + ch_2_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_2_sp_limits_max_wack; + when "000010001" => + -- Reg ch_2_sp_limits_min + ch_2_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_2_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "01000" => + -- Memory ch_3_coeff_ram_bank + ch_3_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01001" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_3_acc_ctl + ch_3_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_3_acc_ctl_wack; + when "000000001" => + -- Reg ch_3_acc_gain + ch_3_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_3_acc_gain_wack; + when "000010000" => + -- Reg ch_3_sp_limits_max + ch_3_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_3_sp_limits_max_wack; + when "000010001" => + -- Reg ch_3_sp_limits_min + ch_3_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_3_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "01010" => + -- Memory ch_4_coeff_ram_bank + ch_4_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01011" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_4_acc_ctl + ch_4_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_4_acc_ctl_wack; + when "000000001" => + -- Reg ch_4_acc_gain + ch_4_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_4_acc_gain_wack; + when "000010000" => + -- Reg ch_4_sp_limits_max + ch_4_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_4_sp_limits_max_wack; + when "000010001" => + -- Reg ch_4_sp_limits_min + ch_4_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_4_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "01100" => + -- Memory ch_5_coeff_ram_bank + ch_5_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01101" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_5_acc_ctl + ch_5_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_5_acc_ctl_wack; + when "000000001" => + -- Reg ch_5_acc_gain + ch_5_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_5_acc_gain_wack; + when "000010000" => + -- Reg ch_5_sp_limits_max + ch_5_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_5_sp_limits_max_wack; + when "000010001" => + -- Reg ch_5_sp_limits_min + ch_5_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_5_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "01110" => + -- Memory ch_6_coeff_ram_bank + ch_6_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01111" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_6_acc_ctl + ch_6_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_6_acc_ctl_wack; + when "000000001" => + -- Reg ch_6_acc_gain + ch_6_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_6_acc_gain_wack; + when "000010000" => + -- Reg ch_6_sp_limits_max + ch_6_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_6_sp_limits_max_wack; + when "000010001" => + -- Reg ch_6_sp_limits_min + ch_6_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_6_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "10000" => + -- Memory ch_7_coeff_ram_bank + ch_7_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "10001" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_7_acc_ctl + ch_7_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_7_acc_ctl_wack; + when "000000001" => + -- Reg ch_7_acc_gain + ch_7_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_7_acc_gain_wack; + when "000010000" => + -- Reg ch_7_sp_limits_max + ch_7_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_7_sp_limits_max_wack; + when "000010001" => + -- Reg ch_7_sp_limits_min + ch_7_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_7_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "10010" => + -- Memory ch_8_coeff_ram_bank + ch_8_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "10011" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_8_acc_ctl + ch_8_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_8_acc_ctl_wack; + when "000000001" => + -- Reg ch_8_acc_gain + ch_8_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_8_acc_gain_wack; + when "000010000" => + -- Reg ch_8_sp_limits_max + ch_8_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_8_sp_limits_max_wack; + when "000010001" => + -- Reg ch_8_sp_limits_min + ch_8_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_8_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "10100" => + -- Memory ch_9_coeff_ram_bank + ch_9_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "10101" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_9_acc_ctl + ch_9_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_9_acc_ctl_wack; + when "000000001" => + -- Reg ch_9_acc_gain + ch_9_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_9_acc_gain_wack; + when "000010000" => + -- Reg ch_9_sp_limits_max + ch_9_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_9_sp_limits_max_wack; + when "000010001" => + -- Reg ch_9_sp_limits_min + ch_9_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_9_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "10110" => + -- Memory ch_10_coeff_ram_bank + ch_10_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "10111" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_10_acc_ctl + ch_10_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_10_acc_ctl_wack; + when "000000001" => + -- Reg ch_10_acc_gain + ch_10_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_10_acc_gain_wack; + when "000010000" => + -- Reg ch_10_sp_limits_max + ch_10_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_10_sp_limits_max_wack; + when "000010001" => + -- Reg ch_10_sp_limits_min + ch_10_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_10_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when "11000" => + -- Memory ch_11_coeff_ram_bank + ch_11_coeff_ram_bank_data_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "11001" => + case wr_adr_d0(10 downto 2) is + when "000000000" => + -- Reg ch_11_acc_ctl + ch_11_acc_ctl_wreq <= wr_req_d0; + wr_ack_int <= ch_11_acc_ctl_wack; + when "000000001" => + -- Reg ch_11_acc_gain + ch_11_acc_gain_wreq <= wr_req_d0; + wr_ack_int <= ch_11_acc_gain_wack; + when "000010000" => + -- Reg ch_11_sp_limits_max + ch_11_sp_limits_max_wreq <= wr_req_d0; + wr_ack_int <= ch_11_sp_limits_max_wack; + when "000010001" => + -- Reg ch_11_sp_limits_min + ch_11_sp_limits_min_wreq <= wr_req_d0; + wr_ack_int <= ch_11_sp_limits_min_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when others => + wr_ack_int <= wr_req_d0; + end case; + end process; + + -- Process for read requests. + process (adr_int, rd_req_int, fixed_point_pos_coeff_val_i, fixed_point_pos_accs_gains_val_i, loop_intlk_ctl_src_en_orb_distort_reg, loop_intlk_ctl_src_en_packet_loss_reg, loop_intlk_sta_orb_distort_i, loop_intlk_sta_packet_loss_i, loop_intlk_orb_distort_limit_val_reg, loop_intlk_min_num_pkts_val_reg, sps_ram_bank_data_int_dato, sps_ram_bank_data_rack, ch_0_coeff_ram_bank_data_int_dato, ch_0_coeff_ram_bank_data_rack, ch_0_acc_ctl_freeze_reg, ch_0_acc_gain_val_reg, ch_0_sp_limits_max_val_reg, ch_0_sp_limits_min_val_reg, ch_1_coeff_ram_bank_data_int_dato, ch_1_coeff_ram_bank_data_rack, ch_1_acc_ctl_freeze_reg, ch_1_acc_gain_val_reg, ch_1_sp_limits_max_val_reg, ch_1_sp_limits_min_val_reg, ch_2_coeff_ram_bank_data_int_dato, ch_2_coeff_ram_bank_data_rack, ch_2_acc_ctl_freeze_reg, ch_2_acc_gain_val_reg, ch_2_sp_limits_max_val_reg, ch_2_sp_limits_min_val_reg, ch_3_coeff_ram_bank_data_int_dato, ch_3_coeff_ram_bank_data_rack, ch_3_acc_ctl_freeze_reg, ch_3_acc_gain_val_reg, ch_3_sp_limits_max_val_reg, ch_3_sp_limits_min_val_reg, ch_4_coeff_ram_bank_data_int_dato, ch_4_coeff_ram_bank_data_rack, ch_4_acc_ctl_freeze_reg, ch_4_acc_gain_val_reg, ch_4_sp_limits_max_val_reg, ch_4_sp_limits_min_val_reg, ch_5_coeff_ram_bank_data_int_dato, ch_5_coeff_ram_bank_data_rack, ch_5_acc_ctl_freeze_reg, ch_5_acc_gain_val_reg, ch_5_sp_limits_max_val_reg, ch_5_sp_limits_min_val_reg, ch_6_coeff_ram_bank_data_int_dato, ch_6_coeff_ram_bank_data_rack, ch_6_acc_ctl_freeze_reg, ch_6_acc_gain_val_reg, ch_6_sp_limits_max_val_reg, ch_6_sp_limits_min_val_reg, ch_7_coeff_ram_bank_data_int_dato, ch_7_coeff_ram_bank_data_rack, ch_7_acc_ctl_freeze_reg, ch_7_acc_gain_val_reg, ch_7_sp_limits_max_val_reg, ch_7_sp_limits_min_val_reg, ch_8_coeff_ram_bank_data_int_dato, ch_8_coeff_ram_bank_data_rack, ch_8_acc_ctl_freeze_reg, ch_8_acc_gain_val_reg, ch_8_sp_limits_max_val_reg, ch_8_sp_limits_min_val_reg, ch_9_coeff_ram_bank_data_int_dato, ch_9_coeff_ram_bank_data_rack, ch_9_acc_ctl_freeze_reg, ch_9_acc_gain_val_reg, ch_9_sp_limits_max_val_reg, ch_9_sp_limits_min_val_reg, ch_10_coeff_ram_bank_data_int_dato, ch_10_coeff_ram_bank_data_rack, ch_10_acc_ctl_freeze_reg, ch_10_acc_gain_val_reg, ch_10_sp_limits_max_val_reg, ch_10_sp_limits_min_val_reg, ch_11_coeff_ram_bank_data_int_dato, ch_11_coeff_ram_bank_data_rack, ch_11_acc_ctl_freeze_reg, ch_11_acc_gain_val_reg, ch_11_sp_limits_max_val_reg, ch_11_sp_limits_min_val_reg) begin + -- By default ack read requests + rd_dat_d0 <= (others => 'X'); + sps_ram_bank_data_rreq <= '0'; + ch_0_coeff_ram_bank_data_rreq <= '0'; + ch_1_coeff_ram_bank_data_rreq <= '0'; + ch_2_coeff_ram_bank_data_rreq <= '0'; + ch_3_coeff_ram_bank_data_rreq <= '0'; + ch_4_coeff_ram_bank_data_rreq <= '0'; + ch_5_coeff_ram_bank_data_rreq <= '0'; + ch_6_coeff_ram_bank_data_rreq <= '0'; + ch_7_coeff_ram_bank_data_rreq <= '0'; + ch_8_coeff_ram_bank_data_rreq <= '0'; + ch_9_coeff_ram_bank_data_rreq <= '0'; + ch_10_coeff_ram_bank_data_rreq <= '0'; + ch_11_coeff_ram_bank_data_rreq <= '0'; + case adr_int(15 downto 11) is + when "00000" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg fixed_point_pos_coeff + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= fixed_point_pos_coeff_val_i; + when "000000001" => + -- Reg fixed_point_pos_accs_gains + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= fixed_point_pos_accs_gains_val_i; + when "000010000" => + -- Reg loop_intlk_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= loop_intlk_ctl_src_en_orb_distort_reg; + rd_dat_d0(2) <= loop_intlk_ctl_src_en_packet_loss_reg; + rd_dat_d0(31 downto 3) <= (others => '0'); + when "000010001" => + -- Reg loop_intlk_sta + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= loop_intlk_sta_orb_distort_i; + rd_dat_d0(1) <= loop_intlk_sta_packet_loss_i; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000010010" => + -- Reg loop_intlk_orb_distort_limit + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= loop_intlk_orb_distort_limit_val_reg; + when "000010011" => + -- Reg loop_intlk_min_num_pkts + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= loop_intlk_min_num_pkts_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "00001" => + -- Memory sps_ram_bank + rd_dat_d0 <= sps_ram_bank_data_int_dato; + sps_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= sps_ram_bank_data_rack; + when "00010" => + -- Memory ch_0_coeff_ram_bank + rd_dat_d0 <= ch_0_coeff_ram_bank_data_int_dato; + ch_0_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_0_coeff_ram_bank_data_rack; + when "00011" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_0_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_0_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_0_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_0_acc_gain_val_reg; + when "000010000" => + -- Reg ch_0_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_0_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_0_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_0_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "00100" => + -- Memory ch_1_coeff_ram_bank + rd_dat_d0 <= ch_1_coeff_ram_bank_data_int_dato; + ch_1_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_1_coeff_ram_bank_data_rack; + when "00101" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_1_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_1_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_1_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_1_acc_gain_val_reg; + when "000010000" => + -- Reg ch_1_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_1_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_1_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_1_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "00110" => + -- Memory ch_2_coeff_ram_bank + rd_dat_d0 <= ch_2_coeff_ram_bank_data_int_dato; + ch_2_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_2_coeff_ram_bank_data_rack; + when "00111" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_2_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_2_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_2_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_2_acc_gain_val_reg; + when "000010000" => + -- Reg ch_2_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_2_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_2_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_2_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "01000" => + -- Memory ch_3_coeff_ram_bank + rd_dat_d0 <= ch_3_coeff_ram_bank_data_int_dato; + ch_3_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_3_coeff_ram_bank_data_rack; + when "01001" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_3_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_3_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_3_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_3_acc_gain_val_reg; + when "000010000" => + -- Reg ch_3_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_3_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_3_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_3_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "01010" => + -- Memory ch_4_coeff_ram_bank + rd_dat_d0 <= ch_4_coeff_ram_bank_data_int_dato; + ch_4_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_4_coeff_ram_bank_data_rack; + when "01011" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_4_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_4_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_4_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_4_acc_gain_val_reg; + when "000010000" => + -- Reg ch_4_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_4_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_4_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_4_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "01100" => + -- Memory ch_5_coeff_ram_bank + rd_dat_d0 <= ch_5_coeff_ram_bank_data_int_dato; + ch_5_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_5_coeff_ram_bank_data_rack; + when "01101" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_5_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_5_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_5_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_5_acc_gain_val_reg; + when "000010000" => + -- Reg ch_5_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_5_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_5_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_5_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "01110" => + -- Memory ch_6_coeff_ram_bank + rd_dat_d0 <= ch_6_coeff_ram_bank_data_int_dato; + ch_6_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_6_coeff_ram_bank_data_rack; + when "01111" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_6_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_6_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_6_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_6_acc_gain_val_reg; + when "000010000" => + -- Reg ch_6_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_6_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_6_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_6_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "10000" => + -- Memory ch_7_coeff_ram_bank + rd_dat_d0 <= ch_7_coeff_ram_bank_data_int_dato; + ch_7_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_7_coeff_ram_bank_data_rack; + when "10001" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_7_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_7_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_7_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_7_acc_gain_val_reg; + when "000010000" => + -- Reg ch_7_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_7_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_7_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_7_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "10010" => + -- Memory ch_8_coeff_ram_bank + rd_dat_d0 <= ch_8_coeff_ram_bank_data_int_dato; + ch_8_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_8_coeff_ram_bank_data_rack; + when "10011" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_8_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_8_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_8_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_8_acc_gain_val_reg; + when "000010000" => + -- Reg ch_8_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_8_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_8_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_8_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "10100" => + -- Memory ch_9_coeff_ram_bank + rd_dat_d0 <= ch_9_coeff_ram_bank_data_int_dato; + ch_9_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_9_coeff_ram_bank_data_rack; + when "10101" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_9_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_9_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_9_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_9_acc_gain_val_reg; + when "000010000" => + -- Reg ch_9_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_9_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_9_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_9_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "10110" => + -- Memory ch_10_coeff_ram_bank + rd_dat_d0 <= ch_10_coeff_ram_bank_data_int_dato; + ch_10_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_10_coeff_ram_bank_data_rack; + when "10111" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_10_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_10_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_10_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_10_acc_gain_val_reg; + when "000010000" => + -- Reg ch_10_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_10_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_10_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_10_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when "11000" => + -- Memory ch_11_coeff_ram_bank + rd_dat_d0 <= ch_11_coeff_ram_bank_data_int_dato; + ch_11_coeff_ram_bank_data_rreq <= rd_req_int; + rd_ack_d0 <= ch_11_coeff_ram_bank_data_rack; + when "11001" => + case adr_int(10 downto 2) is + when "000000000" => + -- Reg ch_11_acc_ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(1) <= ch_11_acc_ctl_freeze_reg; + rd_dat_d0(31 downto 2) <= (others => '0'); + when "000000001" => + -- Reg ch_11_acc_gain + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_11_acc_gain_val_reg; + when "000010000" => + -- Reg ch_11_sp_limits_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_11_sp_limits_max_val_reg; + when "000010001" => + -- Reg ch_11_sp_limits_min + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_11_sp_limits_min_val_reg; + when others => + rd_ack_d0 <= rd_req_int; + end case; + when others => + rd_ack_d0 <= rd_req_int; + end case; + end process; end syn; diff --git a/hdl/modules/fofb_processing/fofb_processing_dcc_adapter.vhd b/hdl/modules/fofb_processing/fofb_processing_dcc_adapter.vhd index d7d8bcf9..e7732c26 100644 --- a/hdl/modules/fofb_processing/fofb_processing_dcc_adapter.vhd +++ b/hdl/modules/fofb_processing/fofb_processing_dcc_adapter.vhd @@ -104,7 +104,6 @@ begin g_with_wr_almost_empty => false, g_with_wr_almost_full => false, g_with_wr_count => false, - g_with_fifo_inferred => false, g_almost_empty_threshold => 0, g_almost_full_threshold => 0 ) diff --git a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd index 8fcc08ca..0f91154e 100644 --- a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd +++ b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd @@ -16,7 +16,9 @@ -- 2022-07-27 1.1 guilherme.ricioli Changed coeffs RAMs' wb interface -- 2022-09-05 2.0 augusto.fraga Update to match the new -- fofb_processing API --- 2022-01-11 2.3 guilherme.ricioli Expose loop interlock regs +-- 2022-01-11 2.1 guilherme.ricioli Expose loop interlock regs +-- 2023-02-10 3.0 guilherme.ricioli Update to match the new +-- wb_fofb_processing_regs api ------------------------------------------------------------------------------- library ieee; @@ -104,8 +106,8 @@ entity xwb_fofb_processing is --------------------------------------------------------------------------- -- Wishbone Control Interface signals --------------------------------------------------------------------------- - wb_slv_i : in t_wishbone_slave_in; - wb_slv_o : out t_wishbone_slave_out + wb_slv_i : in t_wishbone_slave_in; + wb_slv_o : out t_wishbone_slave_out ); end xwb_fofb_processing; @@ -141,44 +143,44 @@ architecture rtl of xwb_fofb_processing is ----------------------------- -- Accumulator clear bit array (for each fofb channel) - signal clear_acc_arr : std_logic_vector(c_MAX_CHANNELS-1 downto 0) := (others => '0'); + signal acc_ctl_clear_arr : std_logic_vector(c_MAX_CHANNELS-1 downto 0) := (others => '0'); -- Accumulator freeze bit array (for each fofb channel) - signal freeze_acc_arr : std_logic_vector(c_MAX_CHANNELS-1 downto 0) := (others => '0'); + signal acc_ctl_freeze_arr : std_logic_vector(c_MAX_CHANNELS-1 downto 0) := (others => '0'); ----------------------------- -- Set-point RAM signals ----------------------------- - signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); - signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + signal sps_ram_bank_adr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal sps_ram_bank_data_dat : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); -- Gain array - signal gain_arr : t_fofb_processing_gain_arr(g_CHANNELS-1 downto 0); - signal wb_gain_arr : t_fofb_processing_wb_gain_arr(c_MAX_CHANNELS-1 downto 0) := (others => (others => '0')); + signal gain_arr : t_fofb_processing_gain_arr(g_CHANNELS-1 downto 0); + signal acc_gain_val_arr : t_fofb_processing_wb_gain_arr(c_MAX_CHANNELS-1 downto 0) := (others => (others => '0')); ----------------------------- -- Coefficients RAM signals ----------------------------- - signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(c_MAX_CHANNELS-1 downto 0); - signal coeff_ram_data_arr : t_arr_coeff_ram_data(c_MAX_CHANNELS-1 downto 0); + signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(c_MAX_CHANNELS-1 downto 0); + signal coeff_ram_data_arr : t_arr_coeff_ram_data(c_MAX_CHANNELS-1 downto 0); ----------------------------- -- Output saturation signals ----------------------------- - signal sp_max_arr : t_fofb_processing_sp_arr(g_CHANNELS-1 downto 0); - signal sp_min_arr : t_fofb_processing_sp_arr(g_CHANNELS-1 downto 0); - signal wb_sp_max_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); - signal wb_sp_min_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); + signal sp_max_arr : t_fofb_processing_sp_arr(g_CHANNELS-1 downto 0); + signal sp_min_arr : t_fofb_processing_sp_arr(g_CHANNELS-1 downto 0); + signal sp_limits_max_val_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); + signal sp_limits_min_val_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); ----------------------------- -- Loop interlock signals ----------------------------- - signal loop_intlk_src_en : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); - signal loop_intlk_state_clr : std_logic; - signal loop_intlk_state : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); - signal loop_intlk_distort_limit : unsigned(g_BPM_POS_INT_WIDTH-1 downto 0); - signal loop_intlk_min_num_meas : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); - signal orb_distort_limit_val : std_logic_vector(31 downto 0); - signal min_num_pkts_val : std_logic_vector(31 downto 0); + signal loop_intlk_src_en : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); + signal loop_intlk_ctl_sta_clr : std_logic; + signal loop_intlk_sta : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); + signal loop_intlk_distort_limit : unsigned(g_BPM_POS_INT_WIDTH-1 downto 0); + signal loop_intlk_min_num_meas : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal loop_intlk_orb_distort_limit_val : std_logic_vector(31 downto 0); + signal loop_intlk_min_num_pkts_val : std_logic_vector(31 downto 0); ----------------------------- -- Wishbone slave adapter signals/structures @@ -195,6 +197,45 @@ architecture rtl of xwb_fofb_processing is begin + cmp_fofb_processing: fofb_processing + generic map ( + g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, + g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, + g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, + g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, + g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, + g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, + g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, + g_USE_MOVING_AVG => g_USE_MOVING_AVG, + g_CHANNELS => g_CHANNELS + ) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + busy_o => busy_o, + bpm_pos_i => bpm_pos_i, + bpm_pos_index_i => bpm_pos_index_i, + bpm_pos_valid_i => bpm_pos_valid_i, + bpm_time_frame_end_i => bpm_time_frame_end_i, + coeff_ram_addr_arr_o => coeff_ram_addr_arr(g_CHANNELS-1 downto 0), + coeff_ram_data_arr_i => coeff_ram_data_arr(g_CHANNELS-1 downto 0), + sp_pos_ram_addr_o => sps_ram_bank_adr, + sp_pos_ram_data_i => sps_ram_bank_data_dat, + gain_arr_i => gain_arr(g_CHANNELS-1 downto 0), + clear_acc_arr_i => acc_ctl_clear_arr(g_CHANNELS-1 downto 0), + freeze_acc_arr_i => acc_ctl_freeze_arr(g_CHANNELS-1 downto 0), + sp_max_arr_i => sp_max_arr, + sp_min_arr_i => sp_min_arr, + sp_arr_o => sp_arr_o, + sp_valid_arr_o => sp_valid_arr_o, + loop_intlk_src_en_i => loop_intlk_src_en, + loop_intlk_state_clr_i => loop_intlk_ctl_sta_clr, + loop_intlk_state_o => loop_intlk_sta, + loop_intlk_distort_limit_i => loop_intlk_distort_limit, + loop_intlk_min_num_meas_i => loop_intlk_min_num_meas + ); + ----------------------------- -- Insert extra Wishbone registering stage for ease timing. -- It effectively cuts the bandwidth in half! @@ -202,274 +243,200 @@ begin gen_with_extra_wb_reg : if g_WITH_EXTRA_WB_REG generate cmp_register_link : xwb_register_link -- puts a register of delay between crossbars port map ( - clk_sys_i => clk_i, - rst_n_i => rst_n_i, - slave_i => wb_slave_in_reg0(0), - slave_o => wb_slave_out_reg0(0), - master_i => wb_slave_out(0), - master_o => wb_slave_in(0) + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + slave_i => wb_slave_in_reg0(0), + slave_o => wb_slave_out_reg0(0), + master_i => wb_slave_out(0), + master_o => wb_slave_in(0) ); - wb_slave_in_reg0(0) <= wb_slv_i; - wb_slv_o <= wb_slave_out_reg0(0); + wb_slave_in_reg0(0) <= wb_slv_i; + wb_slv_o <= wb_slave_out_reg0(0); end generate; gen_without_extra_wb_reg : if not g_WITH_EXTRA_WB_REG generate -- External master connection - wb_slave_in(0) <= wb_slv_i; - wb_slv_o <= wb_slave_out(0); + wb_slave_in(0) <= wb_slv_i; + wb_slv_o <= wb_slave_out(0); end generate; - cmp_fofb_processing: fofb_processing - generic map ( - g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, - g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, - g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, - g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, - g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, - g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, - g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, - g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, - g_USE_MOVING_AVG => g_USE_MOVING_AVG, - g_CHANNELS => g_CHANNELS - ) - port map ( - clk_i => clk_i, - rst_n_i => rst_n_i, - - busy_o => busy_o, - - bpm_pos_i => bpm_pos_i, - bpm_pos_index_i => bpm_pos_index_i, - bpm_pos_valid_i => bpm_pos_valid_i, - bpm_time_frame_end_i => bpm_time_frame_end_i, - - coeff_ram_addr_arr_o => coeff_ram_addr_arr(g_CHANNELS-1 downto 0), - coeff_ram_data_arr_i => coeff_ram_data_arr(g_CHANNELS-1 downto 0), - - sp_pos_ram_addr_o => sp_pos_ram_addr, - sp_pos_ram_data_i => sp_pos_ram_data, - - gain_arr_i => gain_arr(g_CHANNELS-1 downto 0), - - clear_acc_arr_i => clear_acc_arr(g_CHANNELS-1 downto 0), - freeze_acc_arr_i => freeze_acc_arr(g_CHANNELS-1 downto 0), - - sp_max_arr_i => sp_max_arr, - sp_min_arr_i => sp_min_arr, - - sp_arr_o => sp_arr_o, - sp_valid_arr_o => sp_valid_arr_o, - - loop_intlk_src_en_i => loop_intlk_src_en, - loop_intlk_state_clr_i => loop_intlk_state_clr, - loop_intlk_state_o => loop_intlk_state, - loop_intlk_distort_limit_i => loop_intlk_distort_limit, - loop_intlk_min_num_meas_i => loop_intlk_min_num_meas - ); - ----------------------------- -- Slave adapter for Wishbone Register Interface ----------------------------- cmp_slave_adapter : wb_slave_adapter generic map ( - g_master_use_struct => true, - g_master_mode => PIPELINED, - g_master_granularity => WORD, - g_slave_use_struct => false, - g_slave_mode => g_INTERFACE_MODE, - g_slave_granularity => g_ADDRESS_GRANULARITY + g_MASTER_USE_STRUCT => true, + g_MASTER_MODE => PIPELINED, + -- TODO: it seems that using cheby without wbgen compatibility requires + -- g_MASTER_GRANULARITY to be byte + g_MASTER_GRANULARITY => BYTE, + g_SLAVE_USE_STRUCT => false, + g_SLAVE_MODE => g_INTERFACE_MODE, + g_SLAVE_GRANULARITY => g_ADDRESS_GRANULARITY ) port map ( - clk_sys_i => clk_i, - rst_n_i => rst_n_i, - master_i => wb_slv_adp_in, - master_o => wb_slv_adp_out, - sl_adr_i => resized_addr, - sl_dat_i => wb_slave_in(0).dat, - sl_sel_i => wb_slave_in(0).sel, - sl_cyc_i => wb_slave_in(0).cyc, - sl_stb_i => wb_slave_in(0).stb, - sl_we_i => wb_slave_in(0).we, - sl_dat_o => wb_slave_out(0).dat, - sl_ack_o => wb_slave_out(0).ack, - sl_rty_o => wb_slave_out(0).rty, - sl_err_o => wb_slave_out(0).err, - sl_stall_o => wb_slave_out(0).stall + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + master_i => wb_slv_adp_in, + master_o => wb_slv_adp_out, + sl_adr_i => resized_addr, + sl_dat_i => wb_slave_in(0).dat, + sl_sel_i => wb_slave_in(0).sel, + sl_cyc_i => wb_slave_in(0).cyc, + sl_stb_i => wb_slave_in(0).stb, + sl_we_i => wb_slave_in(0).we, + sl_dat_o => wb_slave_out(0).dat, + sl_ack_o => wb_slave_out(0).ack, + sl_rty_o => wb_slave_out(0).rty, + sl_err_o => wb_slave_out(0).err, + sl_stall_o => wb_slave_out(0).stall ); - -- By doing this zeroing we avoid the issue related to BYTE -> WORD conversion - -- slave addressing (possibly performed by the slave adapter component) - -- in which a bit in the MSB of the peripheral addressing part (31 downto c_PERIPH_ADDR_SIZE in our case) - -- is shifted to the internal register adressing part (c_PERIPH_ADDR_SIZE-1 downto 0 in our case). - -- Therefore, possibly changing the these bits! - resized_addr(c_PERIPH_ADDR_SIZE-1 downto 0) - <= wb_slave_in(0).adr(c_PERIPH_ADDR_SIZE-1 downto 0); - resized_addr(c_WISHBONE_ADDRESS_WIDTH-1 downto c_PERIPH_ADDR_SIZE) - <= (others => '0'); + + gen_wb_slave_in_addr_conn : if g_ADDRESS_GRANULARITY = WORD generate + -- By doing this zeroing we avoid the issue related to BYTE -> WORD conversion + -- slave addressing (possibly performed by the slave adapter component) + -- in which a bit in the MSB of the peripheral addressing part (31 downto c_PERIPH_ADDR_SIZE in our case) + -- is shifted to the internal register adressing part (c_PERIPH_ADDR_SIZE-1 downto 0 in our case). + -- Therefore, possibly changing the these bits! + resized_addr(c_PERIPH_ADDR_SIZE-1 downto 0) + <= wb_slave_in(0).adr(c_PERIPH_ADDR_SIZE-1 downto 0); + resized_addr(c_WISHBONE_ADDRESS_WIDTH-1 downto c_PERIPH_ADDR_SIZE) + <= (others => '0'); + else generate + resized_addr <= wb_slave_in(0).adr; + end generate; + gen_wb_conn: for i in 0 to g_CHANNELS-1 generate -- fixed-point values are aligned to the left - gain_arr(i) <= signed(wb_gain_arr(i)(c_FOFB_WB_GAIN_WIDTH-1 downto c_FOFB_WB_GAIN_WIDTH-c_FOFB_GAIN_WIDTH)); + gain_arr(i) <= signed(acc_gain_val_arr(i)(c_FOFB_WB_GAIN_WIDTH-1 downto c_FOFB_WB_GAIN_WIDTH-c_FOFB_GAIN_WIDTH)); - sp_max_arr(i) <= signed(wb_sp_max_arr(i)(c_FOFB_SP_WIDTH-1 downto 0)); - sp_min_arr(i) <= signed(wb_sp_min_arr(i)(c_FOFB_SP_WIDTH-1 downto 0)); + sp_max_arr(i) <= signed(sp_limits_max_val_arr(i)(c_FOFB_SP_WIDTH-1 downto 0)); + sp_min_arr(i) <= signed(sp_limits_min_val_arr(i)(c_FOFB_SP_WIDTH-1 downto 0)); end generate gen_wb_conn; - loop_intlk_distort_limit <= unsigned(orb_distort_limit_val(loop_intlk_distort_limit'left downto 0)); + loop_intlk_distort_limit <= unsigned(loop_intlk_orb_distort_limit_val(loop_intlk_distort_limit'left downto 0)); -- Each DCC packet has 2 measurements - loop_intlk_min_num_meas <= shift_left(unsigned(min_num_pkts_val(loop_intlk_min_num_meas'left downto 0)), 1); + loop_intlk_min_num_meas <= shift_left(unsigned(loop_intlk_min_num_pkts_val(loop_intlk_min_num_meas'left downto 0)), 1); cmp_wb_fofb_processing_regs: entity work.wb_fofb_processing_regs port map ( - rst_n_i => rst_n_i, - clk_sys_i => clk_i, - wb_adr_i => wb_slv_adp_out.adr(12 downto 0), - wb_dat_i => wb_slv_adp_out.dat(31 downto 0), - wb_dat_o => wb_slv_adp_in.dat(31 downto 0), - wb_cyc_i => wb_slv_adp_out.cyc, - wb_sel_i => wb_slv_adp_out.sel(3 downto 0), - wb_stb_i => wb_slv_adp_out.stb, - wb_we_i => wb_slv_adp_out.we, - wb_ack_o => wb_slv_adp_in.ack, - wb_stall_o => wb_slv_adp_in.stall, - wb_fofb_processing_regs_clk_i => clk_i, - wb_fofb_processing_regs_coeffs_fixed_point_pos_val_i => c_COEFF_FIXED_POINT_POS_VAL, - wb_fofb_processing_regs_accs_gains_fixed_point_pos_val_i => c_GAIN_FIXED_POINT_POS_VAL, - wb_fofb_processing_regs_acc_gain_0_val_o => wb_gain_arr(0), - wb_fofb_processing_regs_acc_ctl_0_clear_o => clear_acc_arr(0), - wb_fofb_processing_regs_acc_ctl_0_freeze_o => freeze_acc_arr(0), - wb_fofb_processing_regs_acc_gain_1_val_o => wb_gain_arr(1), - wb_fofb_processing_regs_acc_ctl_1_clear_o => clear_acc_arr(1), - wb_fofb_processing_regs_acc_ctl_1_freeze_o => freeze_acc_arr(1), - wb_fofb_processing_regs_acc_gain_2_val_o => wb_gain_arr(2), - wb_fofb_processing_regs_acc_ctl_2_clear_o => clear_acc_arr(2), - wb_fofb_processing_regs_acc_ctl_2_freeze_o => freeze_acc_arr(2), - wb_fofb_processing_regs_acc_gain_3_val_o => wb_gain_arr(3), - wb_fofb_processing_regs_acc_ctl_3_clear_o => clear_acc_arr(3), - wb_fofb_processing_regs_acc_ctl_3_freeze_o => freeze_acc_arr(3), - wb_fofb_processing_regs_acc_gain_4_val_o => wb_gain_arr(4), - wb_fofb_processing_regs_acc_ctl_4_clear_o => clear_acc_arr(4), - wb_fofb_processing_regs_acc_ctl_4_freeze_o => freeze_acc_arr(4), - wb_fofb_processing_regs_acc_gain_5_val_o => wb_gain_arr(5), - wb_fofb_processing_regs_acc_ctl_5_clear_o => clear_acc_arr(5), - wb_fofb_processing_regs_acc_ctl_5_freeze_o => freeze_acc_arr(5), - wb_fofb_processing_regs_acc_gain_6_val_o => wb_gain_arr(6), - wb_fofb_processing_regs_acc_ctl_6_clear_o => clear_acc_arr(6), - wb_fofb_processing_regs_acc_ctl_6_freeze_o => freeze_acc_arr(6), - wb_fofb_processing_regs_acc_gain_7_val_o => wb_gain_arr(7), - wb_fofb_processing_regs_acc_ctl_7_clear_o => clear_acc_arr(7), - wb_fofb_processing_regs_acc_ctl_7_freeze_o => freeze_acc_arr(7), - wb_fofb_processing_regs_acc_gain_8_val_o => wb_gain_arr(8), - wb_fofb_processing_regs_acc_ctl_8_clear_o => clear_acc_arr(8), - wb_fofb_processing_regs_acc_ctl_8_freeze_o => freeze_acc_arr(8), - wb_fofb_processing_regs_acc_gain_9_val_o => wb_gain_arr(9), - wb_fofb_processing_regs_acc_ctl_9_clear_o => clear_acc_arr(9), - wb_fofb_processing_regs_acc_ctl_9_freeze_o => freeze_acc_arr(9), - wb_fofb_processing_regs_acc_gain_10_val_o => wb_gain_arr(10), - wb_fofb_processing_regs_acc_ctl_10_clear_o => clear_acc_arr(10), - wb_fofb_processing_regs_acc_ctl_10_freeze_o => freeze_acc_arr(10), - wb_fofb_processing_regs_acc_gain_11_val_o => wb_gain_arr(11), - wb_fofb_processing_regs_acc_ctl_11_clear_o => clear_acc_arr(11), - wb_fofb_processing_regs_acc_ctl_11_freeze_o => freeze_acc_arr(11), - wb_fofb_processing_regs_sp_max_0_val_o => wb_sp_max_arr(0), - wb_fofb_processing_regs_sp_min_0_val_o => wb_sp_min_arr(0), - wb_fofb_processing_regs_sp_max_1_val_o => wb_sp_max_arr(1), - wb_fofb_processing_regs_sp_min_1_val_o => wb_sp_min_arr(1), - wb_fofb_processing_regs_sp_max_2_val_o => wb_sp_max_arr(2), - wb_fofb_processing_regs_sp_min_2_val_o => wb_sp_min_arr(2), - wb_fofb_processing_regs_sp_max_3_val_o => wb_sp_max_arr(3), - wb_fofb_processing_regs_sp_min_3_val_o => wb_sp_min_arr(3), - wb_fofb_processing_regs_sp_max_4_val_o => wb_sp_max_arr(4), - wb_fofb_processing_regs_sp_min_4_val_o => wb_sp_min_arr(4), - wb_fofb_processing_regs_sp_max_5_val_o => wb_sp_max_arr(5), - wb_fofb_processing_regs_sp_min_5_val_o => wb_sp_min_arr(5), - wb_fofb_processing_regs_sp_max_6_val_o => wb_sp_max_arr(6), - wb_fofb_processing_regs_sp_min_6_val_o => wb_sp_min_arr(6), - wb_fofb_processing_regs_sp_max_7_val_o => wb_sp_max_arr(7), - wb_fofb_processing_regs_sp_min_7_val_o => wb_sp_min_arr(7), - wb_fofb_processing_regs_sp_max_8_val_o => wb_sp_max_arr(8), - wb_fofb_processing_regs_sp_min_8_val_o => wb_sp_min_arr(8), - wb_fofb_processing_regs_sp_max_9_val_o => wb_sp_max_arr(9), - wb_fofb_processing_regs_sp_min_9_val_o => wb_sp_min_arr(9), - wb_fofb_processing_regs_sp_max_10_val_o => wb_sp_max_arr(10), - wb_fofb_processing_regs_sp_min_10_val_o => wb_sp_min_arr(10), - wb_fofb_processing_regs_sp_max_11_val_o => wb_sp_max_arr(11), - wb_fofb_processing_regs_sp_min_11_val_o => wb_sp_min_arr(11), - wb_fofb_processing_regs_coeffs_ram_bank_0_addr_i => coeff_ram_addr_arr(0), - wb_fofb_processing_regs_coeffs_ram_bank_0_data_o => coeff_ram_data_arr(0), - wb_fofb_processing_regs_coeffs_ram_bank_0_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_0_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_0_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_1_addr_i => coeff_ram_addr_arr(1), - wb_fofb_processing_regs_coeffs_ram_bank_1_data_o => coeff_ram_data_arr(1), - wb_fofb_processing_regs_coeffs_ram_bank_1_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_1_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_1_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_2_addr_i => coeff_ram_addr_arr(2), - wb_fofb_processing_regs_coeffs_ram_bank_2_data_o => coeff_ram_data_arr(2), - wb_fofb_processing_regs_coeffs_ram_bank_2_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_2_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_2_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_3_addr_i => coeff_ram_addr_arr(3), - wb_fofb_processing_regs_coeffs_ram_bank_3_data_o => coeff_ram_data_arr(3), - wb_fofb_processing_regs_coeffs_ram_bank_3_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_3_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_3_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_4_addr_i => coeff_ram_addr_arr(4), - wb_fofb_processing_regs_coeffs_ram_bank_4_data_o => coeff_ram_data_arr(4), - wb_fofb_processing_regs_coeffs_ram_bank_4_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_4_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_4_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_5_addr_i => coeff_ram_addr_arr(5), - wb_fofb_processing_regs_coeffs_ram_bank_5_data_o => coeff_ram_data_arr(5), - wb_fofb_processing_regs_coeffs_ram_bank_5_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_5_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_5_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_6_addr_i => coeff_ram_addr_arr(6), - wb_fofb_processing_regs_coeffs_ram_bank_6_data_o => coeff_ram_data_arr(6), - wb_fofb_processing_regs_coeffs_ram_bank_6_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_6_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_6_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_7_addr_i => coeff_ram_addr_arr(7), - wb_fofb_processing_regs_coeffs_ram_bank_7_data_o => coeff_ram_data_arr(7), - wb_fofb_processing_regs_coeffs_ram_bank_7_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_7_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_7_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_8_addr_i => coeff_ram_addr_arr(8), - wb_fofb_processing_regs_coeffs_ram_bank_8_data_o => coeff_ram_data_arr(8), - wb_fofb_processing_regs_coeffs_ram_bank_8_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_8_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_8_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_9_addr_i => coeff_ram_addr_arr(9), - wb_fofb_processing_regs_coeffs_ram_bank_9_data_o => coeff_ram_data_arr(9), - wb_fofb_processing_regs_coeffs_ram_bank_9_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_9_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_9_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_10_addr_i => coeff_ram_addr_arr(10), - wb_fofb_processing_regs_coeffs_ram_bank_10_data_o => coeff_ram_data_arr(10), - wb_fofb_processing_regs_coeffs_ram_bank_10_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_10_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_10_wr_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_11_addr_i => coeff_ram_addr_arr(11), - wb_fofb_processing_regs_coeffs_ram_bank_11_data_o => coeff_ram_data_arr(11), - wb_fofb_processing_regs_coeffs_ram_bank_11_rd_i => '0', - wb_fofb_processing_regs_coeffs_ram_bank_11_data_i => (others => '0'), - wb_fofb_processing_regs_coeffs_ram_bank_11_wr_i => '0', - wb_fofb_processing_regs_setpoints_ram_bank_addr_i => sp_pos_ram_addr, - wb_fofb_processing_regs_setpoints_ram_bank_data_o => sp_pos_ram_data, - wb_fofb_processing_regs_setpoints_ram_bank_rd_i => '0', - wb_fofb_processing_regs_setpoints_ram_bank_data_i => (others => '0'), - wb_fofb_processing_regs_setpoints_ram_bank_wr_i => '0', - wb_fofb_processing_regs_loop_intlk_src_en_ctl_orb_distort_en_o => loop_intlk_src_en(c_FOFB_LOOP_INTLK_DISTORT_ID), - wb_fofb_processing_regs_loop_intlk_src_en_ctl_packet_loss_en_o => loop_intlk_src_en(c_FOFB_LOOP_INTLK_PKT_LOSS_ID), - wb_fofb_processing_regs_loop_intlk_ctl_clr_o => loop_intlk_state_clr, - wb_fofb_processing_regs_loop_intlk_sta_orb_distort_i => loop_intlk_state(c_FOFB_LOOP_INTLK_DISTORT_ID), - wb_fofb_processing_regs_loop_intlk_sta_packet_loss_i => loop_intlk_state(c_FOFB_LOOP_INTLK_PKT_LOSS_ID), - wb_fofb_processing_regs_orb_distort_limit_val_o => orb_distort_limit_val, - wb_fofb_processing_regs_min_num_pkts_val_o => min_num_pkts_val + rst_n_i => rst_n_i, + clk_i => clk_i, + wb_i => wb_slv_adp_out, + wb_o => wb_slv_adp_in, + fixed_point_pos_coeff_val_i => c_COEFF_FIXED_POINT_POS_VAL, + fixed_point_pos_accs_gains_val_i => c_GAIN_FIXED_POINT_POS_VAL, + loop_intlk_ctl_sta_clr_o => loop_intlk_ctl_sta_clr, + loop_intlk_ctl_src_en_orb_distort_o => loop_intlk_src_en(c_FOFB_LOOP_INTLK_DISTORT_ID), + loop_intlk_ctl_src_en_packet_loss_o => loop_intlk_src_en(c_FOFB_LOOP_INTLK_PKT_LOSS_ID), + loop_intlk_sta_orb_distort_i => loop_intlk_sta(c_FOFB_LOOP_INTLK_DISTORT_ID), + loop_intlk_sta_packet_loss_i => loop_intlk_sta(c_FOFB_LOOP_INTLK_PKT_LOSS_ID), + loop_intlk_orb_distort_limit_val_o => loop_intlk_orb_distort_limit_val, + loop_intlk_min_num_pkts_val_o => loop_intlk_min_num_pkts_val, + sps_ram_bank_adr_i => sps_ram_bank_adr, + sps_ram_bank_data_rd_i => '0', + sps_ram_bank_data_dat_o => sps_ram_bank_data_dat, + ch_0_coeff_ram_bank_adr_i => coeff_ram_addr_arr(0), + ch_0_coeff_ram_bank_data_rd_i => '0', + ch_0_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(0), + ch_0_acc_ctl_clear_o => acc_ctl_clear_arr(0), + ch_0_acc_ctl_freeze_o => acc_ctl_freeze_arr(0), + ch_0_acc_gain_val_o => acc_gain_val_arr(0), + ch_0_sp_limits_max_val_o => sp_limits_max_val_arr(0), + ch_0_sp_limits_min_val_o => sp_limits_min_val_arr(0), + ch_1_coeff_ram_bank_adr_i => coeff_ram_addr_arr(1), + ch_1_coeff_ram_bank_data_rd_i => '0', + ch_1_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(1), + ch_1_acc_ctl_clear_o => acc_ctl_clear_arr(1), + ch_1_acc_ctl_freeze_o => acc_ctl_freeze_arr(1), + ch_1_acc_gain_val_o => acc_gain_val_arr(1), + ch_1_sp_limits_max_val_o => sp_limits_max_val_arr(1), + ch_1_sp_limits_min_val_o => sp_limits_min_val_arr(1), + ch_2_coeff_ram_bank_adr_i => coeff_ram_addr_arr(2), + ch_2_coeff_ram_bank_data_rd_i => '0', + ch_2_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(2), + ch_2_acc_ctl_clear_o => acc_ctl_clear_arr(2), + ch_2_acc_ctl_freeze_o => acc_ctl_freeze_arr(2), + ch_2_acc_gain_val_o => acc_gain_val_arr(2), + ch_2_sp_limits_max_val_o => sp_limits_max_val_arr(2), + ch_2_sp_limits_min_val_o => sp_limits_min_val_arr(2), + ch_3_coeff_ram_bank_adr_i => coeff_ram_addr_arr(3), + ch_3_coeff_ram_bank_data_rd_i => '0', + ch_3_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(3), + ch_3_acc_ctl_clear_o => acc_ctl_clear_arr(3), + ch_3_acc_ctl_freeze_o => acc_ctl_freeze_arr(3), + ch_3_acc_gain_val_o => acc_gain_val_arr(3), + ch_3_sp_limits_max_val_o => sp_limits_max_val_arr(3), + ch_3_sp_limits_min_val_o => sp_limits_min_val_arr(3), + ch_4_coeff_ram_bank_adr_i => coeff_ram_addr_arr(4), + ch_4_coeff_ram_bank_data_rd_i => '0', + ch_4_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(4), + ch_4_acc_ctl_clear_o => acc_ctl_clear_arr(4), + ch_4_acc_ctl_freeze_o => acc_ctl_freeze_arr(4), + ch_4_acc_gain_val_o => acc_gain_val_arr(4), + ch_4_sp_limits_max_val_o => sp_limits_max_val_arr(4), + ch_4_sp_limits_min_val_o => sp_limits_min_val_arr(4), + ch_5_coeff_ram_bank_adr_i => coeff_ram_addr_arr(5), + ch_5_coeff_ram_bank_data_rd_i => '0', + ch_5_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(5), + ch_5_acc_ctl_clear_o => acc_ctl_clear_arr(5), + ch_5_acc_ctl_freeze_o => acc_ctl_freeze_arr(5), + ch_5_acc_gain_val_o => acc_gain_val_arr(5), + ch_5_sp_limits_max_val_o => sp_limits_max_val_arr(5), + ch_5_sp_limits_min_val_o => sp_limits_min_val_arr(5), + ch_6_coeff_ram_bank_adr_i => coeff_ram_addr_arr(6), + ch_6_coeff_ram_bank_data_rd_i => '0', + ch_6_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(6), + ch_6_acc_ctl_clear_o => acc_ctl_clear_arr(6), + ch_6_acc_ctl_freeze_o => acc_ctl_freeze_arr(6), + ch_6_acc_gain_val_o => acc_gain_val_arr(6), + ch_6_sp_limits_max_val_o => sp_limits_max_val_arr(6), + ch_6_sp_limits_min_val_o => sp_limits_min_val_arr(6), + ch_7_coeff_ram_bank_adr_i => coeff_ram_addr_arr(7), + ch_7_coeff_ram_bank_data_rd_i => '0', + ch_7_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(7), + ch_7_acc_ctl_clear_o => acc_ctl_clear_arr(7), + ch_7_acc_ctl_freeze_o => acc_ctl_freeze_arr(7), + ch_7_acc_gain_val_o => acc_gain_val_arr(7), + ch_7_sp_limits_max_val_o => sp_limits_max_val_arr(7), + ch_7_sp_limits_min_val_o => sp_limits_min_val_arr(7), + ch_8_coeff_ram_bank_adr_i => coeff_ram_addr_arr(8), + ch_8_coeff_ram_bank_data_rd_i => '0', + ch_8_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(8), + ch_8_acc_ctl_clear_o => acc_ctl_clear_arr(8), + ch_8_acc_ctl_freeze_o => acc_ctl_freeze_arr(8), + ch_8_acc_gain_val_o => acc_gain_val_arr(8), + ch_8_sp_limits_max_val_o => sp_limits_max_val_arr(8), + ch_8_sp_limits_min_val_o => sp_limits_min_val_arr(8), + ch_9_coeff_ram_bank_adr_i => coeff_ram_addr_arr(9), + ch_9_coeff_ram_bank_data_rd_i => '0', + ch_9_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(9), + ch_9_acc_ctl_clear_o => acc_ctl_clear_arr(9), + ch_9_acc_ctl_freeze_o => acc_ctl_freeze_arr(9), + ch_9_acc_gain_val_o => acc_gain_val_arr(9), + ch_9_sp_limits_max_val_o => sp_limits_max_val_arr(9), + ch_9_sp_limits_min_val_o => sp_limits_min_val_arr(9), + ch_10_coeff_ram_bank_adr_i => coeff_ram_addr_arr(10), + ch_10_coeff_ram_bank_data_rd_i => '0', + ch_10_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(10), + ch_10_acc_ctl_clear_o => acc_ctl_clear_arr(10), + ch_10_acc_ctl_freeze_o => acc_ctl_freeze_arr(10), + ch_10_acc_gain_val_o => acc_gain_val_arr(10), + ch_10_sp_limits_max_val_o => sp_limits_max_val_arr(10), + ch_10_sp_limits_min_val_o => sp_limits_min_val_arr(10), + ch_11_coeff_ram_bank_adr_i => coeff_ram_addr_arr(11), + ch_11_coeff_ram_bank_data_rd_i => '0', + ch_11_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(11), + ch_11_acc_ctl_clear_o => acc_ctl_clear_arr(11), + ch_11_acc_ctl_freeze_o => acc_ctl_freeze_arr(11), + ch_11_acc_gain_val_o => acc_gain_val_arr(11), + ch_11_sp_limits_max_val_o => sp_limits_max_val_arr(11), + ch_11_sp_limits_min_val_o => sp_limits_min_val_arr(11) ); - dcc_p2p_en_o <= not loop_intlk_state(c_FOFB_LOOP_INTLK_PKT_LOSS_ID); + dcc_p2p_en_o <= not loop_intlk_sta(c_FOFB_LOOP_INTLK_PKT_LOSS_ID); end architecture rtl; diff --git a/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd index d22fd6a1..2a99603e 100644 --- a/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd @@ -1,166 +1,243 @@ package wb_fofb_processing_regs_consts_pkg is - constant c_WB_FOFB_PROCESSING_REGS_SIZE : Natural := 28672; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_FIXED_POINT_POS_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_FIXED_POINT_POS_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACCS_GAINS_FIXED_POINT_POS_ADDR : Natural := 16#4#; - constant c_WB_FOFB_PROCESSING_REGS_ACCS_GAINS_FIXED_POINT_POS_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_ADDR : Natural := 16#8#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR : Natural := 16#c#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_1_ADDR : Natural := 16#10#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_1_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_ADDR : Natural := 16#14#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_2_ADDR : Natural := 16#18#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_2_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_2_ADDR : Natural := 16#1c#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_2_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_2_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_3_ADDR : Natural := 16#20#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_3_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_3_ADDR : Natural := 16#24#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_3_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_3_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_4_ADDR : Natural := 16#28#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_4_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_4_ADDR : Natural := 16#2c#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_4_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_4_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_5_ADDR : Natural := 16#30#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_5_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_5_ADDR : Natural := 16#34#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_5_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_5_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_6_ADDR : Natural := 16#38#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_6_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_6_ADDR : Natural := 16#3c#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_6_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_6_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_7_ADDR : Natural := 16#40#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_7_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_7_ADDR : Natural := 16#44#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_7_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_7_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_8_ADDR : Natural := 16#48#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_8_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_8_ADDR : Natural := 16#4c#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_8_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_8_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_9_ADDR : Natural := 16#50#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_9_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_9_ADDR : Natural := 16#54#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_9_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_9_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_10_ADDR : Natural := 16#58#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_10_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_10_ADDR : Natural := 16#5c#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_10_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_10_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_11_ADDR : Natural := 16#60#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_11_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_11_ADDR : Natural := 16#64#; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_11_CLEAR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_ACC_CTL_11_FREEZE_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_0_ADDR : Natural := 16#68#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_0_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_0_ADDR : Natural := 16#6c#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_0_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_1_ADDR : Natural := 16#70#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_1_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_1_ADDR : Natural := 16#74#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_1_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_2_ADDR : Natural := 16#78#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_2_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_2_ADDR : Natural := 16#7c#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_2_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_3_ADDR : Natural := 16#80#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_3_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_3_ADDR : Natural := 16#84#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_3_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_4_ADDR : Natural := 16#88#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_4_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_4_ADDR : Natural := 16#8c#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_4_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_5_ADDR : Natural := 16#90#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_5_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_5_ADDR : Natural := 16#94#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_5_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_6_ADDR : Natural := 16#98#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_6_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_6_ADDR : Natural := 16#9c#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_6_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_7_ADDR : Natural := 16#a0#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_7_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_7_ADDR : Natural := 16#a4#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_7_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_8_ADDR : Natural := 16#a8#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_8_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_8_ADDR : Natural := 16#ac#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_8_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_9_ADDR : Natural := 16#b0#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_9_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_9_ADDR : Natural := 16#b4#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_9_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_10_ADDR : Natural := 16#b8#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_10_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_10_ADDR : Natural := 16#bc#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_10_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_11_ADDR : Natural := 16#c0#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MAX_11_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_11_ADDR : Natural := 16#c4#; - constant c_WB_FOFB_PROCESSING_REGS_SP_MIN_11_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ADDR : Natural := 16#c8#; - constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR : Natural := 16#cc#; - constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_CLR_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ADDR : Natural := 16#d0#; + constant c_WB_FOFB_PROCESSING_REGS_SIZE : Natural := 53248; + constant c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_COEFF_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_COEFF_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ACCS_GAINS_ADDR : Natural := 16#4#; + constant c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ACCS_GAINS_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ADDR : Natural := 16#40#; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR : Natural := 16#40#; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_STA_CLR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET : Natural := 2; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ADDR : Natural := 16#44#; constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ORB_DISTORT_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_PACKET_LOSS_OFFSET : Natural := 1; - constant c_WB_FOFB_PROCESSING_REGS_ORB_DISTORT_LIMIT_ADDR : Natural := 16#d4#; - constant c_WB_FOFB_PROCESSING_REGS_ORB_DISTORT_LIMIT_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_MIN_NUM_PKTS_ADDR : Natural := 16#d8#; - constant c_WB_FOFB_PROCESSING_REGS_MIN_NUM_PKTS_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_ADDR : Natural := 16#800#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1_ADDR : Natural := 16#1000#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_2_ADDR : Natural := 16#1800#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_2_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_2_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_3_ADDR : Natural := 16#2000#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_3_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_3_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_4_ADDR : Natural := 16#2800#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_4_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_4_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_5_ADDR : Natural := 16#3000#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_5_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_5_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_6_ADDR : Natural := 16#3800#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_6_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_6_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_7_ADDR : Natural := 16#4000#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_7_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_7_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_8_ADDR : Natural := 16#4800#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_8_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_8_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_9_ADDR : Natural := 16#5000#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_9_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_9_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_10_ADDR : Natural := 16#5800#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_10_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_10_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_11_ADDR : Natural := 16#6000#; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_11_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_11_DATA_ADDR : Natural := 16#0#; - constant c_WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_ADDR : Natural := 16#6800#; - constant c_WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_SIZE : Natural := 4; - constant c_WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT_ADDR : Natural := 16#48#; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_ADDR : Natural := 16#4c#; + constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_ADDR : Natural := 16#800#; + constant c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_ADDR : Natural := 16#1000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_SIZE : Natural := 49152; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR : Natural := 16#1000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_ADDR : Natural := 16#1000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_ADDR : Natural := 16#1800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR : Natural := 16#1800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_GAIN_ADDR : Natural := 16#1804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_ADDR : Natural := 16#1840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_ADDR : Natural := 16#1840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_ADDR : Natural := 16#1844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ADDR : Natural := 16#2000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_COEFF_RAM_BANK_ADDR : Natural := 16#2000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_ADDR : Natural := 16#2800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_ADDR : Natural := 16#2800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_GAIN_ADDR : Natural := 16#2804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_ADDR : Natural := 16#2840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MAX_ADDR : Natural := 16#2840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_ADDR : Natural := 16#2844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ADDR : Natural := 16#3000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_COEFF_RAM_BANK_ADDR : Natural := 16#3000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_ADDR : Natural := 16#3800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_CTL_ADDR : Natural := 16#3800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_GAIN_ADDR : Natural := 16#3804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_ADDR : Natural := 16#3840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MAX_ADDR : Natural := 16#3840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_ADDR : Natural := 16#3844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ADDR : Natural := 16#4000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_COEFF_RAM_BANK_ADDR : Natural := 16#4000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_ADDR : Natural := 16#4800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_CTL_ADDR : Natural := 16#4800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_GAIN_ADDR : Natural := 16#4804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_ADDR : Natural := 16#4840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MAX_ADDR : Natural := 16#4840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_ADDR : Natural := 16#4844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ADDR : Natural := 16#5000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_COEFF_RAM_BANK_ADDR : Natural := 16#5000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_ADDR : Natural := 16#5800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_CTL_ADDR : Natural := 16#5800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_GAIN_ADDR : Natural := 16#5804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_ADDR : Natural := 16#5840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MAX_ADDR : Natural := 16#5840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_ADDR : Natural := 16#5844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ADDR : Natural := 16#6000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_COEFF_RAM_BANK_ADDR : Natural := 16#6000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_ADDR : Natural := 16#6800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_CTL_ADDR : Natural := 16#6800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_GAIN_ADDR : Natural := 16#6804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_ADDR : Natural := 16#6840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MAX_ADDR : Natural := 16#6840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_ADDR : Natural := 16#6844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ADDR : Natural := 16#7000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_COEFF_RAM_BANK_ADDR : Natural := 16#7000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_ADDR : Natural := 16#7800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_CTL_ADDR : Natural := 16#7800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_GAIN_ADDR : Natural := 16#7804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_ADDR : Natural := 16#7840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MAX_ADDR : Natural := 16#7840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_ADDR : Natural := 16#7844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ADDR : Natural := 16#8000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_COEFF_RAM_BANK_ADDR : Natural := 16#8000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_ADDR : Natural := 16#8800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_CTL_ADDR : Natural := 16#8800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_GAIN_ADDR : Natural := 16#8804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_ADDR : Natural := 16#8840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MAX_ADDR : Natural := 16#8840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_ADDR : Natural := 16#8844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ADDR : Natural := 16#9000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_COEFF_RAM_BANK_ADDR : Natural := 16#9000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_ADDR : Natural := 16#9800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_CTL_ADDR : Natural := 16#9800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_GAIN_ADDR : Natural := 16#9804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_ADDR : Natural := 16#9840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MAX_ADDR : Natural := 16#9840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_ADDR : Natural := 16#9844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ADDR : Natural := 16#a000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_COEFF_RAM_BANK_ADDR : Natural := 16#a000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_ADDR : Natural := 16#a800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_CTL_ADDR : Natural := 16#a800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_GAIN_ADDR : Natural := 16#a804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_ADDR : Natural := 16#a840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MAX_ADDR : Natural := 16#a840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_ADDR : Natural := 16#a844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ADDR : Natural := 16#b000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_COEFF_RAM_BANK_ADDR : Natural := 16#b000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_ADDR : Natural := 16#b800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_CTL_ADDR : Natural := 16#b800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_GAIN_ADDR : Natural := 16#b804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_ADDR : Natural := 16#b840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MAX_ADDR : Natural := 16#b840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_ADDR : Natural := 16#b844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ADDR : Natural := 16#c000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SIZE : Natural := 4096; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_COEFF_RAM_BANK_ADDR : Natural := 16#c000#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_COEFF_RAM_BANK_SIZE : Natural := 4; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_ADDR : Natural := 16#c800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_CTL_ADDR : Natural := 16#c800#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_CTL_CLEAR_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_CTL_FREEZE_OFFSET : Natural := 1; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_GAIN_ADDR : Natural := 16#c804#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_GAIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_ADDR : Natural := 16#c840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MAX_ADDR : Natural := 16#c840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_ADDR : Natural := 16#c844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; end package wb_fofb_processing_regs_consts_pkg; diff --git a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd index e4df1c78..86476dce 100644 --- a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd +++ b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd @@ -23,6 +23,8 @@ -- accumulators regs -- 2022-01-11 2.3 guilherme.ricioli Test wishbone interface for -- loop interlock regs +-- 2023-02-15 3.0 guilherme.ricioli Update to match the new +-- wb_fofb_processing_regs api ------------------------------------------------------------------------------- library ieee; @@ -105,11 +107,11 @@ architecture xwb_fofb_processing_tb_arch of xwb_fofb_processing_tb is constant c_SYS_CLOCK_FREQ : natural := 100_000_000; constant c_RAM_BANK_SIZE : natural := - (c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_1_ADDR - - c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_ADDR); + (c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_ADDR); constant c_NUM_OF_COEFFS_PER_CHANNEL : natural := - c_RAM_BANK_SIZE / c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_SIZE; + c_RAM_BANK_SIZE / c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_SIZE; constant c_NUM_OF_SETPOINTS : natural := c_NUM_OF_COEFFS_PER_CHANNEL; @@ -153,12 +155,26 @@ architecture xwb_fofb_processing_tb_arch of xwb_fofb_processing_tb is -- TODO: used to solve 'actual signal must be a static name' error signal valid_to_check : std_logic := '0'; + function f_get_ch_reg_addr(offs: natural; ch: natural) return natural is + constant c_CH_REGS_BASE_ADDR : natural := c_WB_FOFB_PROCESSING_REGS_CH_ADDR; + constant c_CH_REGS_SIZE_PER_CH : natural := c_WB_FOFB_PROCESSING_REGS_CH_0_SIZE; + begin + assert (offs <= c_CH_REGS_SIZE_PER_CH and ch <= g_CHANNELS-1) + report "improper params: offs: " & natural'image(offs) & ", ch: " & + natural'image(ch) + severity error; + + return c_CH_REGS_BASE_ADDR + ch * c_CH_REGS_SIZE_PER_CH + offs; + end function; + begin f_gen_clk(c_SYS_CLOCK_FREQ, clk); + -- main process process variable addr : natural := 0; + variable offs : natural := 0; variable data : std_logic_vector(31 downto 0) := (others => '0'); @@ -210,38 +226,38 @@ begin rst_n <= '1'; f_wait_cycles(clk, 10); - -- writing on coefficients rams via wishbone bus - report "writing on coefficients rams via wishbone bus" + -- writing on coefficients rams + report "writing on coefficients rams" severity note; read32_pl(clk, wb_slave_i, wb_slave_o, - c_WB_FOFB_PROCESSING_REGS_COEFFS_FIXED_POINT_POS_ADDR, data); + c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_COEFF_ADDR, data); report "coefficients fixed-point position: " & to_hstring(data) severity note; - addr := c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_ADDR; + offs := c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR; for i in 0 to (g_CHANNELS - 1) loop for j in 0 to (c_NUM_OF_COEFFS_PER_CHANNEL - 1) loop + addr := f_get_ch_reg_addr(offs + + j*c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_SIZE, i); + write32_pl(clk, wb_slave_i, wb_slave_o, addr, coeff_ram.get_coeff(j)); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); assert (data = coeff_ram.get_coeff(j)) - report "wrong ram coefficient at " & natural'image(addr) + report "wrong ram coefficient at " & natural'image(addr) & " " & to_hstring(data) severity error; - - -- address should jump c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_SIZE - -- on each iteration (wishbone bus is using byte-granularity) - addr := addr + c_WB_FOFB_PROCESSING_REGS_COEFFS_RAM_BANK_0_SIZE; end loop; end loop; - -- writing on setpoints ram via wishbone bus - report "writing on setpoints ram via wishbone bus" + -- writing on setpoints ram + report "writing on setpoints ram" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_ADDR; for i in 0 to (c_NUM_OF_SETPOINTS - 1) loop write32_pl(clk, wb_slave_i, wb_slave_o, addr, sp_ram.get_sp(i)); @@ -251,21 +267,22 @@ begin report "wrong ram setpoint at " & natural'image(addr) severity error; - -- address should jump c_WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_SIZE + -- address should jump c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_SIZE -- on each iteration (wishbone bus is using byte-granularity) - addr := addr + c_WB_FOFB_PROCESSING_REGS_SETPOINTS_RAM_BANK_SIZE; + addr := addr + c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_SIZE; end loop; - -- setting gains via wishbone bus - report "setting gains via wishbone bus" + -- setting gains + report "setting gains" severity note; read32_pl(clk, wb_slave_i, wb_slave_o, - c_WB_FOFB_PROCESSING_REGS_ACCS_GAINS_FIXED_POINT_POS_ADDR, data); + c_WB_FOFB_PROCESSING_REGS_FIXED_POINT_POS_ACCS_GAINS_ADDR, data); report "gains fixed-point position: " & to_hstring(data) severity note; - addr := c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_ADDR; + offs := c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_GAIN_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR; for i in 0 to (g_CHANNELS - 1) loop accs_gains_reader.read_accs_gain(real_gain_arr(i)); @@ -274,6 +291,8 @@ begin to_signed(integer(real_gain_arr(i) * 2.0**c_FOFB_GAIN_FRAC_WIDTH), c_FOFB_WB_GAIN_WIDTH), c_FOFB_WB_GAIN_WIDTH-c_FOFB_GAIN_WIDTH)); + addr := f_get_ch_reg_addr(offs, i); + write32_pl(clk, wb_slave_i, wb_slave_o, addr, wb_gain); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); @@ -281,30 +300,30 @@ begin report "wrong gain at " & natural'image(addr) severity error; - -- address should jump c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_1_ADDR - - -- c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_ADDR on each iteration - addr := addr + c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_1_ADDR - - c_WB_FOFB_PROCESSING_REGS_ACC_GAIN_0_ADDR; end loop; - -- setting saturation limits via wishbone bus - report "setting saturation limits via wishbone bus" + -- setting saturation limits + report "setting saturation limits" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_SP_MAX_0_ADDR; for i in 0 to (g_CHANNELS - 1) loop + offs := c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR; + addr := f_get_ch_reg_addr(offs, i); + -- writing maximum saturation value write32_pl(clk, wb_slave_i, wb_slave_o, addr, c_WB_SP_MAX); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); - addr := addr + c_WB_FOFB_PROCESSING_REGS_SP_MIN_0_ADDR - - c_WB_FOFB_PROCESSING_REGS_SP_MAX_0_ADDR; - assert (data = c_WB_SP_MAX) report "wrong saturation limit at " & natural'image(addr) severity error; + offs := c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR; + addr := f_get_ch_reg_addr(offs, i); + -- writing minimum saturation value write32_pl(clk, wb_slave_i, wb_slave_o, addr, c_WB_SP_MIN); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); @@ -312,9 +331,6 @@ begin assert (data = c_WB_SP_MIN) report "wrong saturation limit at " & natural'image(addr) severity error; - - addr := addr + c_WB_FOFB_PROCESSING_REGS_SP_MAX_1_ADDR - - c_WB_FOFB_PROCESSING_REGS_SP_MIN_0_ADDR; end loop; -- setting limit for loop interlock orbit distortion source via wishbone @@ -324,7 +340,7 @@ begin " bus" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_ORB_DISTORT_LIMIT_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT_ADDR; write32_pl(clk, wb_slave_i, wb_slave_o, addr, c_WB_ORB_DISTORT_LIMIT); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); @@ -337,10 +353,10 @@ begin -- bus report "setting minimum number of packets for loop interlock source via " & - " wishbone bus" + "wishbone bus" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_MIN_NUM_PKTS_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_ADDR; write32_pl(clk, wb_slave_i, wb_slave_o, addr, c_WB_MIN_NUM_PKTS); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); @@ -349,31 +365,31 @@ begin report "minimum number of packets was not set" severity error; - -- disabling loop interlock sources via wishbone bus - report "disabling loop interlock sources via wishbone bus" + -- disabling loop interlock sources + report "disabling loop interlock sources" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET) := + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET) := '0'; data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET) := + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET) := '0'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); assert (data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET) = + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET) = '0') report "loop interlock orbit distortion source was not disabled" severity error; assert (data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET) = + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET) = '0') report "loop interlock packet loss source was not disabled" severity error; @@ -474,22 +490,22 @@ begin end loop; end loop; - -- enabling loop interlock orbit distortion source via wishbone bus - report "enabling loop interlock orbit distortion source via wishbone bus" + -- enabling loop interlock orbit distortion source + report "enabling loop interlock orbit distortion source" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET) := + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET) := '1'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); assert (data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET) = + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET) = '1') report "loop interlock orbit distortion source was not enabled" severity error; @@ -596,9 +612,9 @@ begin end if; end loop; - -- checking loop interlock orbit distortion source state via wishbone bus + -- checking loop interlock orbit distortion source state report - "checking loop interlock orbit distortion source state via wishbone bus" + "checking loop interlock orbit distortion source state" severity note; addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ADDR; @@ -623,43 +639,43 @@ begin report "end of two extra fofb processing cycles" severity note; - -- disabling loop interlock orbit distortion source via wishbone bus - report "disabling loop interlock orbit distortion source via wishbone bus" + -- disabling loop interlock orbit distortion source + report "disabling loop interlock orbit distortion source" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET) := + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET) := '0'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); assert (data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ORB_DISTORT_EN_OFFSET) = + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_ORB_DISTORT_OFFSET) = '0') report "loop interlock orbit distortion source was not disabled" severity error; - -- clearing loop interlock state via wishbone bus - report "clearing loop interlock state via wishbone bus" + -- clearing loop interlock state + report "clearing loop interlock state" severity note; addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); - data(c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_CLR_OFFSET) := '1'; + data(c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_STA_CLR_OFFSET) := '1'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); -- NOTE: must wait 4 clk cycles for status register to update f_wait_cycles(clk, 4); - -- checking if loop interlock state was cleared via wishbone bus + -- checking if loop interlock state was cleared report - "checking if loop interlock state was cleared via wishbone bus" + "checking if loop interlock state was cleared" severity note; addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ADDR; @@ -671,22 +687,22 @@ begin severity error; expec_loop_intlk_state := false; - -- enabling loop interlock packet loss source via wishbone bus - report "enabling loop interlock packet loss source via wishbone bus" + -- enabling loop interlock packet loss source + report "enabling loop interlock packet loss source" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET) := + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET) := '1'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); assert (data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET) = + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET) = '1') report "loop interlock packet loss source was not enabled" severity error; @@ -790,9 +806,9 @@ begin end if; end loop; - -- checking loop interlock packet loss source state via wishbone bus + -- checking loop interlock packet loss source state report - "checking loop interlock packet loss source state via wishbone bus" + "checking loop interlock packet loss source state" severity note; addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ADDR; @@ -817,43 +833,43 @@ begin report "end of two extra fofb processing cycles" severity note; - -- disabling loop interlock packet loss source via wishbone bus - report "disabling loop interlock packet loss source via wishbone bus" + -- disabling loop interlock packet loss source + report "disabling loop interlock packet loss source" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET) := + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET) := '0'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); assert (data( - c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_SRC_EN_CTL_PACKET_LOSS_EN_OFFSET) = + c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_SRC_EN_PACKET_LOSS_OFFSET) = '0') report "loop interlock packet loss source was not disabled" severity error; - -- clearing loop interlock state via wishbone bus - report "clearing loop interlock state via wishbone bus" + -- clearing loop interlock state + report "clearing loop interlock state" severity note; addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_ADDR; read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); - data(c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_CLR_OFFSET) := '1'; + data(c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_CTL_STA_CLR_OFFSET) := '1'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); -- NOTE: must wait 4 clk cycles for status register to update f_wait_cycles(clk, 4); - -- checking if loop interlock state was cleared via wishbone bus + -- checking if loop interlock state was cleared report - "checking if loop interlock state was cleared via wishbone bus" + "checking if loop interlock state was cleared" severity note; addr := c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_STA_ADDR; @@ -865,23 +881,23 @@ begin severity error; expec_loop_intlk_state := false; - -- freezing accumulators via wishbone bus - report "freezing accumulators via wishbone bus" + -- freezing accumulators + report "freezing accumulators" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR; for i in 0 to (g_CHANNELS - 1) loop read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); - data(c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_FREEZE_OFFSET) := '1'; + data(c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_FREEZE_OFFSET) := '1'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); frozen_sp_arr(i) <= sp_arr(i); - -- address should jump c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_ADDR - - -- c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR on each iteration - addr := addr + c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_ADDR - - c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR; + -- address should jump c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_ADDR - + -- c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR on each iteration + addr := addr + c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR; end loop; -- ########## performing an extra fofb processing cycle ########## @@ -930,15 +946,15 @@ begin end loop; -- ########## end of: performing an extra fofb processing cycle ########## - -- clearing accumulators via wishbone bus - report "clearing accumulators via wishbone bus" + -- clearing accumulators + report "clearing accumulators" severity note; - addr := c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR; + addr := c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR; for i in 0 to (g_CHANNELS - 1) loop read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); - data(c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_CLEAR_OFFSET) := '1'; + data(c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_CLEAR_OFFSET) := '1'; write32_pl(clk, wb_slave_i, wb_slave_o, addr, data); valid_to_check <= sp_valid_arr(i); @@ -957,16 +973,19 @@ begin -- checking if autoclear is working read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); - assert (data(c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_CLEAR_OFFSET) = '0') + assert (data(c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_CLEAR_OFFSET) = '0') report "autoclear not working at " & natural'image(addr) severity error; - -- address should jump c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_ADDR - - -- c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR on each iteration - addr := addr + c_WB_FOFB_PROCESSING_REGS_ACC_CTL_1_ADDR - - c_WB_FOFB_PROCESSING_REGS_ACC_CTL_0_ADDR; + -- address should jump c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_ADDR - + -- c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR on each iteration + addr := addr + c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR; end loop; + report "success!" + severity note; + finish; end process; From a448f3c5bfde7f0084e53bb46fe9478e4b16d76c Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 15 Feb 2023 13:20:01 -0300 Subject: [PATCH 03/24] fofb_ctrl_pkg.vhd: update fofb processing regs sdb --- hdl/modules/fofb_ctrl_pkg.vhd | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index 895d761d..23cb2d2d 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -667,18 +667,18 @@ package fofb_ctrl_pkg is -- FOFB Processing constant c_xwb_fofb_processing_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device - abi_ver_major => x"02", + abi_ver_major => x"03", abi_ver_minor => x"00", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 32-bit port granularity (0100) sdb_component => ( addr_first => x"0000000000000000", - addr_last => x"0000000000007FFF", + addr_last => x"000000000000FFFF", product => ( vendor_id => x"1000000000001215", -- LNLS device_id => x"49681ca6", - version => x"00000001", - date => x"20220809", + version => x"00000002", + date => x"20230215", name => "FOFB_PROC_REGS "))); end fofb_ctrl_pkg; From 572155ea4894950ed209f4d03f8ed727b6f261be Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 24 Feb 2023 09:40:18 -0300 Subject: [PATCH 04/24] fofb_processing_channel_tb.vhd: increase cycles --- .../fofb_processing_channel/fofb_bpm_err.dat | 5120 +++++++++++++++++ .../fofb_processing_channel_tb.vhd | 4 +- 2 files changed, 5122 insertions(+), 2 deletions(-) diff --git a/hdl/testbench/fofb_processing_channel/fofb_bpm_err.dat b/hdl/testbench/fofb_processing_channel/fofb_bpm_err.dat index 7ee501e9..98d1975d 100644 --- a/hdl/testbench/fofb_processing_channel/fofb_bpm_err.dat +++ b/hdl/testbench/fofb_processing_channel/fofb_bpm_err.dat @@ -1278,3 +1278,5123 @@ 52 34 3879 +3512 +-3004 +503 +2220 +1393 +2608 +1746 +3212 +-3746 +-493 +-4076 +-1347 +2993 +356 +-3238 +-1142 +-179 +1203 +3772 +-2852 +-3266 +1555 +3278 +2564 +-133 +-2473 +3088 +3469 +3133 +-1450 +4017 +2897 +-1145 +170 +1141 +-3180 +-3263 +3098 +806 +1961 +533 +2883 +-280 +-2609 +-2052 +-1549 +179 +-1807 +4067 +3192 +3969 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fofb_processing_channel_tb is g_ACC_GAIN_MUL_PIPELINE_STAGES : natural := 2; -- Number of FOFB cycles to simulate - g_FOFB_NUM_CYC : natural := 4; + g_FOFB_NUM_CYC : natural := 20; -- Inverse response matrix coefficients file g_COEFF_RAM_FILE : string := "../coeff_norm_q31.dat"; @@ -116,7 +116,7 @@ architecture fofb_processing_channel_tb_arch of fofb_processing_channel_tb is constant c_COEFF_RAM_ADDR_WIDTH : natural := 9; constant c_COEFF_RAM_DATA_WIDTH : natural := 32; - constant c_LOOP_INTLK_CLK_CYCLES_DELAY : natural := 800; + constant c_LOOP_INTLK_CLK_CYCLES_DELAY : natural := 6000; signal clk : std_logic := '0'; signal rst_n : std_logic := '0'; signal busy : std_logic; From 5c247ddd2bb5bf021ef96640296ce750173a665e Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 24 Feb 2023 15:48:59 -0300 Subject: [PATCH 05/24] fofb_processing_channel: add setpoint decimation --- hdl/modules/fofb_processing/dot_prod_pkg.vhd | 12 ++++ .../fofb_processing/fofb_processing.vhd | 6 ++ .../fofb_processing_channel.vhd | 47 +++++++++++++++ .../fofb_processing_channel_tb.vhd | 57 +++++++++++++++++++ 4 files changed, 122 insertions(+) diff --git a/hdl/modules/fofb_processing/dot_prod_pkg.vhd b/hdl/modules/fofb_processing/dot_prod_pkg.vhd index 5431dc13..8ca19dd3 100644 --- a/hdl/modules/fofb_processing/dot_prod_pkg.vhd +++ b/hdl/modules/fofb_processing/dot_prod_pkg.vhd @@ -131,6 +131,9 @@ package dot_prod_pkg is -- Fractionary width for the set-point output g_SP_FRAC_WIDTH : natural := 0; + -- Maximum decimation ratio for the decimated setpoint output + g_SP_DECIM_MAX_RATIO : natural := 8191; + -- Extra bits for the dot product accumulator g_DOT_PROD_ACC_EXTRA_WIDTH : natural := 4; @@ -200,6 +203,15 @@ package dot_prod_pkg is -- is set to '1' and all arithmetic operations have finished sp_valid_o : out std_logic; + -- Setpoint decimation ratio + sp_decim_ratio_i : in integer range 0 to g_SP_DECIM_MAX_RATIO := 4600; + + -- Decimated setpoint + sp_decim_o : out signed(31 downto 0); + + -- Decimated setpoint valid + sp_decim_valid_o : out std_logic; + -- Loop interlock signal (has the same behavior as freeze_acc_i) loop_intlk_i : in std_logic ); diff --git a/hdl/modules/fofb_processing/fofb_processing.vhd b/hdl/modules/fofb_processing/fofb_processing.vhd index 05de4d60..df2e653a 100644 --- a/hdl/modules/fofb_processing/fofb_processing.vhd +++ b/hdl/modules/fofb_processing/fofb_processing.vhd @@ -152,6 +152,8 @@ architecture behave of fofb_processing is signal loop_intlk_state : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0) := (others => '0'); begin + -- TODO: properly connect g_SP_DECIM_MAX_RATIO, sp_decim_ratio_i, sp_decim_o and sp_decim_valid_o + gen_channels : for i in 0 to g_CHANNELS-1 generate fofb_processing_channel_interface : fofb_processing_channel generic map ( @@ -163,6 +165,7 @@ begin g_GAIN_FRAC_WIDTH => c_FOFB_GAIN_FRAC_WIDTH, g_SP_INT_WIDTH => c_FOFB_SP_INT_WIDTH, g_SP_FRAC_WIDTH => c_FOFB_SP_FRAC_WIDTH, + g_SP_DECIM_MAX_RATIO => 8191, g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, @@ -187,6 +190,9 @@ begin sp_min_i => sp_min_arr_i(i), sp_o => sp_arr_o(i), sp_valid_o => sp_valid_arr_o(i), + sp_decim_ratio_i => 4600, -- at Monit rate (but not synced) + sp_decim_o => open, + sp_decim_valid_o => open, loop_intlk_i => or loop_intlk_state ); end generate; diff --git a/hdl/modules/fofb_processing/fofb_processing_channel.vhd b/hdl/modules/fofb_processing/fofb_processing_channel.vhd index 044e823a..ee0bb17f 100644 --- a/hdl/modules/fofb_processing/fofb_processing_channel.vhd +++ b/hdl/modules/fofb_processing/fofb_processing_channel.vhd @@ -26,6 +26,7 @@ -- 2022-08-29 2.0 augusto.fraga Refactored using VHDL 2008, add -- accumulator gain -- 2022-10-26 2.1 guilherme.ricioli Added loop interlock interface +-- 2023-02-24 2.2 guilherme.ricioli Added setpoint decimation ------------------------------------------------------------------------------- library ieee; @@ -63,6 +64,9 @@ entity fofb_processing_channel is -- Fractionary width for the set-point output g_SP_FRAC_WIDTH : natural := 0; + -- Maximum decimation ratio for the decimated setpoint output + g_SP_DECIM_MAX_RATIO : natural := 8191; + -- Extra bits for the dot product accumulator g_DOT_PROD_ACC_EXTRA_WIDTH : natural := 4; @@ -132,12 +136,22 @@ entity fofb_processing_channel is -- is set to '1' and all arithmetic operations have finished sp_valid_o : out std_logic; + -- Setpoint decimation ratio + sp_decim_ratio_i : in integer range 0 to g_SP_DECIM_MAX_RATIO := 4600; + + -- Decimated setpoint + sp_decim_o : out signed(31 downto 0); + + -- Decimated setpoint valid + sp_decim_valid_o : out std_logic; + -- Loop interlock signal (has the same behavior as freeze_acc_i) loop_intlk_i : in std_logic ); end fofb_processing_channel; architecture behave of fofb_processing_channel is + type t_fofb_proc_state is (CALC_DOT_PROD, WAIT_DOT_PROD_FINISH); signal fofb_proc_state : t_fofb_proc_state; signal clear_acc_dot_prod : std_logic; @@ -164,6 +178,11 @@ architecture behave of fofb_processing_channel is signal bpm_pos_err_fp : sfixed(g_BPM_POS_INT_WIDTH downto -g_BPM_POS_FRAC_WIDTH); signal coeff_fp : sfixed(g_COEFF_INT_WIDTH downto -g_COEFF_FRAC_WIDTH); signal res_acc_sum_valid : std_logic; + signal sp_decim_ratio_d1 : integer range 0 to g_SP_DECIM_MAX_RATIO := 4600; + signal sp_decim_ratio_changed : boolean := false; + signal sp_filtered : signed(31 downto 0) := (others => '0'); + signal sp_filtered_samples : integer range 0 to g_SP_DECIM_MAX_RATIO + 1 := 0; + begin -- Cast bpm_pos_err_index_i to std_logic_vector (coefficient RAM address) @@ -187,6 +206,9 @@ begin -- Core is busy when it is not in the calculing the dot product state busy_o <= '0' when fofb_proc_state = CALC_DOT_PROD else '1'; + -- Checks if sp_decim_ratio_i changed + sp_decim_ratio_changed <= true when sp_decim_ratio_i /= sp_decim_ratio_d1 else false; + cmp_dot_prod: dot_prod generic map ( g_A_INT_WIDTH => g_COEFF_INT_WIDTH, @@ -223,6 +245,8 @@ begin res_acc_sum_valid <= '0'; res_mult_gain_pipe_valid <= (others => '0'); fofb_proc_state <= CALC_DOT_PROD; + sp_filtered <= (others => '0'); + sp_filtered_samples <= 0; else -- Delay 1 clock cycle to wait for the RAM data dot_prod_valid <= bpm_pos_err_valid_i; @@ -300,6 +324,29 @@ begin end if; sp_valid_o <= '1'; end if; + + sp_decim_valid_o <= '0'; + + -- Register sp_decim_ratio_i so to check if it changes + sp_decim_ratio_d1 <= sp_decim_ratio_i; + + if sp_decim_ratio_changed = true then + -- Resets decimation/filtering regs + sp_filtered <= (others => '0'); + sp_filtered_samples <= 0; + elsif sp_valid_o = '1' then + -- Computes the low-pass filtered setpoint + sp_filtered <= sp_filtered + sp_o; + sp_filtered_samples <= sp_filtered_samples + 1; + elsif sp_filtered_samples = sp_decim_ratio_i + 1 then + -- Decimates the low-pass filtered setpoint + sp_decim_o <= sp_filtered; + sp_decim_valid_o <= '1'; + + -- Resets decimation/filtering regs + sp_filtered <= (others => '0'); + sp_filtered_samples <= 0; + end if; end if; end if; end if; diff --git a/hdl/testbench/fofb_processing_channel/fofb_processing_channel_tb.vhd b/hdl/testbench/fofb_processing_channel/fofb_processing_channel_tb.vhd index 158fa4eb..9f4560db 100644 --- a/hdl/testbench/fofb_processing_channel/fofb_processing_channel_tb.vhd +++ b/hdl/testbench/fofb_processing_channel/fofb_processing_channel_tb.vhd @@ -14,6 +14,7 @@ -- Revisions : -- Date Version Author Description -- 2022-08-26 1.0 augusto.fraga Created +-- 2023-02-24 1.1 guilherme.ricioli Added setpoint decimation ------------------------------------------------------------------------------- library ieee; @@ -55,6 +56,9 @@ entity fofb_processing_channel_tb is -- Fractionary width for the set-point output g_SP_FRAC_WIDTH : natural := 0; + -- Maximum decimation ratio for the decimated setpoint output + g_SP_DECIM_MAX_RATIO : natural := 8191; + -- Extra bits for the dot product accumulator g_DOT_PROD_ACC_EXTRA_WIDTH : natural := 4; @@ -114,9 +118,21 @@ architecture fofb_processing_channel_tb_arch of fofb_processing_channel_tb is return to_signed(integer(gain * 2.0**g_GAIN_FRAC_WIDTH), gain_width); end function f_conv_gain; + impure function gen_rand_int(min, max : integer) return integer is + variable s1 : integer := 742030307; + variable s2 : integer := 656422083; + variable r : real; + begin + uniform(s1, s2, r); + return integer(r * real(max - min) + real(min)); + end function gen_rand_int; + constant c_COEFF_RAM_ADDR_WIDTH : natural := 9; constant c_COEFF_RAM_DATA_WIDTH : natural := 32; constant c_LOOP_INTLK_CLK_CYCLES_DELAY : natural := 6000; + constant c_FOFB_CYC_TO_CHANGE_SP_DECIM_RATIO : integer := gen_rand_int(1, g_FOFB_NUM_CYC); + constant c_BPM_READING_TO_CHANGE_SP_DECIM_RATIO : integer := gen_rand_int(0, 159); + signal clk : std_logic := '0'; signal rst_n : std_logic := '0'; signal busy : std_logic; @@ -134,6 +150,9 @@ architecture fofb_processing_channel_tb_arch of fofb_processing_channel_tb is signal sp_max : sp'subtype := to_signed(32767, sp'length); signal sp_min : sp'subtype := to_signed(-32768, sp'length); signal sp_valid : std_logic := '0'; + signal sp_decim_ratio : integer range 0 to g_SP_DECIM_MAX_RATIO := 3; + signal sp_decim : signed(31 downto 0); + signal sp_decim_valid : std_logic; signal loop_intlk : std_logic := '0'; shared variable coeff_ram : t_coeff_ram_data; begin @@ -148,6 +167,7 @@ begin g_GAIN_FRAC_WIDTH => g_GAIN_FRAC_WIDTH, g_SP_INT_WIDTH => g_SP_INT_WIDTH, g_SP_FRAC_WIDTH => g_SP_FRAC_WIDTH, + g_SP_DECIM_MAX_RATIO => g_SP_DECIM_MAX_RATIO, g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, @@ -172,6 +192,9 @@ begin sp_min_i => sp_min, sp_o => sp, sp_valid_o => sp_valid, + sp_decim_ratio_i => sp_decim_ratio, + sp_decim_o => sp_decim, + sp_decim_valid_o => sp_decim_valid, loop_intlk_i => loop_intlk ); @@ -185,6 +208,8 @@ begin variable dot_prod_acc_simu : real := 0.0; variable fofb_proc_acc_simu : real := 0.0; variable sp_err : real := 0.0; + variable sp_decim_simu : real := 0.0; + variable sp_decim_err : real := 0.0; begin -- Load the coefficients of the inverse response matrix for a single -- corrector @@ -216,6 +241,15 @@ begin f_send_bpm_err_pos_xy(clk, i, bpm_err_x_data, bpm_err_y_data, busy, bpm_pos_err, bpm_pos_err_index, bpm_pos_err_valid); dot_prod_acc_simu := dot_prod_acc_simu + real(bpm_err_x_data) * coeff_ram.get_coeff_real(i, g_COEFF_FRAC_WIDTH); dot_prod_acc_simu := dot_prod_acc_simu + real(bpm_err_y_data) * coeff_ram.get_coeff_real(i + 256, g_COEFF_FRAC_WIDTH); + + -- Changes setpoint decimation ratio + if fofb_cyc = c_FOFB_CYC_TO_CHANGE_SP_DECIM_RATIO and + i = c_BPM_READING_TO_CHANGE_SP_DECIM_RATIO then + sp_decim_ratio <= sp_decim_ratio + 1; + f_wait_cycles(clk, 1); + + sp_decim_simu := 0.0; + end if; else report "File " & g_FOFB_BPM_ERR_FILE & " ended prematurely!" severity error; end if; @@ -226,6 +260,9 @@ begin fofb_proc_acc_simu := fofb_proc_acc_simu + dot_prod_acc_simu * acc_gain_real; end if; + -- Computes the filtered setpoint + sp_decim_simu := sp_decim_simu + fofb_proc_acc_simu; + -- Time frame ended bpm_time_frame_end <= '1'; f_wait_cycles(clk, 1); @@ -251,6 +288,26 @@ begin report "Set point error: " & to_string(sp_err) & " OK!" severity note; end if; + -- Checks if a new decimated/filtered setpoint is ready + f_wait_clocked_signal(clk, sp_decim_valid, '1', 10); + + if sp_decim_valid = '1' then + -- This may be problematic for small values + sp_decim_err := abs((real(to_integer(sp_decim)) / floor(sp_decim_simu)) - 1.0); + + report "Decimated set point: " & to_string(to_integer(sp_decim)) severity note; + report "Decimated set point simulated: " & to_string(integer(floor(sp_decim_simu))) severity note; + + if sp_decim_err > 0.005 then + report "Decimated setpoint error: " & to_string(sp_decim_err) & " Too large!" severity error; + else + report "Decimated setpoint error: " & to_string(sp_decim_err) & " OK!" severity note; + end if; + + f_wait_cycles(clk, 1); + sp_decim_simu := 0.0; + end if; + acc_gain_real <= acc_gain_real + 0.5; end loop; From 010a044657d39b382af54aea9b37d9659fa0b52a Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 1 Mar 2023 15:40:14 -0300 Subject: [PATCH 06/24] fofb_processing_cosim.vhd: fix identation --- .../fofb_processing_cosim.vhd | 137 ++++++++---------- 1 file changed, 60 insertions(+), 77 deletions(-) diff --git a/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd b/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd index 31a0a5b3..a22e6a82 100644 --- a/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd +++ b/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd @@ -76,36 +76,28 @@ architecture rtl of fofb_processing_cosim is type t_word32_arr is array (natural range <>) of std_logic_vector(31 downto 0); -- Constants - constant c_FOFB_CHANNELS : integer := 1; + constant c_FOFB_CHANNELS : integer := 1; -- Signals - signal clk : std_logic := '0'; - signal rst_n : std_logic := '0'; - - signal busy : std_logic; - signal bpm_time_frame_end : std_logic := '0'; - - signal bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0) := (others => '0'); - signal bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal bpm_pos_valid : std_logic := '0'; - - signal coeff_ram_data_arr : t_arr_coeff_ram_data(c_FOFB_CHANNELS-1 downto 0); - signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(c_FOFB_CHANNELS-1 downto 0); - signal coeff_data_arr : t_word32_arr(511 downto 0) := (others => x"00000000"); - - signal sp_max : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(g_SP_MAX, c_FOFB_SP_WIDTH); - signal sp_min : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(g_SP_MIN, c_FOFB_SP_WIDTH); - - signal sp_arr : t_fofb_processing_sp_arr(c_FOFB_CHANNELS-1 downto 0); - signal sp_valid_arr : std_logic_vector(c_FOFB_CHANNELS-1 downto 0) := (others => '0'); - signal sp_data_arr : t_word32_arr(511 downto 0) := (others => x"00000000"); - - signal clear_acc_arr : std_logic_vector(c_FOFB_CHANNELS-1 downto 0) := (others => '0'); - - signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); - signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); - - signal gain_arr : t_fofb_processing_gain_arr(c_FOFB_CHANNELS-1 downto 0) := (others => (others => '0')); + signal clk : std_logic := '0'; + signal rst_n : std_logic := '0'; + signal busy : std_logic; + signal bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_valid : std_logic := '0'; + signal bpm_time_frame_end : std_logic := '0'; + signal coeff_ram_data_arr : t_arr_coeff_ram_data(c_FOFB_CHANNELS-1 downto 0); + signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(c_FOFB_CHANNELS-1 downto 0); + signal coeff_data_arr : t_word32_arr(511 downto 0) := (others => x"00000000"); + signal clear_acc_arr : std_logic_vector(c_FOFB_CHANNELS-1 downto 0) := (others => '0'); + signal sp_max : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(g_SP_MAX, c_FOFB_SP_WIDTH); + signal sp_min : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(g_SP_MIN, c_FOFB_SP_WIDTH); + signal sp_arr : t_fofb_processing_sp_arr(c_FOFB_CHANNELS-1 downto 0); + signal sp_valid_arr : std_logic_vector(c_FOFB_CHANNELS-1 downto 0) := (others => '0'); + signal sp_data_arr : t_word32_arr(511 downto 0) := (others => x"00000000"); + signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + signal gain_arr : t_fofb_processing_gain_arr(c_FOFB_CHANNELS-1 downto 0) := (others => (others => '0')); begin @@ -113,14 +105,14 @@ begin f_gen_clk(100_000_000, clk); process - variable fofb_server: t_fofb_server; - variable sp_o : integer := 0; - variable fofb_msg : t_fofb_server_msg_type; - variable connected : boolean := false; - variable end_simu : boolean := false; - variable data : std_logic_vector(31 downto 0); - variable data_sig : signed(31 downto 0); - variable data_int : integer; + variable fofb_server : t_fofb_server; + variable sp_o : integer := 0; + variable fofb_msg : t_fofb_server_msg_type; + variable connected : boolean := false; + variable end_simu : boolean := false; + variable data : std_logic_vector(31 downto 0); + variable data_sig : signed(31 downto 0); + variable data_int : integer; begin -- Create a new instance of fofb_server fofb_server := new_fofb_server(g_TCP_PORT, @@ -247,49 +239,40 @@ begin cmp_fofb_processing: fofb_processing generic map ( - g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, - g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, - g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, - g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, - g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, - g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, - g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, - g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, - g_CHANNELS => c_FOFB_CHANNELS + g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, + g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, + g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, + g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, + g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, + g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, + g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, + g_CHANNELS => c_FOFB_CHANNELS ) port map ( - clk_i => clk, - rst_n_i => rst_n, - - busy_o => busy, - - bpm_pos_i => bpm_pos, - bpm_pos_index_i => bpm_pos_index, - bpm_pos_valid_i => bpm_pos_valid, - bpm_time_frame_end_i => bpm_time_frame_end, - - coeff_ram_addr_arr_o => coeff_ram_addr_arr, - coeff_ram_data_arr_i => coeff_ram_data_arr, - - freeze_acc_arr_i => (others => '0'), - clear_acc_arr_i => clear_acc_arr, - - sp_pos_ram_addr_o => sp_pos_ram_addr, - sp_pos_ram_data_i => sp_pos_ram_data, - - gain_arr_i => gain_arr, - - sp_max_arr_i => (others => sp_max), - sp_min_arr_i => (others => sp_min), - - sp_arr_o => sp_arr, - sp_valid_arr_o => sp_valid_arr, - - loop_intlk_src_en_i => (others => '0'), - loop_intlk_state_clr_i => '0', - loop_intlk_state_o => open, - loop_intlk_distort_limit_i => (others => '0'), - loop_intlk_min_num_meas_i => (others => '0') + clk_i => clk, + rst_n_i => rst_n, + busy_o => busy, + bpm_pos_i => bpm_pos, + bpm_pos_index_i => bpm_pos_index, + bpm_pos_valid_i => bpm_pos_valid, + bpm_time_frame_end_i => bpm_time_frame_end, + coeff_ram_addr_arr_o => coeff_ram_addr_arr, + coeff_ram_data_arr_i => coeff_ram_data_arr, + freeze_acc_arr_i => (others => '0'), + clear_acc_arr_i => clear_acc_arr, + sp_pos_ram_addr_o => sp_pos_ram_addr, + sp_pos_ram_data_i => sp_pos_ram_data, + gain_arr_i => gain_arr, + sp_max_arr_i => (others => sp_max), + sp_min_arr_i => (others => sp_min), + sp_arr_o => sp_arr, + sp_valid_arr_o => sp_valid_arr, + loop_intlk_src_en_i => (others => '0'), + loop_intlk_state_clr_i => '0', + loop_intlk_state_o => open, + loop_intlk_distort_limit_i => (others => '0'), + loop_intlk_min_num_meas_i => (others => '0') ); end architecture rtl; From cfd908e67346ad1ea62c83428fec3ac584b66ca9 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 1 Mar 2023 15:57:56 -0300 Subject: [PATCH 07/24] fofb_processing_dcc_adapter_tb.vhd: fix identation --- .../fofb_processing_dcc_adapter_tb.vhd | 85 +++++++------------ 1 file changed, 33 insertions(+), 52 deletions(-) diff --git a/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd b/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd index e9544eaa..40a48d3e 100644 --- a/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd +++ b/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd @@ -65,28 +65,21 @@ architecture rtl of fofb_processing_dcc_adapter_tb is signal rst_n : std_logic := '0'; signal clk_dcc : std_logic := '0'; signal rst_dcc_n : std_logic := '0'; - signal dcc_time_frame_end : std_logic := '0'; signal dcc_packet : t_fofb_cc_packet; signal dcc_packet_valid : std_logic := '0'; - signal fofb_proc_busy : std_logic := '0'; signal fofb_proc_bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); signal fofb_proc_bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); signal fofb_proc_bpm_pos_valid : std_logic; signal fofb_proc_time_frame_end : std_logic; - signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(g_FOFB_CHANNELS-1 downto 0); signal coeff_ram_data_arr : t_arr_coeff_ram_data(g_FOFB_CHANNELS-1 downto 0) := (others => x"40000000"); - signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0) := x"00000000"; - signal gain_arr : t_fofb_processing_gain_arr(g_FOFB_CHANNELS-1 downto 0) := (others => x"1000"); - signal sp_arr : t_fofb_processing_sp_arr(g_FOFB_CHANNELS-1 downto 0); signal sp_valid_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0); - signal sp_max : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(32767, c_FOFB_SP_WIDTH); signal sp_min : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(-32768, c_FOFB_SP_WIDTH); @@ -141,50 +134,41 @@ begin cmp_fofb_processing: fofb_processing generic map ( - g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, - g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, - g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, - g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, - g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, - g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, - g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, - g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, - g_USE_MOVING_AVG => g_USE_MOVING_AVG, - g_CHANNELS => g_FOFB_CHANNELS + g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, + g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, + g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, + g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, + g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, + g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, + g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, + g_USE_MOVING_AVG => g_USE_MOVING_AVG, + g_CHANNELS => g_FOFB_CHANNELS ) port map ( - clk_i => clk, - rst_n_i => rst_n, - - busy_o => fofb_proc_busy, - - bpm_pos_i => fofb_proc_bpm_pos, - bpm_pos_index_i => fofb_proc_bpm_pos_index, - bpm_pos_valid_i => fofb_proc_bpm_pos_valid, - bpm_time_frame_end_i => fofb_proc_time_frame_end, - - coeff_ram_addr_arr_o => coeff_ram_addr_arr, - coeff_ram_data_arr_i => coeff_ram_data_arr, - - freeze_acc_arr_i => (others => '0'), - clear_acc_arr_i => (others => '0'), - - sp_pos_ram_addr_o => sp_pos_ram_addr, - sp_pos_ram_data_i => sp_pos_ram_data, - - gain_arr_i => gain_arr, - - sp_max_arr_i => (others => sp_max), - sp_min_arr_i => (others => sp_min), - - sp_arr_o => sp_arr, - sp_valid_arr_o => sp_valid_arr, - - loop_intlk_src_en_i => (others => '0'), - loop_intlk_state_clr_i => '0', - loop_intlk_state_o => open, - loop_intlk_distort_limit_i => (others => '0'), - loop_intlk_min_num_meas_i => (others => '0') + clk_i => clk, + rst_n_i => rst_n, + busy_o => fofb_proc_busy, + bpm_pos_i => fofb_proc_bpm_pos, + bpm_pos_index_i => fofb_proc_bpm_pos_index, + bpm_pos_valid_i => fofb_proc_bpm_pos_valid, + bpm_time_frame_end_i => fofb_proc_time_frame_end, + coeff_ram_addr_arr_o => coeff_ram_addr_arr, + coeff_ram_data_arr_i => coeff_ram_data_arr, + freeze_acc_arr_i => (others => '0'), + clear_acc_arr_i => (others => '0'), + sp_pos_ram_addr_o => sp_pos_ram_addr, + sp_pos_ram_data_i => sp_pos_ram_data, + gain_arr_i => gain_arr, + sp_max_arr_i => (others => sp_max), + sp_min_arr_i => (others => sp_min), + sp_arr_o => sp_arr, + sp_valid_arr_o => sp_valid_arr, + loop_intlk_src_en_i => (others => '0'), + loop_intlk_state_clr_i => '0', + loop_intlk_state_o => open, + loop_intlk_distort_limit_i => (others => '0'), + loop_intlk_min_num_meas_i => (others => '0') ); cmp_fofb_dcc_adapter: fofb_processing_dcc_adapter @@ -193,17 +177,14 @@ begin rst_n_i => rst_n, clk_dcc_i => clk_dcc, rst_dcc_n_i => rst_dcc_n, - dcc_time_frame_end_i => dcc_time_frame_end, dcc_packet_i => dcc_packet, dcc_packet_valid_i => dcc_packet_valid, - fofb_proc_busy_i => fofb_proc_busy, fofb_proc_bpm_pos_o => fofb_proc_bpm_pos, fofb_proc_bpm_pos_index_o => fofb_proc_bpm_pos_index, fofb_proc_bpm_pos_valid_o => fofb_proc_bpm_pos_valid, fofb_proc_time_frame_end_o => fofb_proc_time_frame_end, - acq_dcc_packet_o => open, acq_dcc_valid_o => open ); From 15164c463604bcbfd31d6ab8648cffcf8a3c1d95 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 1 Mar 2023 10:55:16 -0300 Subject: [PATCH 08/24] fofb_processing_tb.vhd: fix identation --- .../fofb_processing/fofb_processing_tb.vhd | 136 ++++++++---------- 1 file changed, 59 insertions(+), 77 deletions(-) diff --git a/hdl/testbench/fofb_processing/fofb_processing_tb.vhd b/hdl/testbench/fofb_processing/fofb_processing_tb.vhd index 6b8721ad..eabb13d0 100644 --- a/hdl/testbench/fofb_processing/fofb_processing_tb.vhd +++ b/hdl/testbench/fofb_processing/fofb_processing_tb.vhd @@ -86,46 +86,37 @@ end fofb_processing_tb; architecture behave of fofb_processing_tb is -- Constants - constant c_SYS_CLOCK_FREQ : natural := 100_000_000; + constant c_SYS_CLOCK_FREQ : natural := 100_000_000; constant c_LOOP_INTLK_DISTORT_LIMIT : natural := 20000; constant c_LOOP_INTLK_MIN_NUM_MEAS : natural := 10; -- Signals - signal clk : std_logic := '0'; - signal rst_n : std_logic := '0'; + signal clk : std_logic := '0'; + signal rst_n : std_logic := '0'; + signal busy : std_logic; + signal bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_valid : std_logic := '0'; + signal bpm_time_frame_end : std_logic := '0'; + signal coeff_ram_data_arr : t_arr_coeff_ram_data(g_FOFB_CHANNELS-1 downto 0); + signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(g_FOFB_CHANNELS-1 downto 0); + signal clear_acc_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0) := (others => '0'); + signal gain_arr : t_fofb_processing_gain_arr(g_FOFB_CHANNELS-1 downto 0); + signal sp_max : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(32767, c_FOFB_SP_WIDTH); + signal sp_min : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(-32768, c_FOFB_SP_WIDTH); + signal sp_arr : t_fofb_processing_sp_arr(g_FOFB_CHANNELS-1 downto 0); + signal sp_valid_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0) := (others => '0'); + signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + signal loop_intlk_src_en : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0) := (others => '0'); + signal loop_intlk_state_clr : std_logic := '0'; + signal loop_intlk_state : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); + signal loop_intlk_distort_limit : unsigned(g_BPM_POS_INT_WIDTH-1 downto 0) := (others => '0'); + signal loop_intlk_min_num_meas : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + shared variable coeff_ram : t_coeff_ram_data; + shared variable sp_ram : t_sp_ram_data; + signal fofb_proc_gains : real_vector(g_FOFB_CHANNELS-1 downto 0) := (others => 0.0); - signal busy : std_logic; - signal bpm_time_frame_end : std_logic := '0'; - - signal bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0) := (others => '0'); - signal bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal bpm_pos_valid : std_logic := '0'; - - signal coeff_ram_data_arr : t_arr_coeff_ram_data(g_FOFB_CHANNELS-1 downto 0); - signal coeff_ram_addr_arr : t_arr_coeff_ram_addr(g_FOFB_CHANNELS-1 downto 0); - - signal sp_max : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(32767, c_FOFB_SP_WIDTH); - signal sp_min : signed(c_FOFB_SP_WIDTH-1 downto 0) := to_signed(-32768, c_FOFB_SP_WIDTH); - - signal sp_arr : t_fofb_processing_sp_arr(g_FOFB_CHANNELS-1 downto 0); - signal sp_valid_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0) := (others => '0'); - signal clear_acc_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0) := (others => '0'); - - signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); - signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); - - signal gain_arr : t_fofb_processing_gain_arr(g_FOFB_CHANNELS-1 downto 0); - - shared variable coeff_ram : t_coeff_ram_data; - shared variable sp_ram : t_sp_ram_data; - - signal fofb_proc_gains : real_vector(g_FOFB_CHANNELS-1 downto 0) := (others => 0.0); - - signal loop_intlk_src_en : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0) := (others => '0'); - signal loop_intlk_state_clr : std_logic := '0'; - signal loop_intlk_state : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); - signal loop_intlk_distort_limit : unsigned(g_BPM_POS_INT_WIDTH-1 downto 0) := (others => '0'); - signal loop_intlk_min_num_meas : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); begin -- Generate clock signal f_gen_clk(c_SYS_CLOCK_FREQ, clk); @@ -529,50 +520,41 @@ begin cmp_fofb_processing: fofb_processing generic map ( - g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, - g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, - g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, - g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, - g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, - g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, - g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, - g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, - g_USE_MOVING_AVG => g_USE_MOVING_AVG, - g_CHANNELS => g_FOFB_CHANNELS + g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, + g_BPM_POS_INT_WIDTH => g_BPM_POS_INT_WIDTH, + g_BPM_POS_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, + g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, + g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, + g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, + g_ACC_GAIN_MUL_PIPELINE_STAGES => g_ACC_GAIN_MUL_PIPELINE_STAGES, + g_USE_MOVING_AVG => g_USE_MOVING_AVG, + g_CHANNELS => g_FOFB_CHANNELS ) port map ( - clk_i => clk, - rst_n_i => rst_n, - - busy_o => busy, - - bpm_pos_i => bpm_pos, - bpm_pos_index_i => bpm_pos_index, - bpm_pos_valid_i => bpm_pos_valid, - bpm_time_frame_end_i => bpm_time_frame_end, - - coeff_ram_addr_arr_o => coeff_ram_addr_arr, - coeff_ram_data_arr_i => coeff_ram_data_arr, - - freeze_acc_arr_i => (others => '0'), - clear_acc_arr_i => clear_acc_arr, - - sp_pos_ram_addr_o => sp_pos_ram_addr, - sp_pos_ram_data_i => sp_pos_ram_data, - - gain_arr_i => gain_arr, - - sp_max_arr_i => (others => sp_max), - sp_min_arr_i => (others => sp_min), - - sp_arr_o => sp_arr, - sp_valid_arr_o => sp_valid_arr, - - loop_intlk_src_en_i => loop_intlk_src_en, - loop_intlk_state_clr_i => loop_intlk_state_clr, - loop_intlk_state_o => loop_intlk_state, - loop_intlk_distort_limit_i => loop_intlk_distort_limit, - loop_intlk_min_num_meas_i => loop_intlk_min_num_meas + clk_i => clk, + rst_n_i => rst_n, + busy_o => busy, + bpm_pos_i => bpm_pos, + bpm_pos_index_i => bpm_pos_index, + bpm_pos_valid_i => bpm_pos_valid, + bpm_time_frame_end_i => bpm_time_frame_end, + coeff_ram_addr_arr_o => coeff_ram_addr_arr, + coeff_ram_data_arr_i => coeff_ram_data_arr, + freeze_acc_arr_i => (others => '0'), + clear_acc_arr_i => clear_acc_arr, + sp_pos_ram_addr_o => sp_pos_ram_addr, + sp_pos_ram_data_i => sp_pos_ram_data, + gain_arr_i => gain_arr, + sp_max_arr_i => (others => sp_max), + sp_min_arr_i => (others => sp_min), + sp_arr_o => sp_arr, + sp_valid_arr_o => sp_valid_arr, + loop_intlk_src_en_i => loop_intlk_src_en, + loop_intlk_state_clr_i => loop_intlk_state_clr, + loop_intlk_state_o => loop_intlk_state, + loop_intlk_distort_limit_i => loop_intlk_distort_limit, + loop_intlk_min_num_meas_i => loop_intlk_min_num_meas ); end architecture behave; From f4dca6f2633ca6754060343a3ce9734b0c175163 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 1 Mar 2023 11:03:22 -0300 Subject: [PATCH 09/24] fofb_processing_tb.vhd: increase cycles --- .../fofb_processing/fofb_bpm_pos.dat | 5120 +++++++++++++++++ .../fofb_processing/fofb_processing_tb.vhd | 2 +- 2 files changed, 5121 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a/hdl/testbench/fofb_processing/fofb_processing_tb.vhd +++ b/hdl/testbench/fofb_processing/fofb_processing_tb.vhd @@ -68,7 +68,7 @@ entity fofb_processing_tb is g_USE_MOVING_AVG : boolean := true; -- Number of FOFB cycles to simulate - g_FOFB_NUM_CYC : natural := 4; + g_FOFB_NUM_CYC : natural := 20; -- Inverse response matrix coefficients file g_COEFF_RAM_FILE : string := "../coeff_norm.dat"; From 30ff05f9969ddd81748915bb607a2704fae411eb Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 1 Mar 2023 10:38:12 -0300 Subject: [PATCH 10/24] fofb_processing: connect decimated setpoint signals --- hdl/modules/fofb_processing/dot_prod_pkg.vhd | 12 +++++ .../fofb_processing/fofb_processing.vhd | 21 ++++++--- .../fofb_processing/xwb_fofb_processing.vhd | 3 ++ .../fofb_processing/fofb_processing_tb.vhd | 44 ++++++++++++++++++- .../fofb_processing_cosim.vhd | 4 ++ .../fofb_processing_dcc_adapter_tb.vhd | 4 ++ 6 files changed, 81 insertions(+), 7 deletions(-) diff --git a/hdl/modules/fofb_processing/dot_prod_pkg.vhd b/hdl/modules/fofb_processing/dot_prod_pkg.vhd index 8ca19dd3..1f0f09a5 100644 --- a/hdl/modules/fofb_processing/dot_prod_pkg.vhd +++ b/hdl/modules/fofb_processing/dot_prod_pkg.vhd @@ -29,8 +29,11 @@ package dot_prod_pkg is constant c_FOFB_SP_FRAC_WIDTH : natural := 0; constant c_FOFB_SP_WIDTH : natural := c_FOFB_SP_INT_WIDTH + c_FOFB_SP_FRAC_WIDTH + 1; constant c_FOFB_WB_SP_MIN_MAX_WIDTH : natural := 32; + constant c_FOFB_SP_DECIM_MAX_RATIO : natural := 8191; type t_fofb_processing_sp_arr is array (natural range <>) of signed(c_FOFB_SP_WIDTH-1 downto 0); type t_fofb_processing_wb_sp_arr is array (natural range <>) of std_logic_vector(c_FOFB_WB_SP_MIN_MAX_WIDTH-1 downto 0); + type t_fofb_processing_sp_decim_arr is array (natural range <>) of signed(31 downto 0); + type t_fofb_processing_sp_decim_ratio_arr is array (natural range <>) of integer range 0 to c_FOFB_SP_DECIM_MAX_RATIO; constant c_FOFB_GAIN_INT_WIDTH : natural := 3; constant c_FOFB_GAIN_FRAC_WIDTH : natural := 12; @@ -305,6 +308,15 @@ package dot_prod_pkg is -- Set-point valid array (for each channel) sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + -- Setpoint decimation ratio (for each channel) + sp_decim_ratio_arr_i : in t_fofb_processing_sp_decim_ratio_arr(g_CHANNELS-1 downto 0); + + -- Decimated setpoint (for each channel) + sp_decim_arr_o : out t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0); + + -- Decimated setpoint valid (for each channel) + sp_decim_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + -- Loop interlock sources enable loop_intlk_src_en_i : in std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); diff --git a/hdl/modules/fofb_processing/fofb_processing.vhd b/hdl/modules/fofb_processing/fofb_processing.vhd index df2e653a..a54de433 100644 --- a/hdl/modules/fofb_processing/fofb_processing.vhd +++ b/hdl/modules/fofb_processing/fofb_processing.vhd @@ -22,6 +22,8 @@ -- mechanisms and orbit distortion -- loop interlocking -- 2022-11-04 2.2 guilherme.ricioli Add packet loss loop interlocking +-- 2023-03-01 2.3 guilherme.ricioli Connected decimated setpoint +-- signals ------------------------------------------------------------------------------- library ieee; @@ -119,6 +121,15 @@ entity fofb_processing is -- Set-point valid array (for each channel) sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + -- Setpoint decimation ratio (for each channel) + sp_decim_ratio_arr_i : in t_fofb_processing_sp_decim_ratio_arr(g_CHANNELS-1 downto 0); + + -- Decimated setpoint (for each channel) + sp_decim_arr_o : out t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0); + + -- Decimated setpoint valid (for each channel) + sp_decim_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + -- Loop interlock sources enable loop_intlk_src_en_i : in std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); @@ -152,8 +163,6 @@ architecture behave of fofb_processing is signal loop_intlk_state : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0) := (others => '0'); begin - -- TODO: properly connect g_SP_DECIM_MAX_RATIO, sp_decim_ratio_i, sp_decim_o and sp_decim_valid_o - gen_channels : for i in 0 to g_CHANNELS-1 generate fofb_processing_channel_interface : fofb_processing_channel generic map ( @@ -165,7 +174,7 @@ begin g_GAIN_FRAC_WIDTH => c_FOFB_GAIN_FRAC_WIDTH, g_SP_INT_WIDTH => c_FOFB_SP_INT_WIDTH, g_SP_FRAC_WIDTH => c_FOFB_SP_FRAC_WIDTH, - g_SP_DECIM_MAX_RATIO => 8191, + g_SP_DECIM_MAX_RATIO => c_FOFB_SP_DECIM_MAX_RATIO, g_DOT_PROD_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, g_DOT_PROD_MUL_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, g_DOT_PROD_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES, @@ -190,9 +199,9 @@ begin sp_min_i => sp_min_arr_i(i), sp_o => sp_arr_o(i), sp_valid_o => sp_valid_arr_o(i), - sp_decim_ratio_i => 4600, -- at Monit rate (but not synced) - sp_decim_o => open, - sp_decim_valid_o => open, + sp_decim_ratio_i => sp_decim_ratio_arr_i(i), + sp_decim_o => sp_decim_arr_o(i), + sp_decim_valid_o => sp_decim_valid_arr_o(i), loop_intlk_i => or loop_intlk_state ); end generate; diff --git a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd index 0f91154e..46acd33e 100644 --- a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd +++ b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd @@ -229,6 +229,9 @@ begin sp_min_arr_i => sp_min_arr, sp_arr_o => sp_arr_o, sp_valid_arr_o => sp_valid_arr_o, + sp_decim_ratio_arr_i => (others => 4600), -- at Monit rate (but not synced) + sp_decim_arr_o => open, + sp_decim_valid_arr_o => open, loop_intlk_src_en_i => loop_intlk_src_en, loop_intlk_state_clr_i => loop_intlk_ctl_sta_clr, loop_intlk_state_o => loop_intlk_sta, diff --git a/hdl/testbench/fofb_processing/fofb_processing_tb.vhd b/hdl/testbench/fofb_processing/fofb_processing_tb.vhd index 8c92672c..6b7b8e40 100644 --- a/hdl/testbench/fofb_processing/fofb_processing_tb.vhd +++ b/hdl/testbench/fofb_processing/fofb_processing_tb.vhd @@ -23,6 +23,8 @@ -- 2022-09-02 2.0 augusto.fraga Update the testbench to match the -- new fofb_processing version -- 2022-11-04 2.1 guilherme.ricioli Test loop interlock +-- 2023-03-01 2.2 guilherme.ricioli Connected decimated setpoint +-- signals ------------------------------------------------------------------------------- library ieee; @@ -108,6 +110,10 @@ architecture behave of fofb_processing_tb is signal sp_valid_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0) := (others => '0'); signal sp_pos_ram_addr : std_logic_vector(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); signal sp_pos_ram_data : std_logic_vector(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + signal sp_decim_ratio_arr : t_fofb_processing_sp_decim_ratio_arr(g_FOFB_CHANNELS-1 downto 0) := (others => 0); + signal sp_decim_arr : t_fofb_processing_sp_decim_arr(g_FOFB_CHANNELS-1 downto 0); + signal sp_decim_valid_arr : std_logic_vector(g_FOFB_CHANNELS-1 downto 0); + signal is_there_any_sp_decim_valid : std_logic := '0'; signal loop_intlk_src_en : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0) := (others => '0'); signal loop_intlk_state_clr : std_logic := '0'; signal loop_intlk_state : std_logic_vector(c_FOFB_LOOP_INTLK_TRIGS_WIDTH-1 downto 0); @@ -126,6 +132,12 @@ begin gain_arr(i) <= to_signed(integer(fofb_proc_gains(i) * 2.0**c_FOFB_GAIN_FRAC_WIDTH), c_FOFB_GAIN_WIDTH); end generate; + gen_ratios : for i in 0 to g_FOFB_CHANNELS-1 generate + sp_decim_ratio_arr(i) <= i; + end generate gen_ratios; + + is_there_any_sp_decim_valid <= or sp_decim_valid_arr; + -- Main simulation process process variable bpm_pos_reader : t_bpm_pos_reader; @@ -136,6 +148,8 @@ begin variable bpm_prev_x : integer_vector(2**c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => 0); variable bpm_prev_y : integer_vector(2**c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => 0); variable sp_err : real := 0.0; + variable sp_decim_arr_simu : real_vector(g_FOFB_CHANNELS-1 downto 0) := (others => 0.0); + variable sp_decim_err : real := 0.0; variable meas_cnt : natural := 0; variable loop_intlked : boolean := false; begin @@ -219,9 +233,12 @@ begin end loop; end loop; - -- Accumulate the simulated dot product result for i in 0 to g_FOFB_CHANNELS-1 loop + -- Accumulate the simulated dot product result fofb_proc_acc_simu(i) := fofb_proc_acc_simu(i) + dot_prod_acc_simu(i) * fofb_proc_gains(i); + + -- Computes the filtered setpoints + sp_decim_arr_simu(i) := sp_decim_arr_simu(i) + fofb_proc_acc_simu(i); end loop; -- Time frame ended @@ -250,6 +267,28 @@ begin report "Set point error: " & to_string(sp_err) & " OK!" severity note; end if; end loop; + + -- Checks if any new decimated/filtered setpoint is ready (if more than one, they happen at the same cycle) + f_wait_clocked_signal(clk, is_there_any_sp_decim_valid, '1', 10); + + for i in 0 to g_FOFB_CHANNELS-1 loop + if sp_decim_valid_arr(i) = '1' then + -- This may be problematic for small values + sp_decim_err := abs((real(to_integer(sp_decim_arr(i))) / floor(sp_decim_arr_simu(i))) - 1.0); + + report "Instance: " & to_string(i) severity note; + report "Decimated set point: " & to_string(to_integer(sp_decim_arr(i))) severity note; + report "Decimated set point simulated: " & to_string(integer(floor(sp_decim_arr_simu(i)))) severity note; + + if sp_decim_err > 0.005 then + report "Decimated setpoint error: " & to_string(sp_decim_err) & " Too large!" severity error; + else + report "Decimated setpoint error: " & to_string(sp_decim_err) & " OK!" severity note; + end if; + + sp_decim_arr_simu(i) := 0.0; + end if; + end loop; end loop; -- Enable loop interlock orbit distortion source @@ -550,6 +589,9 @@ begin sp_min_arr_i => (others => sp_min), sp_arr_o => sp_arr, sp_valid_arr_o => sp_valid_arr, + sp_decim_ratio_arr_i => sp_decim_ratio_arr, + sp_decim_arr_o => sp_decim_arr, + sp_decim_valid_arr_o => sp_decim_valid_arr, loop_intlk_src_en_i => loop_intlk_src_en, loop_intlk_state_clr_i => loop_intlk_state_clr, loop_intlk_state_o => loop_intlk_state, diff --git a/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd b/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd index a22e6a82..abfdf73a 100644 --- a/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd +++ b/hdl/testbench/fofb_processing_cosim/fofb_processing_cosim.vhd @@ -77,6 +77,7 @@ architecture rtl of fofb_processing_cosim is -- Constants constant c_FOFB_CHANNELS : integer := 1; + constant c_SP_DECIM_RATIO : integer := 4600; -- at Monit rate (but not synced) -- Signals signal clk : std_logic := '0'; @@ -268,6 +269,9 @@ begin sp_min_arr_i => (others => sp_min), sp_arr_o => sp_arr, sp_valid_arr_o => sp_valid_arr, + sp_decim_ratio_arr_i => (others => c_SP_DECIM_RATIO), + sp_decim_arr_o => open, + sp_decim_valid_arr_o => open, loop_intlk_src_en_i => (others => '0'), loop_intlk_state_clr_i => '0', loop_intlk_state_o => open, diff --git a/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd b/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd index 40a48d3e..ff8272ab 100644 --- a/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd +++ b/hdl/testbench/fofb_processing_dcc_adapter/fofb_processing_dcc_adapter_tb.vhd @@ -60,6 +60,7 @@ entity fofb_processing_dcc_adapter_tb is end fofb_processing_dcc_adapter_tb; architecture rtl of fofb_processing_dcc_adapter_tb is + constant c_SP_DECIM_RATIO : integer := 4600; -- at Monit rate (but not synced) signal clk : std_logic := '0'; signal rst_n : std_logic := '0'; @@ -164,6 +165,9 @@ begin sp_min_arr_i => (others => sp_min), sp_arr_o => sp_arr, sp_valid_arr_o => sp_valid_arr, + sp_decim_ratio_arr_i => (others => c_SP_DECIM_RATIO), + sp_decim_arr_o => open, + sp_decim_valid_arr_o => open, loop_intlk_src_en_i => (others => '0'), loop_intlk_state_clr_i => '0', loop_intlk_state_o => open, From ca5973191ed34317d72f594a7cec70faedff42bf Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 2 Mar 2023 09:01:03 -0300 Subject: [PATCH 11/24] fofb_processing/cheby/*: reduce acc regs block size There is no need for reserving an extra 14 regs address space. 8 is enough. --- .../cheby/wb_fofb_processing_regs.cheby | 2 +- .../cheby/wb_fofb_processing_regs.h | 16 +-- .../cheby/wb_fofb_processing_regs.vhd | 98 +++++++++---------- .../wb_fofb_processing_regs_consts_pkg.vhd | 96 +++++++++--------- 4 files changed, 106 insertions(+), 106 deletions(-) diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby index 9c3c2b5a..a84ba136 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby @@ -139,7 +139,7 @@ memory-map: - block: name: acc description: fofb processing accumulator registers (per channel) - size: 64 + size: 32 children: - reg: name: ctl diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h index b0d123a4..9f20151a 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h @@ -61,7 +61,7 @@ /* fofb processing accumulator registers (per channel) */ #define WB_FOFB_PROCESSING_REGS_CH_ACC 0x800UL -#define WB_FOFB_PROCESSING_REGS_CH_ACC_SIZE 64 /* 0x40 */ +#define WB_FOFB_PROCESSING_REGS_CH_ACC_SIZE 32 /* 0x20 */ /* fofb processing accumulator control register (per channel) */ #define WB_FOFB_PROCESSING_REGS_CH_ACC_CTL 0x800UL @@ -74,16 +74,16 @@ #define WB_FOFB_PROCESSING_REGS_CH_ACC_GAIN_VAL_SHIFT 0 /* fofb processing saturation limits registers (per channel) */ -#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS 0x840UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS 0x820UL #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_SIZE 8 /* 0x8 */ /* fofb processing maximum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX 0x840UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX 0x820UL #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX_VAL_MASK 0xffffffffUL #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MAX_VAL_SHIFT 0 /* fofb processing minimum saturation value register (per channel) */ -#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN 0x844UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN 0x824UL #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN_VAL_MASK 0xffffffffUL #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN_VAL_SHIFT 0 @@ -144,10 +144,10 @@ struct wb_fofb_processing_regs { uint32_t gain; /* padding to: 1 words */ - uint32_t __padding_0[14]; + uint32_t __padding_0[6]; } acc; - /* [0x840]: BLOCK fofb processing saturation limits registers (per channel) */ + /* [0x820]: BLOCK fofb processing saturation limits registers (per channel) */ struct sp_limits { /* [0x0]: REG (rw) fofb processing maximum saturation value register (per channel) */ uint32_t max; @@ -156,8 +156,8 @@ struct wb_fofb_processing_regs { uint32_t min; } sp_limits; - /* padding to: 528 words */ - uint32_t __padding_0[494]; + /* padding to: 520 words */ + uint32_t __padding_0[502]; } ch[12]; }; diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd index 720f4942..62528719 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd @@ -1,4 +1,4 @@ --- Do not edit. Generated on Tue Feb 14 18:19:12 2023 by guilherme.ricioli +-- Do not edit. Generated on Thu Mar 02 09:08:53 2023 by guilherme.ricioli -- With Cheby 1.4.0 and these options: -- -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd @@ -2308,11 +2308,11 @@ begin -- Reg ch_0_acc_gain ch_0_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_0_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_0_sp_limits_max ch_0_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_0_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_0_sp_limits_min ch_0_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_0_sp_limits_min_wack; @@ -2333,11 +2333,11 @@ begin -- Reg ch_1_acc_gain ch_1_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_1_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_1_sp_limits_max ch_1_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_1_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_1_sp_limits_min ch_1_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_1_sp_limits_min_wack; @@ -2358,11 +2358,11 @@ begin -- Reg ch_2_acc_gain ch_2_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_2_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_2_sp_limits_max ch_2_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_2_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_2_sp_limits_min ch_2_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_2_sp_limits_min_wack; @@ -2383,11 +2383,11 @@ begin -- Reg ch_3_acc_gain ch_3_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_3_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_3_sp_limits_max ch_3_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_3_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_3_sp_limits_min ch_3_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_3_sp_limits_min_wack; @@ -2408,11 +2408,11 @@ begin -- Reg ch_4_acc_gain ch_4_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_4_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_4_sp_limits_max ch_4_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_4_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_4_sp_limits_min ch_4_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_4_sp_limits_min_wack; @@ -2433,11 +2433,11 @@ begin -- Reg ch_5_acc_gain ch_5_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_5_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_5_sp_limits_max ch_5_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_5_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_5_sp_limits_min ch_5_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_5_sp_limits_min_wack; @@ -2458,11 +2458,11 @@ begin -- Reg ch_6_acc_gain ch_6_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_6_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_6_sp_limits_max ch_6_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_6_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_6_sp_limits_min ch_6_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_6_sp_limits_min_wack; @@ -2483,11 +2483,11 @@ begin -- Reg ch_7_acc_gain ch_7_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_7_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_7_sp_limits_max ch_7_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_7_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_7_sp_limits_min ch_7_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_7_sp_limits_min_wack; @@ -2508,11 +2508,11 @@ begin -- Reg ch_8_acc_gain ch_8_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_8_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_8_sp_limits_max ch_8_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_8_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_8_sp_limits_min ch_8_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_8_sp_limits_min_wack; @@ -2533,11 +2533,11 @@ begin -- Reg ch_9_acc_gain ch_9_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_9_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_9_sp_limits_max ch_9_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_9_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_9_sp_limits_min ch_9_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_9_sp_limits_min_wack; @@ -2558,11 +2558,11 @@ begin -- Reg ch_10_acc_gain ch_10_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_10_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_10_sp_limits_max ch_10_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_10_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_10_sp_limits_min ch_10_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_10_sp_limits_min_wack; @@ -2583,11 +2583,11 @@ begin -- Reg ch_11_acc_gain ch_11_acc_gain_wreq <= wr_req_d0; wr_ack_int <= ch_11_acc_gain_wack; - when "000010000" => + when "000001000" => -- Reg ch_11_sp_limits_max ch_11_sp_limits_max_wreq <= wr_req_d0; wr_ack_int <= ch_11_sp_limits_max_wack; - when "000010001" => + when "000001001" => -- Reg ch_11_sp_limits_min ch_11_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_11_sp_limits_min_wack; @@ -2673,11 +2673,11 @@ begin -- Reg ch_0_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_0_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_0_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_0_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_0_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_0_sp_limits_min_val_reg; @@ -2701,11 +2701,11 @@ begin -- Reg ch_1_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_1_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_1_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_1_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_1_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_1_sp_limits_min_val_reg; @@ -2729,11 +2729,11 @@ begin -- Reg ch_2_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_2_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_2_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_2_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_2_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_2_sp_limits_min_val_reg; @@ -2757,11 +2757,11 @@ begin -- Reg ch_3_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_3_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_3_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_3_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_3_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_3_sp_limits_min_val_reg; @@ -2785,11 +2785,11 @@ begin -- Reg ch_4_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_4_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_4_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_4_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_4_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_4_sp_limits_min_val_reg; @@ -2813,11 +2813,11 @@ begin -- Reg ch_5_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_5_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_5_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_5_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_5_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_5_sp_limits_min_val_reg; @@ -2841,11 +2841,11 @@ begin -- Reg ch_6_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_6_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_6_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_6_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_6_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_6_sp_limits_min_val_reg; @@ -2869,11 +2869,11 @@ begin -- Reg ch_7_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_7_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_7_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_7_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_7_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_7_sp_limits_min_val_reg; @@ -2897,11 +2897,11 @@ begin -- Reg ch_8_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_8_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_8_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_8_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_8_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_8_sp_limits_min_val_reg; @@ -2925,11 +2925,11 @@ begin -- Reg ch_9_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_9_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_9_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_9_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_9_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_9_sp_limits_min_val_reg; @@ -2953,11 +2953,11 @@ begin -- Reg ch_10_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_10_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_10_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_10_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_10_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_10_sp_limits_min_val_reg; @@ -2981,11 +2981,11 @@ begin -- Reg ch_11_acc_gain rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_11_acc_gain_val_reg; - when "000010000" => + when "000001000" => -- Reg ch_11_sp_limits_max rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_11_sp_limits_max_val_reg; - when "000010001" => + when "000001001" => -- Reg ch_11_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_11_sp_limits_min_val_reg; diff --git a/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd index 2a99603e..f653a216 100644 --- a/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd @@ -30,17 +30,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_0_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_ADDR : Natural := 16#1800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_ADDR : Natural := 16#1800#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_GAIN_ADDR : Natural := 16#1804#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_ADDR : Natural := 16#1840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_ADDR : Natural := 16#1820#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_ADDR : Natural := 16#1840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_ADDR : Natural := 16#1820#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_ADDR : Natural := 16#1844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_ADDR : Natural := 16#1824#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ADDR : Natural := 16#2000#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SIZE : Natural := 4096; @@ -48,17 +48,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_1_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_1_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_ADDR : Natural := 16#2800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_ADDR : Natural := 16#2800#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_GAIN_ADDR : Natural := 16#2804#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_ADDR : Natural := 16#2840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_ADDR : Natural := 16#2820#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MAX_ADDR : Natural := 16#2840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MAX_ADDR : Natural := 16#2820#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_ADDR : Natural := 16#2844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_ADDR : Natural := 16#2824#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ADDR : Natural := 16#3000#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SIZE : Natural := 4096; @@ -66,17 +66,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_2_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_2_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_ADDR : Natural := 16#3800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_CTL_ADDR : Natural := 16#3800#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_GAIN_ADDR : Natural := 16#3804#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_ADDR : Natural := 16#3840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_ADDR : Natural := 16#3820#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MAX_ADDR : Natural := 16#3840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MAX_ADDR : Natural := 16#3820#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_ADDR : Natural := 16#3844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_ADDR : Natural := 16#3824#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ADDR : Natural := 16#4000#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SIZE : Natural := 4096; @@ -84,17 +84,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_3_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_3_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_ADDR : Natural := 16#4800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_CTL_ADDR : Natural := 16#4800#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_GAIN_ADDR : Natural := 16#4804#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_ADDR : Natural := 16#4840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_ADDR : Natural := 16#4820#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MAX_ADDR : Natural := 16#4840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MAX_ADDR : Natural := 16#4820#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_ADDR : Natural := 16#4844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_ADDR : Natural := 16#4824#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ADDR : Natural := 16#5000#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SIZE : Natural := 4096; @@ -102,17 +102,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_4_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_4_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_ADDR : Natural := 16#5800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_CTL_ADDR : Natural := 16#5800#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_GAIN_ADDR : Natural := 16#5804#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_ADDR : Natural := 16#5840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_ADDR : Natural := 16#5820#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MAX_ADDR : Natural := 16#5840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MAX_ADDR : Natural := 16#5820#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_ADDR : Natural := 16#5844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_ADDR : Natural := 16#5824#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ADDR : Natural := 16#6000#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SIZE : Natural := 4096; @@ -120,17 +120,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_5_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_5_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_ADDR : Natural := 16#6800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_CTL_ADDR : Natural := 16#6800#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_GAIN_ADDR : Natural := 16#6804#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_ADDR : Natural := 16#6840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_ADDR : Natural := 16#6820#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MAX_ADDR : Natural := 16#6840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MAX_ADDR : Natural := 16#6820#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_ADDR : Natural := 16#6844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_ADDR : Natural := 16#6824#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ADDR : Natural := 16#7000#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SIZE : Natural := 4096; @@ -138,17 +138,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_6_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_6_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_ADDR : Natural := 16#7800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_CTL_ADDR : Natural := 16#7800#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_GAIN_ADDR : Natural := 16#7804#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_ADDR : Natural := 16#7840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_ADDR : Natural := 16#7820#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MAX_ADDR : Natural := 16#7840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MAX_ADDR : Natural := 16#7820#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_ADDR : Natural := 16#7844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_ADDR : Natural := 16#7824#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ADDR : Natural := 16#8000#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SIZE : Natural := 4096; @@ -156,17 +156,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_7_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_7_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_ADDR : Natural := 16#8800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_CTL_ADDR : Natural := 16#8800#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_GAIN_ADDR : Natural := 16#8804#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_ADDR : Natural := 16#8840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_ADDR : Natural := 16#8820#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MAX_ADDR : Natural := 16#8840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MAX_ADDR : Natural := 16#8820#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_ADDR : Natural := 16#8844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_ADDR : Natural := 16#8824#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ADDR : Natural := 16#9000#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SIZE : Natural := 4096; @@ -174,17 +174,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_8_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_8_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_ADDR : Natural := 16#9800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_CTL_ADDR : Natural := 16#9800#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_GAIN_ADDR : Natural := 16#9804#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_ADDR : Natural := 16#9840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_ADDR : Natural := 16#9820#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MAX_ADDR : Natural := 16#9840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MAX_ADDR : Natural := 16#9820#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_ADDR : Natural := 16#9844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_ADDR : Natural := 16#9824#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ADDR : Natural := 16#a000#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SIZE : Natural := 4096; @@ -192,17 +192,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_9_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_9_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_ADDR : Natural := 16#a800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_CTL_ADDR : Natural := 16#a800#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_GAIN_ADDR : Natural := 16#a804#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_ADDR : Natural := 16#a840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_ADDR : Natural := 16#a820#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MAX_ADDR : Natural := 16#a840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MAX_ADDR : Natural := 16#a820#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_ADDR : Natural := 16#a844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_ADDR : Natural := 16#a824#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ADDR : Natural := 16#b000#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SIZE : Natural := 4096; @@ -210,17 +210,17 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_10_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_10_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_ADDR : Natural := 16#b800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_CTL_ADDR : Natural := 16#b800#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_GAIN_ADDR : Natural := 16#b804#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_ADDR : Natural := 16#b840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_ADDR : Natural := 16#b820#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MAX_ADDR : Natural := 16#b840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MAX_ADDR : Natural := 16#b820#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_ADDR : Natural := 16#b844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_ADDR : Natural := 16#b824#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ADDR : Natural := 16#c000#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SIZE : Natural := 4096; @@ -228,16 +228,16 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_11_COEFF_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_CH_11_COEFF_RAM_BANK_DATA_ADDR : Natural := 16#0#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_ADDR : Natural := 16#c800#; - constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_SIZE : Natural := 64; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_SIZE : Natural := 32; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_CTL_ADDR : Natural := 16#c800#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_CTL_CLEAR_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_CTL_FREEZE_OFFSET : Natural := 1; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_GAIN_ADDR : Natural := 16#c804#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ACC_GAIN_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_ADDR : Natural := 16#c840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_ADDR : Natural := 16#c820#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_SIZE : Natural := 8; - constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MAX_ADDR : Natural := 16#c840#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MAX_ADDR : Natural := 16#c820#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; - constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_ADDR : Natural := 16#c844#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_ADDR : Natural := 16#c824#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; end package wb_fofb_processing_regs_consts_pkg; From 499d09a1984fda287ec71a6e483ec5877a37d9d9 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 2 Mar 2023 14:11:01 -0300 Subject: [PATCH 12/24] xwb_fofb_processing_tb.vhd: increase cycles --- .../xwb_fofb_processing/fofb_bpm_pos.dat | 5120 +++++++++++++++++ .../xwb_fofb_processing_tb.vhd | 2 +- 2 files changed, 5121 insertions(+), 1 deletion(-) diff --git a/hdl/testbench/xwb_fofb_processing/fofb_bpm_pos.dat b/hdl/testbench/xwb_fofb_processing/fofb_bpm_pos.dat index 55d0ea8d..aa06c83a 100644 --- a/hdl/testbench/xwb_fofb_processing/fofb_bpm_pos.dat +++ b/hdl/testbench/xwb_fofb_processing/fofb_bpm_pos.dat @@ -1278,3 +1278,5123 @@ -49119 -18123 -52379 +92212 +143509 +29905 +100472 +313753 +-92315 +111222 +62338 +129386 +136233 +-11182 +-74941 +-37252 +49679 +-56551 +-46384 +102870 +84985 +-132831 +-35710 +-94870 +-75058 +-279529 +34205 +-9235 +77359 +97035 +-67981 +198640 +52870 +78842 +-90413 +87117 +70008 +-390589 +-482232 +-20277 +-49037 +-84950 +27435 +-45155 +82576 +133942 +30563 +45280 +11981 +6165 +125714 +60608 +25122 +-6408 +-156109 +143511 +47367 +-118974 +-96636 +52158 +-16852 +-33186 +-92252 +-37245 +-108948 +-95876 +-317478 +-6693 +-13300 +8137 +24518 +150125 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a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd index 86476dce..f76fcff6 100644 --- a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd +++ b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd @@ -71,7 +71,7 @@ entity xwb_fofb_processing_tb is g_ACC_GAIN_MUL_PIPELINE_STAGES : natural := 2; -- number of fofb cycles to simulate - g_FOFB_NUM_CYC : natural := 4; + g_FOFB_NUM_CYC : natural := 20; -- fofb processing saturation maximum value g_SP_MAX : integer := 15200; From 2629615c5a75c2167c63ea9a97c3317aec7d6a57 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 2 Mar 2023 10:29:35 -0300 Subject: [PATCH 13/24] xwb_fofb_processing: expose setpoint decimation regs --- hdl/modules/fofb_ctrl_pkg.vhd | 6 + .../cheby/wb_fofb_processing_regs.cheby | 42 ++ .../cheby/wb_fofb_processing_regs.h | 43 +- .../cheby/wb_fofb_processing_regs.vhd | 621 +++++++++++++++++- hdl/modules/fofb_processing/dot_prod_pkg.vhd | 2 + .../fofb_processing/fofb_processing.vhd | 1 + .../fofb_processing_channel.vhd | 1 + .../fofb_processing/xwb_fofb_processing.vhd | 59 +- .../wb_fofb_processing_regs_consts_pkg.vhd | 74 +++ .../xwb_fofb_processing_tb.vhd | 93 +++ .../afc_ref_fofb_ctrl_gen.vhd | 2 + 11 files changed, 933 insertions(+), 11 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index 23cb2d2d..a0331be2 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -580,6 +580,12 @@ package fofb_ctrl_pkg is -- Set-point valid array (for each channel) sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + -- Decimated setpoint (for each channel) + sp_decim_arr_o : out t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0); + + -- Decimated setpoint valid (for each channel) + sp_decim_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + dcc_p2p_en_o : out std_logic; --------------------------------------------------------------------------- diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby index a84ba136..0478962d 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby @@ -111,6 +111,16 @@ memory-map: name: val range: 31-0 description: value + - reg: + name: sp_decim_ratio_max + width: 32 + access: ro + description: fofb processing maximum setpoint decimation ratio constant + children: + - field: + name: cte + range: 31-0 + description: value - memory: name: sps_ram_bank memsize: 2k @@ -198,3 +208,35 @@ memory-map: name: val range: 31-0 description: value + - block: + name: sp_decim + description: fofb processing setpoints decimation registers (per channel) + align: False + children: + - reg: + name: data + width: 32 + access: ro + description: fofb processing decimated setpoint value register (per channel) + children: + - field: + name: val + range: 31-0 + description: value + - reg: + name: ratio + width: 32 + access: rw + description: | + fofb processing setpoint decimation ratio register (per channel) + NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + lowest ceil(log2(sp_decim_ratio_max)) bits + children: + - field: + name: val + range: 31-0 + description: value + comment : | + 0: decimation at each new sample + 1: decimation at each 2 samples + and so on diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h index 9f20151a..b549ae89 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h @@ -41,6 +41,11 @@ #define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_VAL_MASK 0xffffffffUL #define WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_VAL_SHIFT 0 +/* fofb processing maximum setpoint decimation ratio constant */ +#define WB_FOFB_PROCESSING_REGS_SP_DECIM_RATIO_MAX 0x80UL +#define WB_FOFB_PROCESSING_REGS_SP_DECIM_RATIO_MAX_CTE_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_SP_DECIM_RATIO_MAX_CTE_SHIFT 0 + /* fofb processing setpoints ram bank */ #define WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK 0x800UL #define WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_SIZE 4 /* 0x4 */ @@ -87,6 +92,23 @@ #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN_VAL_MASK 0xffffffffUL #define WB_FOFB_PROCESSING_REGS_CH_SP_LIMITS_MIN_VAL_SHIFT 0 +/* fofb processing setpoints decimation registers (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM 0x828UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_SIZE 8 /* 0x8 */ + +/* fofb processing decimated setpoint value register (per channel) */ +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_DATA 0x828UL +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_DATA_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_DATA_VAL_SHIFT 0 + +/* fofb processing setpoint decimation ratio register (per channel) +NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + lowest ceil(log2(sp_decim_ratio_max)) bits + */ +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_RATIO 0x82cUL +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_RATIO_VAL_MASK 0xffffffffUL +#define WB_FOFB_PROCESSING_REGS_CH_SP_DECIM_RATIO_VAL_SHIFT 0 + struct wb_fofb_processing_regs { /* [0x0]: BLOCK fofb processing fixed-point position constants */ struct fixed_point_pos { @@ -118,8 +140,11 @@ struct wb_fofb_processing_regs { uint32_t __padding_0[12]; } loop_intlk; + /* [0x80]: REG (ro) fofb processing maximum setpoint decimation ratio constant */ + uint32_t sp_decim_ratio_max; + /* padding to: 512 words */ - uint32_t __padding_0[480]; + uint32_t __padding_0[479]; /* [0x800]: MEMORY fofb processing setpoints ram bank */ struct sps_ram_bank { @@ -156,8 +181,20 @@ struct wb_fofb_processing_regs { uint32_t min; } sp_limits; - /* padding to: 520 words */ - uint32_t __padding_0[502]; + /* [0x828]: BLOCK fofb processing setpoints decimation registers (per channel) */ + struct sp_decim { + /* [0x0]: REG (ro) fofb processing decimated setpoint value register (per channel) */ + uint32_t data; + + /* [0x4]: REG (rw) fofb processing setpoint decimation ratio register (per channel) +NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + lowest ceil(log2(sp_decim_ratio_max)) bits + */ + uint32_t ratio; + } sp_decim; + + /* padding to: 522 words */ + uint32_t __padding_0[500]; } ch[12]; }; diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd index 62528719..1ed529b4 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd @@ -1,4 +1,4 @@ --- Do not edit. Generated on Thu Mar 02 09:08:53 2023 by guilherme.ricioli +-- Do not edit. Generated on Mon Mar 06 16:30:00 2023 by guilherme.ricioli -- With Cheby 1.4.0 and these options: -- -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd @@ -51,6 +51,10 @@ entity wb_fofb_processing_regs is -- value loop_intlk_min_num_pkts_val_o : out std_logic_vector(31 downto 0); + -- fofb processing maximum setpoint decimation ratio constant + -- value + sp_decim_ratio_max_cte_i : in std_logic_vector(31 downto 0); + -- RAM port for sps_ram_bank sps_ram_bank_adr_i : in std_logic_vector(8 downto 0); sps_ram_bank_data_rd_i : in std_logic; @@ -81,6 +85,19 @@ entity wb_fofb_processing_regs is -- value ch_0_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_0_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_0_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_1_coeff_ram_bank ch_1_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_1_coeff_ram_bank_data_rd_i : in std_logic; @@ -106,6 +123,19 @@ entity wb_fofb_processing_regs is -- value ch_1_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_1_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_1_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_2_coeff_ram_bank ch_2_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_2_coeff_ram_bank_data_rd_i : in std_logic; @@ -131,6 +161,19 @@ entity wb_fofb_processing_regs is -- value ch_2_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_2_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_2_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_3_coeff_ram_bank ch_3_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_3_coeff_ram_bank_data_rd_i : in std_logic; @@ -156,6 +199,19 @@ entity wb_fofb_processing_regs is -- value ch_3_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_3_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_3_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_4_coeff_ram_bank ch_4_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_4_coeff_ram_bank_data_rd_i : in std_logic; @@ -181,6 +237,19 @@ entity wb_fofb_processing_regs is -- value ch_4_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_4_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_4_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_5_coeff_ram_bank ch_5_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_5_coeff_ram_bank_data_rd_i : in std_logic; @@ -206,6 +275,19 @@ entity wb_fofb_processing_regs is -- value ch_5_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_5_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_5_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_6_coeff_ram_bank ch_6_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_6_coeff_ram_bank_data_rd_i : in std_logic; @@ -231,6 +313,19 @@ entity wb_fofb_processing_regs is -- value ch_6_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_6_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_6_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_7_coeff_ram_bank ch_7_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_7_coeff_ram_bank_data_rd_i : in std_logic; @@ -256,6 +351,19 @@ entity wb_fofb_processing_regs is -- value ch_7_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_7_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_7_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_8_coeff_ram_bank ch_8_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_8_coeff_ram_bank_data_rd_i : in std_logic; @@ -281,6 +389,19 @@ entity wb_fofb_processing_regs is -- value ch_8_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_8_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_8_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_9_coeff_ram_bank ch_9_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_9_coeff_ram_bank_data_rd_i : in std_logic; @@ -306,6 +427,19 @@ entity wb_fofb_processing_regs is -- value ch_9_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_9_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_9_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_10_coeff_ram_bank ch_10_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_10_coeff_ram_bank_data_rd_i : in std_logic; @@ -331,6 +465,19 @@ entity wb_fofb_processing_regs is -- value ch_10_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_10_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_10_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0); + -- RAM port for ch_11_coeff_ram_bank ch_11_coeff_ram_bank_adr_i : in std_logic_vector(8 downto 0); ch_11_coeff_ram_bank_data_rd_i : in std_logic; @@ -354,7 +501,20 @@ entity wb_fofb_processing_regs is -- fofb processing minimum saturation value register (per channel) -- value - ch_11_sp_limits_min_val_o : out std_logic_vector(31 downto 0) + ch_11_sp_limits_min_val_o : out std_logic_vector(31 downto 0); + + -- fofb processing decimated setpoint value register (per channel) + -- value + ch_11_sp_decim_data_val_i : in std_logic_vector(31 downto 0); + + -- fofb processing setpoint decimation ratio register (per channel) + -- NOTE: if this value is higher than sp_decim_ratio_max, gw will truncate the + -- lowest ceil(log2(sp_decim_ratio_max)) bits + + -- 0: decimation at each new sample + -- 1: decimation at each 2 samples + -- and so on + ch_11_sp_decim_ratio_val_o : out std_logic_vector(31 downto 0) ); end wb_fofb_processing_regs; @@ -402,6 +562,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_0_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_0_sp_limits_min_wreq : std_logic; signal ch_0_sp_limits_min_wack : std_logic; + signal ch_0_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_0_sp_decim_ratio_wreq : std_logic; + signal ch_0_sp_decim_ratio_wack : std_logic; signal ch_1_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_1_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_1_coeff_ram_bank_data_rreq : std_logic; @@ -420,6 +583,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_1_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_1_sp_limits_min_wreq : std_logic; signal ch_1_sp_limits_min_wack : std_logic; + signal ch_1_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_1_sp_decim_ratio_wreq : std_logic; + signal ch_1_sp_decim_ratio_wack : std_logic; signal ch_2_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_2_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_2_coeff_ram_bank_data_rreq : std_logic; @@ -438,6 +604,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_2_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_2_sp_limits_min_wreq : std_logic; signal ch_2_sp_limits_min_wack : std_logic; + signal ch_2_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_2_sp_decim_ratio_wreq : std_logic; + signal ch_2_sp_decim_ratio_wack : std_logic; signal ch_3_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_3_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_3_coeff_ram_bank_data_rreq : std_logic; @@ -456,6 +625,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_3_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_3_sp_limits_min_wreq : std_logic; signal ch_3_sp_limits_min_wack : std_logic; + signal ch_3_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_3_sp_decim_ratio_wreq : std_logic; + signal ch_3_sp_decim_ratio_wack : std_logic; signal ch_4_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_4_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_4_coeff_ram_bank_data_rreq : std_logic; @@ -474,6 +646,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_4_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_4_sp_limits_min_wreq : std_logic; signal ch_4_sp_limits_min_wack : std_logic; + signal ch_4_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_4_sp_decim_ratio_wreq : std_logic; + signal ch_4_sp_decim_ratio_wack : std_logic; signal ch_5_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_5_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_5_coeff_ram_bank_data_rreq : std_logic; @@ -492,6 +667,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_5_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_5_sp_limits_min_wreq : std_logic; signal ch_5_sp_limits_min_wack : std_logic; + signal ch_5_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_5_sp_decim_ratio_wreq : std_logic; + signal ch_5_sp_decim_ratio_wack : std_logic; signal ch_6_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_6_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_6_coeff_ram_bank_data_rreq : std_logic; @@ -510,6 +688,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_6_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_6_sp_limits_min_wreq : std_logic; signal ch_6_sp_limits_min_wack : std_logic; + signal ch_6_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_6_sp_decim_ratio_wreq : std_logic; + signal ch_6_sp_decim_ratio_wack : std_logic; signal ch_7_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_7_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_7_coeff_ram_bank_data_rreq : std_logic; @@ -528,6 +709,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_7_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_7_sp_limits_min_wreq : std_logic; signal ch_7_sp_limits_min_wack : std_logic; + signal ch_7_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_7_sp_decim_ratio_wreq : std_logic; + signal ch_7_sp_decim_ratio_wack : std_logic; signal ch_8_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_8_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_8_coeff_ram_bank_data_rreq : std_logic; @@ -546,6 +730,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_8_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_8_sp_limits_min_wreq : std_logic; signal ch_8_sp_limits_min_wack : std_logic; + signal ch_8_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_8_sp_decim_ratio_wreq : std_logic; + signal ch_8_sp_decim_ratio_wack : std_logic; signal ch_9_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_9_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_9_coeff_ram_bank_data_rreq : std_logic; @@ -564,6 +751,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_9_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_9_sp_limits_min_wreq : std_logic; signal ch_9_sp_limits_min_wack : std_logic; + signal ch_9_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_9_sp_decim_ratio_wreq : std_logic; + signal ch_9_sp_decim_ratio_wack : std_logic; signal ch_10_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_10_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_10_coeff_ram_bank_data_rreq : std_logic; @@ -582,6 +772,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_10_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_10_sp_limits_min_wreq : std_logic; signal ch_10_sp_limits_min_wack : std_logic; + signal ch_10_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_10_sp_decim_ratio_wreq : std_logic; + signal ch_10_sp_decim_ratio_wack : std_logic; signal ch_11_coeff_ram_bank_data_int_dato : std_logic_vector(31 downto 0); signal ch_11_coeff_ram_bank_data_ext_dat : std_logic_vector(31 downto 0); signal ch_11_coeff_ram_bank_data_rreq : std_logic; @@ -600,6 +793,9 @@ architecture syn of wb_fofb_processing_regs is signal ch_11_sp_limits_min_val_reg : std_logic_vector(31 downto 0); signal ch_11_sp_limits_min_wreq : std_logic; signal ch_11_sp_limits_min_wack : std_logic; + signal ch_11_sp_decim_ratio_val_reg : std_logic_vector(31 downto 0); + signal ch_11_sp_decim_ratio_wreq : std_logic; + signal ch_11_sp_decim_ratio_wack : std_logic; signal rd_ack_d0 : std_logic; signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; @@ -771,6 +967,8 @@ begin end if; end process; + -- Register sp_decim_ratio_max + -- Memory sps_ram_bank process (adr_int, wr_adr_d0, sps_ram_bank_wr) begin if sps_ram_bank_wr = '1' then @@ -932,6 +1130,24 @@ begin end if; end process; + -- Register ch_0_sp_decim_data + + -- Register ch_0_sp_decim_ratio + ch_0_sp_decim_ratio_val_o <= ch_0_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_0_sp_decim_ratio_wack <= '0'; + else + if ch_0_sp_decim_ratio_wreq = '1' then + ch_0_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_0_sp_decim_ratio_wack <= ch_0_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_1_coeff_ram_bank process (adr_int, wr_adr_d0, ch_1_coeff_ram_bank_wr) begin if ch_1_coeff_ram_bank_wr = '1' then @@ -1047,6 +1263,24 @@ begin end if; end process; + -- Register ch_1_sp_decim_data + + -- Register ch_1_sp_decim_ratio + ch_1_sp_decim_ratio_val_o <= ch_1_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_1_sp_decim_ratio_wack <= '0'; + else + if ch_1_sp_decim_ratio_wreq = '1' then + ch_1_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_1_sp_decim_ratio_wack <= ch_1_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_2_coeff_ram_bank process (adr_int, wr_adr_d0, ch_2_coeff_ram_bank_wr) begin if ch_2_coeff_ram_bank_wr = '1' then @@ -1162,6 +1396,24 @@ begin end if; end process; + -- Register ch_2_sp_decim_data + + -- Register ch_2_sp_decim_ratio + ch_2_sp_decim_ratio_val_o <= ch_2_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_2_sp_decim_ratio_wack <= '0'; + else + if ch_2_sp_decim_ratio_wreq = '1' then + ch_2_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_2_sp_decim_ratio_wack <= ch_2_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_3_coeff_ram_bank process (adr_int, wr_adr_d0, ch_3_coeff_ram_bank_wr) begin if ch_3_coeff_ram_bank_wr = '1' then @@ -1277,6 +1529,24 @@ begin end if; end process; + -- Register ch_3_sp_decim_data + + -- Register ch_3_sp_decim_ratio + ch_3_sp_decim_ratio_val_o <= ch_3_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_3_sp_decim_ratio_wack <= '0'; + else + if ch_3_sp_decim_ratio_wreq = '1' then + ch_3_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_3_sp_decim_ratio_wack <= ch_3_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_4_coeff_ram_bank process (adr_int, wr_adr_d0, ch_4_coeff_ram_bank_wr) begin if ch_4_coeff_ram_bank_wr = '1' then @@ -1392,6 +1662,24 @@ begin end if; end process; + -- Register ch_4_sp_decim_data + + -- Register ch_4_sp_decim_ratio + ch_4_sp_decim_ratio_val_o <= ch_4_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_4_sp_decim_ratio_wack <= '0'; + else + if ch_4_sp_decim_ratio_wreq = '1' then + ch_4_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_4_sp_decim_ratio_wack <= ch_4_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_5_coeff_ram_bank process (adr_int, wr_adr_d0, ch_5_coeff_ram_bank_wr) begin if ch_5_coeff_ram_bank_wr = '1' then @@ -1507,6 +1795,24 @@ begin end if; end process; + -- Register ch_5_sp_decim_data + + -- Register ch_5_sp_decim_ratio + ch_5_sp_decim_ratio_val_o <= ch_5_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_5_sp_decim_ratio_wack <= '0'; + else + if ch_5_sp_decim_ratio_wreq = '1' then + ch_5_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_5_sp_decim_ratio_wack <= ch_5_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_6_coeff_ram_bank process (adr_int, wr_adr_d0, ch_6_coeff_ram_bank_wr) begin if ch_6_coeff_ram_bank_wr = '1' then @@ -1622,6 +1928,24 @@ begin end if; end process; + -- Register ch_6_sp_decim_data + + -- Register ch_6_sp_decim_ratio + ch_6_sp_decim_ratio_val_o <= ch_6_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_6_sp_decim_ratio_wack <= '0'; + else + if ch_6_sp_decim_ratio_wreq = '1' then + ch_6_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_6_sp_decim_ratio_wack <= ch_6_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_7_coeff_ram_bank process (adr_int, wr_adr_d0, ch_7_coeff_ram_bank_wr) begin if ch_7_coeff_ram_bank_wr = '1' then @@ -1737,6 +2061,24 @@ begin end if; end process; + -- Register ch_7_sp_decim_data + + -- Register ch_7_sp_decim_ratio + ch_7_sp_decim_ratio_val_o <= ch_7_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_7_sp_decim_ratio_wack <= '0'; + else + if ch_7_sp_decim_ratio_wreq = '1' then + ch_7_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_7_sp_decim_ratio_wack <= ch_7_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_8_coeff_ram_bank process (adr_int, wr_adr_d0, ch_8_coeff_ram_bank_wr) begin if ch_8_coeff_ram_bank_wr = '1' then @@ -1852,6 +2194,24 @@ begin end if; end process; + -- Register ch_8_sp_decim_data + + -- Register ch_8_sp_decim_ratio + ch_8_sp_decim_ratio_val_o <= ch_8_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_8_sp_decim_ratio_wack <= '0'; + else + if ch_8_sp_decim_ratio_wreq = '1' then + ch_8_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_8_sp_decim_ratio_wack <= ch_8_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_9_coeff_ram_bank process (adr_int, wr_adr_d0, ch_9_coeff_ram_bank_wr) begin if ch_9_coeff_ram_bank_wr = '1' then @@ -1967,6 +2327,24 @@ begin end if; end process; + -- Register ch_9_sp_decim_data + + -- Register ch_9_sp_decim_ratio + ch_9_sp_decim_ratio_val_o <= ch_9_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_9_sp_decim_ratio_wack <= '0'; + else + if ch_9_sp_decim_ratio_wreq = '1' then + ch_9_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_9_sp_decim_ratio_wack <= ch_9_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_10_coeff_ram_bank process (adr_int, wr_adr_d0, ch_10_coeff_ram_bank_wr) begin if ch_10_coeff_ram_bank_wr = '1' then @@ -2082,6 +2460,24 @@ begin end if; end process; + -- Register ch_10_sp_decim_data + + -- Register ch_10_sp_decim_ratio + ch_10_sp_decim_ratio_val_o <= ch_10_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_10_sp_decim_ratio_wack <= '0'; + else + if ch_10_sp_decim_ratio_wreq = '1' then + ch_10_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_10_sp_decim_ratio_wack <= ch_10_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Memory ch_11_coeff_ram_bank process (adr_int, wr_adr_d0, ch_11_coeff_ram_bank_wr) begin if ch_11_coeff_ram_bank_wr = '1' then @@ -2197,8 +2593,26 @@ begin end if; end process; + -- Register ch_11_sp_decim_data + + -- Register ch_11_sp_decim_ratio + ch_11_sp_decim_ratio_val_o <= ch_11_sp_decim_ratio_val_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_sp_decim_ratio_val_reg <= "00000000000000000000000000000000"; + ch_11_sp_decim_ratio_wack <= '0'; + else + if ch_11_sp_decim_ratio_wreq = '1' then + ch_11_sp_decim_ratio_val_reg <= wr_dat_d0; + end if; + ch_11_sp_decim_ratio_wack <= ch_11_sp_decim_ratio_wreq; + end if; + end if; + end process; + -- Process for write requests. - process (wr_adr_d0, wr_req_d0, loop_intlk_ctl_wack, loop_intlk_orb_distort_limit_wack, loop_intlk_min_num_pkts_wack, ch_0_acc_ctl_wack, ch_0_acc_gain_wack, ch_0_sp_limits_max_wack, ch_0_sp_limits_min_wack, ch_1_acc_ctl_wack, ch_1_acc_gain_wack, ch_1_sp_limits_max_wack, ch_1_sp_limits_min_wack, ch_2_acc_ctl_wack, ch_2_acc_gain_wack, ch_2_sp_limits_max_wack, ch_2_sp_limits_min_wack, ch_3_acc_ctl_wack, ch_3_acc_gain_wack, ch_3_sp_limits_max_wack, ch_3_sp_limits_min_wack, ch_4_acc_ctl_wack, ch_4_acc_gain_wack, ch_4_sp_limits_max_wack, ch_4_sp_limits_min_wack, ch_5_acc_ctl_wack, ch_5_acc_gain_wack, ch_5_sp_limits_max_wack, ch_5_sp_limits_min_wack, ch_6_acc_ctl_wack, ch_6_acc_gain_wack, ch_6_sp_limits_max_wack, ch_6_sp_limits_min_wack, ch_7_acc_ctl_wack, ch_7_acc_gain_wack, ch_7_sp_limits_max_wack, ch_7_sp_limits_min_wack, ch_8_acc_ctl_wack, ch_8_acc_gain_wack, ch_8_sp_limits_max_wack, ch_8_sp_limits_min_wack, ch_9_acc_ctl_wack, ch_9_acc_gain_wack, ch_9_sp_limits_max_wack, ch_9_sp_limits_min_wack, ch_10_acc_ctl_wack, ch_10_acc_gain_wack, ch_10_sp_limits_max_wack, ch_10_sp_limits_min_wack, ch_11_acc_ctl_wack, ch_11_acc_gain_wack, ch_11_sp_limits_max_wack, ch_11_sp_limits_min_wack) begin + process (wr_adr_d0, wr_req_d0, loop_intlk_ctl_wack, loop_intlk_orb_distort_limit_wack, loop_intlk_min_num_pkts_wack, ch_0_acc_ctl_wack, ch_0_acc_gain_wack, ch_0_sp_limits_max_wack, ch_0_sp_limits_min_wack, ch_0_sp_decim_ratio_wack, ch_1_acc_ctl_wack, ch_1_acc_gain_wack, ch_1_sp_limits_max_wack, ch_1_sp_limits_min_wack, ch_1_sp_decim_ratio_wack, ch_2_acc_ctl_wack, ch_2_acc_gain_wack, ch_2_sp_limits_max_wack, ch_2_sp_limits_min_wack, ch_2_sp_decim_ratio_wack, ch_3_acc_ctl_wack, ch_3_acc_gain_wack, ch_3_sp_limits_max_wack, ch_3_sp_limits_min_wack, ch_3_sp_decim_ratio_wack, ch_4_acc_ctl_wack, ch_4_acc_gain_wack, ch_4_sp_limits_max_wack, ch_4_sp_limits_min_wack, ch_4_sp_decim_ratio_wack, ch_5_acc_ctl_wack, ch_5_acc_gain_wack, ch_5_sp_limits_max_wack, ch_5_sp_limits_min_wack, ch_5_sp_decim_ratio_wack, ch_6_acc_ctl_wack, ch_6_acc_gain_wack, ch_6_sp_limits_max_wack, ch_6_sp_limits_min_wack, ch_6_sp_decim_ratio_wack, ch_7_acc_ctl_wack, ch_7_acc_gain_wack, ch_7_sp_limits_max_wack, ch_7_sp_limits_min_wack, ch_7_sp_decim_ratio_wack, ch_8_acc_ctl_wack, ch_8_acc_gain_wack, ch_8_sp_limits_max_wack, ch_8_sp_limits_min_wack, ch_8_sp_decim_ratio_wack, ch_9_acc_ctl_wack, ch_9_acc_gain_wack, ch_9_sp_limits_max_wack, ch_9_sp_limits_min_wack, ch_9_sp_decim_ratio_wack, ch_10_acc_ctl_wack, ch_10_acc_gain_wack, ch_10_sp_limits_max_wack, ch_10_sp_limits_min_wack, ch_10_sp_decim_ratio_wack, ch_11_acc_ctl_wack, ch_11_acc_gain_wack, ch_11_sp_limits_max_wack, ch_11_sp_limits_min_wack, ch_11_sp_decim_ratio_wack) begin loop_intlk_ctl_wreq <= '0'; loop_intlk_orb_distort_limit_wreq <= '0'; loop_intlk_min_num_pkts_wreq <= '0'; @@ -2208,61 +2622,73 @@ begin ch_0_acc_gain_wreq <= '0'; ch_0_sp_limits_max_wreq <= '0'; ch_0_sp_limits_min_wreq <= '0'; + ch_0_sp_decim_ratio_wreq <= '0'; ch_1_coeff_ram_bank_data_int_wr <= '0'; ch_1_acc_ctl_wreq <= '0'; ch_1_acc_gain_wreq <= '0'; ch_1_sp_limits_max_wreq <= '0'; ch_1_sp_limits_min_wreq <= '0'; + ch_1_sp_decim_ratio_wreq <= '0'; ch_2_coeff_ram_bank_data_int_wr <= '0'; ch_2_acc_ctl_wreq <= '0'; ch_2_acc_gain_wreq <= '0'; ch_2_sp_limits_max_wreq <= '0'; ch_2_sp_limits_min_wreq <= '0'; + ch_2_sp_decim_ratio_wreq <= '0'; ch_3_coeff_ram_bank_data_int_wr <= '0'; ch_3_acc_ctl_wreq <= '0'; ch_3_acc_gain_wreq <= '0'; ch_3_sp_limits_max_wreq <= '0'; ch_3_sp_limits_min_wreq <= '0'; + ch_3_sp_decim_ratio_wreq <= '0'; ch_4_coeff_ram_bank_data_int_wr <= '0'; ch_4_acc_ctl_wreq <= '0'; ch_4_acc_gain_wreq <= '0'; ch_4_sp_limits_max_wreq <= '0'; ch_4_sp_limits_min_wreq <= '0'; + ch_4_sp_decim_ratio_wreq <= '0'; ch_5_coeff_ram_bank_data_int_wr <= '0'; ch_5_acc_ctl_wreq <= '0'; ch_5_acc_gain_wreq <= '0'; ch_5_sp_limits_max_wreq <= '0'; ch_5_sp_limits_min_wreq <= '0'; + ch_5_sp_decim_ratio_wreq <= '0'; ch_6_coeff_ram_bank_data_int_wr <= '0'; ch_6_acc_ctl_wreq <= '0'; ch_6_acc_gain_wreq <= '0'; ch_6_sp_limits_max_wreq <= '0'; ch_6_sp_limits_min_wreq <= '0'; + ch_6_sp_decim_ratio_wreq <= '0'; ch_7_coeff_ram_bank_data_int_wr <= '0'; ch_7_acc_ctl_wreq <= '0'; ch_7_acc_gain_wreq <= '0'; ch_7_sp_limits_max_wreq <= '0'; ch_7_sp_limits_min_wreq <= '0'; + ch_7_sp_decim_ratio_wreq <= '0'; ch_8_coeff_ram_bank_data_int_wr <= '0'; ch_8_acc_ctl_wreq <= '0'; ch_8_acc_gain_wreq <= '0'; ch_8_sp_limits_max_wreq <= '0'; ch_8_sp_limits_min_wreq <= '0'; + ch_8_sp_decim_ratio_wreq <= '0'; ch_9_coeff_ram_bank_data_int_wr <= '0'; ch_9_acc_ctl_wreq <= '0'; ch_9_acc_gain_wreq <= '0'; ch_9_sp_limits_max_wreq <= '0'; ch_9_sp_limits_min_wreq <= '0'; + ch_9_sp_decim_ratio_wreq <= '0'; ch_10_coeff_ram_bank_data_int_wr <= '0'; ch_10_acc_ctl_wreq <= '0'; ch_10_acc_gain_wreq <= '0'; ch_10_sp_limits_max_wreq <= '0'; ch_10_sp_limits_min_wreq <= '0'; + ch_10_sp_decim_ratio_wreq <= '0'; ch_11_coeff_ram_bank_data_int_wr <= '0'; ch_11_acc_ctl_wreq <= '0'; ch_11_acc_gain_wreq <= '0'; ch_11_sp_limits_max_wreq <= '0'; ch_11_sp_limits_min_wreq <= '0'; + ch_11_sp_decim_ratio_wreq <= '0'; case wr_adr_d0(15 downto 11) is when "00000" => case wr_adr_d0(10 downto 2) is @@ -2287,6 +2713,9 @@ begin -- Reg loop_intlk_min_num_pkts loop_intlk_min_num_pkts_wreq <= wr_req_d0; wr_ack_int <= loop_intlk_min_num_pkts_wack; + when "000100000" => + -- Reg sp_decim_ratio_max + wr_ack_int <= wr_req_d0; when others => wr_ack_int <= wr_req_d0; end case; @@ -2316,6 +2745,13 @@ begin -- Reg ch_0_sp_limits_min ch_0_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_0_sp_limits_min_wack; + when "000001010" => + -- Reg ch_0_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_0_sp_decim_ratio + ch_0_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_0_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2341,6 +2777,13 @@ begin -- Reg ch_1_sp_limits_min ch_1_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_1_sp_limits_min_wack; + when "000001010" => + -- Reg ch_1_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_1_sp_decim_ratio + ch_1_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_1_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2366,6 +2809,13 @@ begin -- Reg ch_2_sp_limits_min ch_2_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_2_sp_limits_min_wack; + when "000001010" => + -- Reg ch_2_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_2_sp_decim_ratio + ch_2_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_2_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2391,6 +2841,13 @@ begin -- Reg ch_3_sp_limits_min ch_3_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_3_sp_limits_min_wack; + when "000001010" => + -- Reg ch_3_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_3_sp_decim_ratio + ch_3_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_3_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2416,6 +2873,13 @@ begin -- Reg ch_4_sp_limits_min ch_4_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_4_sp_limits_min_wack; + when "000001010" => + -- Reg ch_4_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_4_sp_decim_ratio + ch_4_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_4_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2441,6 +2905,13 @@ begin -- Reg ch_5_sp_limits_min ch_5_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_5_sp_limits_min_wack; + when "000001010" => + -- Reg ch_5_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_5_sp_decim_ratio + ch_5_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_5_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2466,6 +2937,13 @@ begin -- Reg ch_6_sp_limits_min ch_6_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_6_sp_limits_min_wack; + when "000001010" => + -- Reg ch_6_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_6_sp_decim_ratio + ch_6_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_6_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2491,6 +2969,13 @@ begin -- Reg ch_7_sp_limits_min ch_7_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_7_sp_limits_min_wack; + when "000001010" => + -- Reg ch_7_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_7_sp_decim_ratio + ch_7_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_7_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2516,6 +3001,13 @@ begin -- Reg ch_8_sp_limits_min ch_8_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_8_sp_limits_min_wack; + when "000001010" => + -- Reg ch_8_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_8_sp_decim_ratio + ch_8_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_8_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2541,6 +3033,13 @@ begin -- Reg ch_9_sp_limits_min ch_9_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_9_sp_limits_min_wack; + when "000001010" => + -- Reg ch_9_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_9_sp_decim_ratio + ch_9_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_9_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2566,6 +3065,13 @@ begin -- Reg ch_10_sp_limits_min ch_10_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_10_sp_limits_min_wack; + when "000001010" => + -- Reg ch_10_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_10_sp_decim_ratio + ch_10_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_10_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2591,6 +3097,13 @@ begin -- Reg ch_11_sp_limits_min ch_11_sp_limits_min_wreq <= wr_req_d0; wr_ack_int <= ch_11_sp_limits_min_wack; + when "000001010" => + -- Reg ch_11_sp_decim_data + wr_ack_int <= wr_req_d0; + when "000001011" => + -- Reg ch_11_sp_decim_ratio + ch_11_sp_decim_ratio_wreq <= wr_req_d0; + wr_ack_int <= ch_11_sp_decim_ratio_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -2600,7 +3113,7 @@ begin end process; -- Process for read requests. - process (adr_int, rd_req_int, fixed_point_pos_coeff_val_i, fixed_point_pos_accs_gains_val_i, loop_intlk_ctl_src_en_orb_distort_reg, loop_intlk_ctl_src_en_packet_loss_reg, loop_intlk_sta_orb_distort_i, loop_intlk_sta_packet_loss_i, loop_intlk_orb_distort_limit_val_reg, loop_intlk_min_num_pkts_val_reg, sps_ram_bank_data_int_dato, sps_ram_bank_data_rack, ch_0_coeff_ram_bank_data_int_dato, ch_0_coeff_ram_bank_data_rack, ch_0_acc_ctl_freeze_reg, ch_0_acc_gain_val_reg, ch_0_sp_limits_max_val_reg, ch_0_sp_limits_min_val_reg, ch_1_coeff_ram_bank_data_int_dato, ch_1_coeff_ram_bank_data_rack, ch_1_acc_ctl_freeze_reg, ch_1_acc_gain_val_reg, ch_1_sp_limits_max_val_reg, ch_1_sp_limits_min_val_reg, ch_2_coeff_ram_bank_data_int_dato, ch_2_coeff_ram_bank_data_rack, ch_2_acc_ctl_freeze_reg, ch_2_acc_gain_val_reg, ch_2_sp_limits_max_val_reg, ch_2_sp_limits_min_val_reg, ch_3_coeff_ram_bank_data_int_dato, ch_3_coeff_ram_bank_data_rack, ch_3_acc_ctl_freeze_reg, ch_3_acc_gain_val_reg, ch_3_sp_limits_max_val_reg, ch_3_sp_limits_min_val_reg, ch_4_coeff_ram_bank_data_int_dato, ch_4_coeff_ram_bank_data_rack, ch_4_acc_ctl_freeze_reg, ch_4_acc_gain_val_reg, ch_4_sp_limits_max_val_reg, ch_4_sp_limits_min_val_reg, ch_5_coeff_ram_bank_data_int_dato, ch_5_coeff_ram_bank_data_rack, ch_5_acc_ctl_freeze_reg, ch_5_acc_gain_val_reg, ch_5_sp_limits_max_val_reg, ch_5_sp_limits_min_val_reg, ch_6_coeff_ram_bank_data_int_dato, ch_6_coeff_ram_bank_data_rack, ch_6_acc_ctl_freeze_reg, ch_6_acc_gain_val_reg, ch_6_sp_limits_max_val_reg, ch_6_sp_limits_min_val_reg, ch_7_coeff_ram_bank_data_int_dato, ch_7_coeff_ram_bank_data_rack, ch_7_acc_ctl_freeze_reg, ch_7_acc_gain_val_reg, ch_7_sp_limits_max_val_reg, ch_7_sp_limits_min_val_reg, ch_8_coeff_ram_bank_data_int_dato, ch_8_coeff_ram_bank_data_rack, ch_8_acc_ctl_freeze_reg, ch_8_acc_gain_val_reg, ch_8_sp_limits_max_val_reg, ch_8_sp_limits_min_val_reg, ch_9_coeff_ram_bank_data_int_dato, ch_9_coeff_ram_bank_data_rack, ch_9_acc_ctl_freeze_reg, ch_9_acc_gain_val_reg, ch_9_sp_limits_max_val_reg, ch_9_sp_limits_min_val_reg, ch_10_coeff_ram_bank_data_int_dato, ch_10_coeff_ram_bank_data_rack, ch_10_acc_ctl_freeze_reg, ch_10_acc_gain_val_reg, ch_10_sp_limits_max_val_reg, ch_10_sp_limits_min_val_reg, ch_11_coeff_ram_bank_data_int_dato, ch_11_coeff_ram_bank_data_rack, ch_11_acc_ctl_freeze_reg, ch_11_acc_gain_val_reg, ch_11_sp_limits_max_val_reg, ch_11_sp_limits_min_val_reg) begin + process (adr_int, rd_req_int, fixed_point_pos_coeff_val_i, fixed_point_pos_accs_gains_val_i, loop_intlk_ctl_src_en_orb_distort_reg, loop_intlk_ctl_src_en_packet_loss_reg, loop_intlk_sta_orb_distort_i, loop_intlk_sta_packet_loss_i, loop_intlk_orb_distort_limit_val_reg, loop_intlk_min_num_pkts_val_reg, sp_decim_ratio_max_cte_i, sps_ram_bank_data_int_dato, sps_ram_bank_data_rack, ch_0_coeff_ram_bank_data_int_dato, ch_0_coeff_ram_bank_data_rack, ch_0_acc_ctl_freeze_reg, ch_0_acc_gain_val_reg, ch_0_sp_limits_max_val_reg, ch_0_sp_limits_min_val_reg, ch_0_sp_decim_data_val_i, ch_0_sp_decim_ratio_val_reg, ch_1_coeff_ram_bank_data_int_dato, ch_1_coeff_ram_bank_data_rack, ch_1_acc_ctl_freeze_reg, ch_1_acc_gain_val_reg, ch_1_sp_limits_max_val_reg, ch_1_sp_limits_min_val_reg, ch_1_sp_decim_data_val_i, ch_1_sp_decim_ratio_val_reg, ch_2_coeff_ram_bank_data_int_dato, ch_2_coeff_ram_bank_data_rack, ch_2_acc_ctl_freeze_reg, ch_2_acc_gain_val_reg, ch_2_sp_limits_max_val_reg, ch_2_sp_limits_min_val_reg, ch_2_sp_decim_data_val_i, ch_2_sp_decim_ratio_val_reg, ch_3_coeff_ram_bank_data_int_dato, ch_3_coeff_ram_bank_data_rack, ch_3_acc_ctl_freeze_reg, ch_3_acc_gain_val_reg, ch_3_sp_limits_max_val_reg, ch_3_sp_limits_min_val_reg, ch_3_sp_decim_data_val_i, ch_3_sp_decim_ratio_val_reg, ch_4_coeff_ram_bank_data_int_dato, ch_4_coeff_ram_bank_data_rack, ch_4_acc_ctl_freeze_reg, ch_4_acc_gain_val_reg, ch_4_sp_limits_max_val_reg, ch_4_sp_limits_min_val_reg, ch_4_sp_decim_data_val_i, ch_4_sp_decim_ratio_val_reg, ch_5_coeff_ram_bank_data_int_dato, ch_5_coeff_ram_bank_data_rack, ch_5_acc_ctl_freeze_reg, ch_5_acc_gain_val_reg, ch_5_sp_limits_max_val_reg, ch_5_sp_limits_min_val_reg, ch_5_sp_decim_data_val_i, ch_5_sp_decim_ratio_val_reg, ch_6_coeff_ram_bank_data_int_dato, ch_6_coeff_ram_bank_data_rack, ch_6_acc_ctl_freeze_reg, ch_6_acc_gain_val_reg, ch_6_sp_limits_max_val_reg, ch_6_sp_limits_min_val_reg, ch_6_sp_decim_data_val_i, ch_6_sp_decim_ratio_val_reg, ch_7_coeff_ram_bank_data_int_dato, ch_7_coeff_ram_bank_data_rack, ch_7_acc_ctl_freeze_reg, ch_7_acc_gain_val_reg, ch_7_sp_limits_max_val_reg, ch_7_sp_limits_min_val_reg, ch_7_sp_decim_data_val_i, ch_7_sp_decim_ratio_val_reg, ch_8_coeff_ram_bank_data_int_dato, ch_8_coeff_ram_bank_data_rack, ch_8_acc_ctl_freeze_reg, ch_8_acc_gain_val_reg, ch_8_sp_limits_max_val_reg, ch_8_sp_limits_min_val_reg, ch_8_sp_decim_data_val_i, ch_8_sp_decim_ratio_val_reg, ch_9_coeff_ram_bank_data_int_dato, ch_9_coeff_ram_bank_data_rack, ch_9_acc_ctl_freeze_reg, ch_9_acc_gain_val_reg, ch_9_sp_limits_max_val_reg, ch_9_sp_limits_min_val_reg, ch_9_sp_decim_data_val_i, ch_9_sp_decim_ratio_val_reg, ch_10_coeff_ram_bank_data_int_dato, ch_10_coeff_ram_bank_data_rack, ch_10_acc_ctl_freeze_reg, ch_10_acc_gain_val_reg, ch_10_sp_limits_max_val_reg, ch_10_sp_limits_min_val_reg, ch_10_sp_decim_data_val_i, ch_10_sp_decim_ratio_val_reg, ch_11_coeff_ram_bank_data_int_dato, ch_11_coeff_ram_bank_data_rack, ch_11_acc_ctl_freeze_reg, ch_11_acc_gain_val_reg, ch_11_sp_limits_max_val_reg, ch_11_sp_limits_min_val_reg, ch_11_sp_decim_data_val_i, ch_11_sp_decim_ratio_val_reg) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); sps_ram_bank_data_rreq <= '0'; @@ -2648,6 +3161,10 @@ begin -- Reg loop_intlk_min_num_pkts rd_ack_d0 <= rd_req_int; rd_dat_d0 <= loop_intlk_min_num_pkts_val_reg; + when "000100000" => + -- Reg sp_decim_ratio_max + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= sp_decim_ratio_max_cte_i; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2681,6 +3198,14 @@ begin -- Reg ch_0_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_0_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_0_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_0_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_0_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_0_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2709,6 +3234,14 @@ begin -- Reg ch_1_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_1_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_1_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_1_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_1_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_1_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2737,6 +3270,14 @@ begin -- Reg ch_2_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_2_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_2_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_2_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_2_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_2_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2765,6 +3306,14 @@ begin -- Reg ch_3_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_3_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_3_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_3_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_3_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_3_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2793,6 +3342,14 @@ begin -- Reg ch_4_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_4_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_4_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_4_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_4_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_4_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2821,6 +3378,14 @@ begin -- Reg ch_5_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_5_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_5_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_5_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_5_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_5_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2849,6 +3414,14 @@ begin -- Reg ch_6_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_6_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_6_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_6_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_6_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_6_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2877,6 +3450,14 @@ begin -- Reg ch_7_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_7_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_7_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_7_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_7_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_7_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2905,6 +3486,14 @@ begin -- Reg ch_8_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_8_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_8_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_8_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_8_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_8_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2933,6 +3522,14 @@ begin -- Reg ch_9_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_9_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_9_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_9_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_9_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_9_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2961,6 +3558,14 @@ begin -- Reg ch_10_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_10_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_10_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_10_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_10_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_10_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; @@ -2989,6 +3594,14 @@ begin -- Reg ch_11_sp_limits_min rd_ack_d0 <= rd_req_int; rd_dat_d0 <= ch_11_sp_limits_min_val_reg; + when "000001010" => + -- Reg ch_11_sp_decim_data + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_11_sp_decim_data_val_i; + when "000001011" => + -- Reg ch_11_sp_decim_ratio + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= ch_11_sp_decim_ratio_val_reg; when others => rd_ack_d0 <= rd_req_int; end case; diff --git a/hdl/modules/fofb_processing/dot_prod_pkg.vhd b/hdl/modules/fofb_processing/dot_prod_pkg.vhd index 1f0f09a5..7bdd7f7f 100644 --- a/hdl/modules/fofb_processing/dot_prod_pkg.vhd +++ b/hdl/modules/fofb_processing/dot_prod_pkg.vhd @@ -207,6 +207,7 @@ package dot_prod_pkg is sp_valid_o : out std_logic; -- Setpoint decimation ratio + -- 0 -> decimation at each new sample, 1 -> decimation at each 2 samples, and so on sp_decim_ratio_i : in integer range 0 to g_SP_DECIM_MAX_RATIO := 4600; -- Decimated setpoint @@ -309,6 +310,7 @@ package dot_prod_pkg is sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); -- Setpoint decimation ratio (for each channel) + -- 0 -> decimation at each new sample, 1 -> decimation at each 2 samples, and so on sp_decim_ratio_arr_i : in t_fofb_processing_sp_decim_ratio_arr(g_CHANNELS-1 downto 0); -- Decimated setpoint (for each channel) diff --git a/hdl/modules/fofb_processing/fofb_processing.vhd b/hdl/modules/fofb_processing/fofb_processing.vhd index a54de433..b76107ec 100644 --- a/hdl/modules/fofb_processing/fofb_processing.vhd +++ b/hdl/modules/fofb_processing/fofb_processing.vhd @@ -122,6 +122,7 @@ entity fofb_processing is sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); -- Setpoint decimation ratio (for each channel) + -- 0 -> decimation at each new sample, 1 -> decimation at each 2 samples, and so on sp_decim_ratio_arr_i : in t_fofb_processing_sp_decim_ratio_arr(g_CHANNELS-1 downto 0); -- Decimated setpoint (for each channel) diff --git a/hdl/modules/fofb_processing/fofb_processing_channel.vhd b/hdl/modules/fofb_processing/fofb_processing_channel.vhd index ee0bb17f..f55a322a 100644 --- a/hdl/modules/fofb_processing/fofb_processing_channel.vhd +++ b/hdl/modules/fofb_processing/fofb_processing_channel.vhd @@ -137,6 +137,7 @@ entity fofb_processing_channel is sp_valid_o : out std_logic; -- Setpoint decimation ratio + -- 0 -> decimation at each new sample, 1 -> decimation at each 2 samples, and so on sp_decim_ratio_i : in integer range 0 to g_SP_DECIM_MAX_RATIO := 4600; -- Decimated setpoint diff --git a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd index 46acd33e..714ff51b 100644 --- a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd +++ b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd @@ -19,6 +19,7 @@ -- 2022-01-11 2.1 guilherme.ricioli Expose loop interlock regs -- 2023-02-10 3.0 guilherme.ricioli Update to match the new -- wb_fofb_processing_regs api +-- 2023-03-02 3.1 guilherme.ricioli Expose setpoint decimation regs ------------------------------------------------------------------------------- library ieee; @@ -101,6 +102,12 @@ entity xwb_fofb_processing is -- Set-point valid array (for each channel) sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + -- Decimated setpoint (for each channel) + sp_decim_arr_o : out t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0); + + -- Decimated setpoint valid (for each channel) + sp_decim_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0); + dcc_p2p_en_o : out std_logic; --------------------------------------------------------------------------- @@ -138,6 +145,12 @@ architecture rtl of xwb_fofb_processing is constant c_GAIN_FIXED_POINT_POS_VAL : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(31 - c_FOFB_GAIN_INT_WIDTH, 32)); + -- Maximum setpoint decimation ratio constant + -- Upper software layers can use this to restrict setpoint decimation ratio + -- values + constant c_SP_DECIM_RATIO_MAX_CTE : std_logic_vector(31 downto 0) := + std_logic_vector(to_unsigned(c_FOFB_SP_DECIM_MAX_RATIO, 32)); + ----------------------------- -- Signals ----------------------------- @@ -171,6 +184,14 @@ architecture rtl of xwb_fofb_processing is signal sp_limits_max_val_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); signal sp_limits_min_val_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); + ----------------------------- + -- Output decimation signals + ----------------------------- + signal sp_decim_ratio_arr : t_fofb_processing_sp_decim_ratio_arr(g_CHANNELS-1 downto 0); + signal sp_decim_arr : t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0); + signal sp_decim_ratio_val_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); + signal sp_decim_data_val_arr : t_fofb_processing_wb_sp_arr(c_MAX_CHANNELS-1 downto 0); + ----------------------------- -- Loop interlock signals ----------------------------- @@ -229,9 +250,9 @@ begin sp_min_arr_i => sp_min_arr, sp_arr_o => sp_arr_o, sp_valid_arr_o => sp_valid_arr_o, - sp_decim_ratio_arr_i => (others => 4600), -- at Monit rate (but not synced) - sp_decim_arr_o => open, - sp_decim_valid_arr_o => open, + sp_decim_ratio_arr_i => sp_decim_ratio_arr, + sp_decim_arr_o => sp_decim_arr, + sp_decim_valid_arr_o => sp_decim_valid_arr_o, loop_intlk_src_en_i => loop_intlk_src_en, loop_intlk_state_clr_i => loop_intlk_ctl_sta_clr, loop_intlk_state_o => loop_intlk_sta, @@ -318,6 +339,10 @@ begin sp_max_arr(i) <= signed(sp_limits_max_val_arr(i)(c_FOFB_SP_WIDTH-1 downto 0)); sp_min_arr(i) <= signed(sp_limits_min_val_arr(i)(c_FOFB_SP_WIDTH-1 downto 0)); + + -- TODO: sp_decim_ratio_val_arr should be saturated at c_SP_DECIM_RATIO_MAX_CTE + sp_decim_ratio_arr(i) <= to_integer(unsigned(sp_decim_ratio_val_arr(i))); + sp_decim_data_val_arr(i) <= std_logic_vector(sp_decim_arr(i)); end generate gen_wb_conn; loop_intlk_distort_limit <= unsigned(loop_intlk_orb_distort_limit_val(loop_intlk_distort_limit'left downto 0)); @@ -339,6 +364,7 @@ begin loop_intlk_sta_packet_loss_i => loop_intlk_sta(c_FOFB_LOOP_INTLK_PKT_LOSS_ID), loop_intlk_orb_distort_limit_val_o => loop_intlk_orb_distort_limit_val, loop_intlk_min_num_pkts_val_o => loop_intlk_min_num_pkts_val, + sp_decim_ratio_max_cte_i => c_SP_DECIM_RATIO_MAX_CTE, sps_ram_bank_adr_i => sps_ram_bank_adr, sps_ram_bank_data_rd_i => '0', sps_ram_bank_data_dat_o => sps_ram_bank_data_dat, @@ -350,6 +376,8 @@ begin ch_0_acc_gain_val_o => acc_gain_val_arr(0), ch_0_sp_limits_max_val_o => sp_limits_max_val_arr(0), ch_0_sp_limits_min_val_o => sp_limits_min_val_arr(0), + ch_0_sp_decim_data_val_i => sp_decim_data_val_arr(0), + ch_0_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(0), ch_1_coeff_ram_bank_adr_i => coeff_ram_addr_arr(1), ch_1_coeff_ram_bank_data_rd_i => '0', ch_1_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(1), @@ -358,6 +386,8 @@ begin ch_1_acc_gain_val_o => acc_gain_val_arr(1), ch_1_sp_limits_max_val_o => sp_limits_max_val_arr(1), ch_1_sp_limits_min_val_o => sp_limits_min_val_arr(1), + ch_1_sp_decim_data_val_i => sp_decim_data_val_arr(1), + ch_1_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(1), ch_2_coeff_ram_bank_adr_i => coeff_ram_addr_arr(2), ch_2_coeff_ram_bank_data_rd_i => '0', ch_2_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(2), @@ -366,6 +396,8 @@ begin ch_2_acc_gain_val_o => acc_gain_val_arr(2), ch_2_sp_limits_max_val_o => sp_limits_max_val_arr(2), ch_2_sp_limits_min_val_o => sp_limits_min_val_arr(2), + ch_2_sp_decim_data_val_i => sp_decim_data_val_arr(2), + ch_2_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(2), ch_3_coeff_ram_bank_adr_i => coeff_ram_addr_arr(3), ch_3_coeff_ram_bank_data_rd_i => '0', ch_3_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(3), @@ -374,6 +406,8 @@ begin ch_3_acc_gain_val_o => acc_gain_val_arr(3), ch_3_sp_limits_max_val_o => sp_limits_max_val_arr(3), ch_3_sp_limits_min_val_o => sp_limits_min_val_arr(3), + ch_3_sp_decim_data_val_i => sp_decim_data_val_arr(3), + ch_3_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(3), ch_4_coeff_ram_bank_adr_i => coeff_ram_addr_arr(4), ch_4_coeff_ram_bank_data_rd_i => '0', ch_4_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(4), @@ -382,6 +416,8 @@ begin ch_4_acc_gain_val_o => acc_gain_val_arr(4), ch_4_sp_limits_max_val_o => sp_limits_max_val_arr(4), ch_4_sp_limits_min_val_o => sp_limits_min_val_arr(4), + ch_4_sp_decim_data_val_i => sp_decim_data_val_arr(4), + ch_4_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(4), ch_5_coeff_ram_bank_adr_i => coeff_ram_addr_arr(5), ch_5_coeff_ram_bank_data_rd_i => '0', ch_5_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(5), @@ -390,6 +426,8 @@ begin ch_5_acc_gain_val_o => acc_gain_val_arr(5), ch_5_sp_limits_max_val_o => sp_limits_max_val_arr(5), ch_5_sp_limits_min_val_o => sp_limits_min_val_arr(5), + ch_5_sp_decim_data_val_i => sp_decim_data_val_arr(5), + ch_5_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(5), ch_6_coeff_ram_bank_adr_i => coeff_ram_addr_arr(6), ch_6_coeff_ram_bank_data_rd_i => '0', ch_6_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(6), @@ -398,6 +436,8 @@ begin ch_6_acc_gain_val_o => acc_gain_val_arr(6), ch_6_sp_limits_max_val_o => sp_limits_max_val_arr(6), ch_6_sp_limits_min_val_o => sp_limits_min_val_arr(6), + ch_6_sp_decim_data_val_i => sp_decim_data_val_arr(6), + ch_6_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(6), ch_7_coeff_ram_bank_adr_i => coeff_ram_addr_arr(7), ch_7_coeff_ram_bank_data_rd_i => '0', ch_7_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(7), @@ -406,6 +446,8 @@ begin ch_7_acc_gain_val_o => acc_gain_val_arr(7), ch_7_sp_limits_max_val_o => sp_limits_max_val_arr(7), ch_7_sp_limits_min_val_o => sp_limits_min_val_arr(7), + ch_7_sp_decim_data_val_i => sp_decim_data_val_arr(7), + ch_7_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(7), ch_8_coeff_ram_bank_adr_i => coeff_ram_addr_arr(8), ch_8_coeff_ram_bank_data_rd_i => '0', ch_8_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(8), @@ -414,6 +456,8 @@ begin ch_8_acc_gain_val_o => acc_gain_val_arr(8), ch_8_sp_limits_max_val_o => sp_limits_max_val_arr(8), ch_8_sp_limits_min_val_o => sp_limits_min_val_arr(8), + ch_8_sp_decim_data_val_i => sp_decim_data_val_arr(8), + ch_8_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(8), ch_9_coeff_ram_bank_adr_i => coeff_ram_addr_arr(9), ch_9_coeff_ram_bank_data_rd_i => '0', ch_9_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(9), @@ -422,6 +466,8 @@ begin ch_9_acc_gain_val_o => acc_gain_val_arr(9), ch_9_sp_limits_max_val_o => sp_limits_max_val_arr(9), ch_9_sp_limits_min_val_o => sp_limits_min_val_arr(9), + ch_9_sp_decim_data_val_i => sp_decim_data_val_arr(9), + ch_9_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(9), ch_10_coeff_ram_bank_adr_i => coeff_ram_addr_arr(10), ch_10_coeff_ram_bank_data_rd_i => '0', ch_10_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(10), @@ -430,6 +476,8 @@ begin ch_10_acc_gain_val_o => acc_gain_val_arr(10), ch_10_sp_limits_max_val_o => sp_limits_max_val_arr(10), ch_10_sp_limits_min_val_o => sp_limits_min_val_arr(10), + ch_10_sp_decim_data_val_i => sp_decim_data_val_arr(10), + ch_10_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(10), ch_11_coeff_ram_bank_adr_i => coeff_ram_addr_arr(11), ch_11_coeff_ram_bank_data_rd_i => '0', ch_11_coeff_ram_bank_data_dat_o => coeff_ram_data_arr(11), @@ -437,9 +485,12 @@ begin ch_11_acc_ctl_freeze_o => acc_ctl_freeze_arr(11), ch_11_acc_gain_val_o => acc_gain_val_arr(11), ch_11_sp_limits_max_val_o => sp_limits_max_val_arr(11), - ch_11_sp_limits_min_val_o => sp_limits_min_val_arr(11) + ch_11_sp_limits_min_val_o => sp_limits_min_val_arr(11), + ch_11_sp_decim_data_val_i => sp_decim_data_val_arr(11), + ch_11_sp_decim_ratio_val_o => sp_decim_ratio_val_arr(11) ); dcc_p2p_en_o <= not loop_intlk_sta(c_FOFB_LOOP_INTLK_PKT_LOSS_ID); + sp_decim_arr_o <= sp_decim_arr; end architecture rtl; diff --git a/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd index f653a216..c8a95bca 100644 --- a/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_processing_regs_consts_pkg.vhd @@ -19,6 +19,8 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_ORB_DISTORT_LIMIT_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_ADDR : Natural := 16#4c#; constant c_WB_FOFB_PROCESSING_REGS_LOOP_INTLK_MIN_NUM_PKTS_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_SP_DECIM_RATIO_MAX_ADDR : Natural := 16#80#; + constant c_WB_FOFB_PROCESSING_REGS_SP_DECIM_RATIO_MAX_CTE_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_ADDR : Natural := 16#800#; constant c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_SIZE : Natural := 4; constant c_WB_FOFB_PROCESSING_REGS_SPS_RAM_BANK_DATA_ADDR : Natural := 16#0#; @@ -42,6 +44,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_ADDR : Natural := 16#1824#; constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_ADDR : Natural := 16#1828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_DATA_ADDR : Natural := 16#1828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_RATIO_ADDR : Natural := 16#182c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_1_ADDR : Natural := 16#2000#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_1_COEFF_RAM_BANK_ADDR : Natural := 16#2000#; @@ -60,6 +68,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_ADDR : Natural := 16#2824#; constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_DECIM_ADDR : Natural := 16#2828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_DECIM_DATA_ADDR : Natural := 16#2828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_DECIM_RATIO_ADDR : Natural := 16#282c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_1_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_2_ADDR : Natural := 16#3000#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_2_COEFF_RAM_BANK_ADDR : Natural := 16#3000#; @@ -78,6 +92,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_ADDR : Natural := 16#3824#; constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_DECIM_ADDR : Natural := 16#3828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_DECIM_DATA_ADDR : Natural := 16#3828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_DECIM_RATIO_ADDR : Natural := 16#382c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_2_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_3_ADDR : Natural := 16#4000#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_3_COEFF_RAM_BANK_ADDR : Natural := 16#4000#; @@ -96,6 +116,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_ADDR : Natural := 16#4824#; constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_DECIM_ADDR : Natural := 16#4828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_DECIM_DATA_ADDR : Natural := 16#4828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_DECIM_RATIO_ADDR : Natural := 16#482c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_3_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_4_ADDR : Natural := 16#5000#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_4_COEFF_RAM_BANK_ADDR : Natural := 16#5000#; @@ -114,6 +140,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_ADDR : Natural := 16#5824#; constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_DECIM_ADDR : Natural := 16#5828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_DECIM_DATA_ADDR : Natural := 16#5828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_DECIM_RATIO_ADDR : Natural := 16#582c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_4_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_5_ADDR : Natural := 16#6000#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_5_COEFF_RAM_BANK_ADDR : Natural := 16#6000#; @@ -132,6 +164,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_ADDR : Natural := 16#6824#; constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_DECIM_ADDR : Natural := 16#6828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_DECIM_DATA_ADDR : Natural := 16#6828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_DECIM_RATIO_ADDR : Natural := 16#682c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_5_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_6_ADDR : Natural := 16#7000#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_6_COEFF_RAM_BANK_ADDR : Natural := 16#7000#; @@ -150,6 +188,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_ADDR : Natural := 16#7824#; constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_DECIM_ADDR : Natural := 16#7828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_DECIM_DATA_ADDR : Natural := 16#7828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_DECIM_RATIO_ADDR : Natural := 16#782c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_6_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_7_ADDR : Natural := 16#8000#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_7_COEFF_RAM_BANK_ADDR : Natural := 16#8000#; @@ -168,6 +212,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_ADDR : Natural := 16#8824#; constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_DECIM_ADDR : Natural := 16#8828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_DECIM_DATA_ADDR : Natural := 16#8828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_DECIM_RATIO_ADDR : Natural := 16#882c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_7_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_8_ADDR : Natural := 16#9000#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_8_COEFF_RAM_BANK_ADDR : Natural := 16#9000#; @@ -186,6 +236,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_ADDR : Natural := 16#9824#; constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_DECIM_ADDR : Natural := 16#9828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_DECIM_DATA_ADDR : Natural := 16#9828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_DECIM_RATIO_ADDR : Natural := 16#982c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_8_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_9_ADDR : Natural := 16#a000#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_9_COEFF_RAM_BANK_ADDR : Natural := 16#a000#; @@ -204,6 +260,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_ADDR : Natural := 16#a824#; constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_DECIM_ADDR : Natural := 16#a828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_DECIM_DATA_ADDR : Natural := 16#a828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_DECIM_RATIO_ADDR : Natural := 16#a82c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_9_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_10_ADDR : Natural := 16#b000#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_10_COEFF_RAM_BANK_ADDR : Natural := 16#b000#; @@ -222,6 +284,12 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_ADDR : Natural := 16#b824#; constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_DECIM_ADDR : Natural := 16#b828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_DECIM_DATA_ADDR : Natural := 16#b828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_DECIM_RATIO_ADDR : Natural := 16#b82c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_10_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_11_ADDR : Natural := 16#c000#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SIZE : Natural := 4096; constant c_WB_FOFB_PROCESSING_REGS_CH_11_COEFF_RAM_BANK_ADDR : Natural := 16#c000#; @@ -240,4 +308,10 @@ package wb_fofb_processing_regs_consts_pkg is constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MAX_VAL_OFFSET : Natural := 0; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_ADDR : Natural := 16#c824#; constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_LIMITS_MIN_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_DECIM_ADDR : Natural := 16#c828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_DECIM_SIZE : Natural := 8; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_DECIM_DATA_ADDR : Natural := 16#c828#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_DECIM_DATA_VAL_OFFSET : Natural := 0; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_DECIM_RATIO_ADDR : Natural := 16#c82c#; + constant c_WB_FOFB_PROCESSING_REGS_CH_11_SP_DECIM_RATIO_VAL_OFFSET : Natural := 0; end package wb_fofb_processing_regs_consts_pkg; diff --git a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd index f76fcff6..2bb5e79a 100644 --- a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd +++ b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd @@ -25,6 +25,7 @@ -- loop interlock regs -- 2023-02-15 3.0 guilherme.ricioli Update to match the new -- wb_fofb_processing_regs api +-- 2023-03-03 3.1 guilherme.ricioli Test setpoint decimation regs ------------------------------------------------------------------------------- library ieee; @@ -149,6 +150,12 @@ architecture xwb_fofb_processing_tb_arch of xwb_fofb_processing_tb is signal sp_valid_arr : std_logic_vector(g_CHANNELS-1 downto 0):= (others => '0'); + signal sp_decim_arr : + t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0); + signal sp_decim_valid_arr : + std_logic_vector(g_CHANNELS-1 downto 0); + signal is_there_any_sp_decim_valid : std_logic := '0'; + signal wb_slave_i : t_wishbone_slave_in; signal wb_slave_o : t_wishbone_slave_out; @@ -170,6 +177,7 @@ architecture xwb_fofb_processing_tb_arch of xwb_fofb_processing_tb is begin f_gen_clk(c_SYS_CLOCK_FREQ, clk); + is_there_any_sp_decim_valid <= or sp_decim_valid_arr; -- main process process @@ -187,6 +195,7 @@ begin real_vector(g_CHANNELS-1 downto 0) := (others => 0.0); variable wb_gain : std_logic_vector(c_FOFB_WB_GAIN_WIDTH-1 downto 0); + variable wb_ratio : std_logic_vector(31 downto 0); variable coeff_ram : t_coeff_ram_data; variable sp_ram : t_sp_ram_data; @@ -197,6 +206,10 @@ begin real_vector(g_CHANNELS-1 downto 0) := (others => 0.0); variable sp_err : real := 0.0; + variable expec_fofb_proc_sp_decim_arr : + real_vector(g_CHANNELS-1 downto 0) := (others => 0.0); + variable sp_decim_err : real := 0.0; + variable meas_cnt : natural := 0; variable expec_loop_intlk_state : boolean := false; @@ -333,6 +346,27 @@ begin severity error; end loop; + -- setting setpoints decimation ratios + report "setting setpoints decimation ratios" + severity note; + + offs := c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_RATIO_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR; + for i in 0 to (g_CHANNELS - 1) + loop + wb_ratio := std_logic_vector(to_unsigned(i, 32)); + + addr := f_get_ch_reg_addr(offs, i); + + write32_pl(clk, wb_slave_i, wb_slave_o, addr, wb_ratio); + read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); + + assert (data = wb_ratio) + report "wrong setpoint decimation ratio at " & natural'image(addr) + severity error; + + end loop; + -- setting limit for loop interlock orbit distortion source via wishbone -- bus report @@ -457,6 +491,14 @@ begin end loop; -- ########## computing expected fofb processing setpoint ########## + -- ######## computing expected fofb processing decimated setpoint ######## + for i in 0 to g_CHANNELS-1 + loop + expec_fofb_proc_sp_decim_arr(i) := expec_fofb_proc_sp_decim_arr(i) + + expec_fofb_proc_sp_arr(i); + end loop; + -- ######## computing expected fofb processing decimated setpoint ######## + -- time frame ended bpm_time_frame_end <= '1'; f_wait_cycles(clk, 1); @@ -488,6 +530,55 @@ begin severity note; end if; end loop; + + -- Checks if any new decimated/filtered setpoint is ready (if more than + -- one, they happen at the same cycle) + f_wait_clocked_signal(clk, is_there_any_sp_decim_valid, '1', 10); + + for i in 0 to g_CHANNELS-1 + loop + if sp_decim_valid_arr(i) = '1' then + -- TODO: this may be problematic for small values + sp_decim_err := abs((real(to_integer(sp_decim_arr(i))) / + floor(expec_fofb_proc_sp_decim_arr(i))) - 1.0); + + report "channel " & to_string(i) & ": " & + "decimated setpoint: " & to_string(to_integer(sp_decim_arr(i))) & + " (expected: " & + to_string(integer(floor(expec_fofb_proc_sp_decim_arr(i)))) & ")" + severity note; + + if sp_decim_err > 0.01 then + report "error: " & to_string(sp_decim_err) & " is too large (> 1%)!" + severity error; + else + report "error: " & to_string(sp_decim_err) & " is ok!" + severity note; + end if; + + expec_fofb_proc_sp_decim_arr(i) := 0.0; + end if; + end loop; + + -- checking decimated setpoints wishbone reading + report "checking decimated setpoints wishbone reading" + severity note; + + offs := c_WB_FOFB_PROCESSING_REGS_CH_0_SP_DECIM_DATA_ADDR - + c_WB_FOFB_PROCESSING_REGS_CH_0_ADDR; + for i in 0 to (g_CHANNELS - 1) + loop + addr := f_get_ch_reg_addr(offs, i); + + read32_pl(clk, wb_slave_i, wb_slave_o, addr, data); + + assert (data = std_logic_vector(sp_decim_arr(i))) + report + "wrong decimated setpoints wishbone reading at " & + natural'image(addr) + severity error; + + end loop; end loop; -- enabling loop interlock orbit distortion source @@ -1015,6 +1106,8 @@ begin bpm_time_frame_end_i => bpm_time_frame_end, sp_arr_o => sp_arr, sp_valid_arr_o => sp_valid_arr, + sp_decim_arr_o => sp_decim_arr, + sp_decim_valid_arr_o => sp_decim_valid_arr, wb_slv_i => wb_slave_i, wb_slv_o => wb_slave_o ); diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index dd83cdc3..09a23cd9 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -1757,6 +1757,8 @@ begin bpm_time_frame_end_i => fofb_proc_time_frame_end, sp_arr_o => fofb_sp_arr, sp_valid_arr_o => fofb_sp_valid_arr, + sp_decim_arr_o => open, + sp_decim_valid_arr_o => open, dcc_p2p_en_o => fofb_proc_dcc_p2p_en, wb_slv_i => user_wb_out(c_FOFB_PROCESSING_ID), wb_slv_o => user_wb_in(c_FOFB_PROCESSING_ID) From efb59b1e6f4656c91aafcd9b898d3d582749d1d8 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 30 Mar 2023 14:17:24 -0300 Subject: [PATCH 14/24] bpm_pos_flatenizer.vhd: add core This core stores serialized BPM positions and exposes a flat interface to access'em. Also add fofb_sys_id_pkg. --- hdl/modules/Manifest.py | 1 + hdl/modules/fofb_sys_id/Manifest.py | 4 + .../fofb_sys_id/bpm_pos_flatenizer.vhd | 111 ++++++++++++++++++ hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd | 50 ++++++++ 4 files changed, 166 insertions(+) create mode 100644 hdl/modules/fofb_sys_id/Manifest.py create mode 100644 hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd create mode 100644 hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd diff --git a/hdl/modules/Manifest.py b/hdl/modules/Manifest.py index 3210a35d..5201fcd9 100644 --- a/hdl/modules/Manifest.py +++ b/hdl/modules/Manifest.py @@ -3,5 +3,6 @@ modules = { "local": [ "fofb_ctrl_wrapper", "fofb_processing", + "fofb_sys_id" ] } diff --git a/hdl/modules/fofb_sys_id/Manifest.py b/hdl/modules/fofb_sys_id/Manifest.py new file mode 100644 index 00000000..2f4ddef1 --- /dev/null +++ b/hdl/modules/fofb_sys_id/Manifest.py @@ -0,0 +1,4 @@ +files = [ + "bpm_pos_flatenizer.vhd", + "fofb_sys_id_pkg.vhd" +] diff --git a/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd b/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd new file mode 100644 index 00000000..c2dd3597 --- /dev/null +++ b/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd @@ -0,0 +1,111 @@ +-------------------------------------------------------------------------------- +-- Title : BPM positions flatenizer +-- Project : fofb-ctrl-gw +-------------------------------------------------------------------------------- +-- File : bpm_pos_flatenizer.vhd +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Generic +-- Standard : VHDL'08 +-------------------------------------------------------------------------------- +-- Description: Stores serialized BPM positions and exposes a flat interface to +-- access'em. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-03-31 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.fofb_sys_id_pkg.all; +use work.dot_prod_pkg.all; + +entity bpm_pos_flatenizer is + generic ( + -- Maximum number of BPM positions to flatenize + g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16 + ); + port ( + -- Clock + clk_i : in std_logic; + + -- Reset + rst_n_i : in std_logic; + + -- Clear + -- This clears the stored BPM positions. + clear_i : in std_logic; + + -- BPM position base index + -- This, togheter with 'g_MAX_NUM_BPM_POS', defines the valid range of + -- indexes: + -- ['bpm_pos_base_index_i', 'bpm_pos_base_index_i' + 'g_MAX_NUM_BPM_POS'). + -- NOTE: Changing this will clear the stored BPM positions. + bpm_pos_base_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + + -- BPM position index + bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + + -- BPM position + bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + + -- BPM position valid + bpm_pos_valid_i : in std_logic; + + -- BPM positions flatenized + -- 'bpm_pos_flat_o(0)' -> BPM position index 'bpm_pos_base_index_i' + -- 'bpm_pos_flat_o(1)' -> BPM position index 'bpm_pos_base_index_i' + 1 + -- ..., and so on + bpm_pos_flat_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); + + -- Each bit indicates if the corresponding BPM position was received since + -- the last clearing (or resetting). This is useful for debugging. + bpm_pos_flat_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0) := (others => '0') + ); +end entity bpm_pos_flatenizer; + +architecture beh of bpm_pos_flatenizer is + signal bpm_pos_flat : t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); + signal bpm_pos_flat_rcvd : std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0) := (others => '0'); + signal bpm_pos_base_index_d1 : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); +begin + + process(clk_i) is + variable v_bpm_pos_rel_index : integer := 0; + begin + if rising_edge(clk_i) then + if rst_n_i = '0' or + bpm_pos_base_index_i /= bpm_pos_base_index_d1 or + clear_i = '1' then + bpm_pos_flat <= (others => (others => '0')); + bpm_pos_flat_rcvd <= (others => '0'); + else + if bpm_pos_valid_i = '1' then + v_bpm_pos_rel_index := to_integer(bpm_pos_index_i) - + to_integer(bpm_pos_base_index_i); + + -- Checks if BPM position index is within valid range + if v_bpm_pos_rel_index >= 0 and + v_bpm_pos_rel_index < g_MAX_NUM_BPM_POS then + bpm_pos_flat(v_bpm_pos_rel_index) <= bpm_pos_i; + bpm_pos_flat_rcvd(v_bpm_pos_rel_index) <= '1'; + end if; + end if; + end if; + + -- Registers bpm_pos_base_index_i so to check if it changes + bpm_pos_base_index_d1 <= bpm_pos_base_index_i; + end if; + end process; + + bpm_pos_flat_o <= bpm_pos_flat; + bpm_pos_flat_rcvd_o <= bpm_pos_flat_rcvd; + +end architecture beh; diff --git a/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd b/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd new file mode 100644 index 00000000..e232d72e --- /dev/null +++ b/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd @@ -0,0 +1,50 @@ +-------------------------------------------------------------------------------- +-- Title : FOFB system identification package +-- Project : fofb-ctrl-gw +-------------------------------------------------------------------------------- +-- File : fofb_sys_id_pkg.vhd +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Generic +-- Standard : VHDL'08 +-------------------------------------------------------------------------------- +-- Description: Package for FOFB system identification stuff. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-03-30 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.dot_prod_pkg.all; + +package fofb_sys_id_pkg is + + constant c_MAX_NUM_P2P_BPM_POS : natural := 16; + type t_bpm_pos_arr is array (natural range <>) of signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + + component bpm_pos_flatenizer is + generic ( + g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16 + ); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + clear_i : in std_logic; + bpm_pos_base_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + bpm_pos_valid_i : in std_logic; + bpm_pos_flat_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); + bpm_pos_flat_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0) := (others => '0') + ); + end component bpm_pos_flatenizer; + +end package fofb_sys_id_pkg; From 7c8d8ab22db7acb97bb094eb54a97526d5d045a7 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 31 Mar 2023 13:20:19 -0300 Subject: [PATCH 15/24] testbench/bpm_pos_flatenizer: add testbench --- hdl/testbench/bpm_pos_flatenizer/Manifest.py | 12 ++ .../bpm_pos_flatenizer_tb.vhd | 147 ++++++++++++++++++ .../bpm_pos_flatenizer/ghdl/.gitignore | 4 + .../bpm_pos_flatenizer/ghdl/Manifest.py | 11 ++ 4 files changed, 174 insertions(+) create mode 100644 hdl/testbench/bpm_pos_flatenizer/Manifest.py create mode 100644 hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd create mode 100644 hdl/testbench/bpm_pos_flatenizer/ghdl/.gitignore create mode 100644 hdl/testbench/bpm_pos_flatenizer/ghdl/Manifest.py diff --git a/hdl/testbench/bpm_pos_flatenizer/Manifest.py b/hdl/testbench/bpm_pos_flatenizer/Manifest.py new file mode 100644 index 00000000..78dda174 --- /dev/null +++ b/hdl/testbench/bpm_pos_flatenizer/Manifest.py @@ -0,0 +1,12 @@ +files = [ + "bpm_pos_flatenizer_tb.vhd", + "../fofb_tb_pkg.vhd", +] + +modules = { + "local" : [ + "../../ip_cores/general-cores", + "../../ip_cores/CommsCtrlFPGA", + "../../modules", + ], +} diff --git a/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd b/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd new file mode 100644 index 00000000..275727e1 --- /dev/null +++ b/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd @@ -0,0 +1,147 @@ +-------------------------------------------------------------------------------- +-- Title : BPM positions flatenizer testbench +-------------------------------------------------------------------------------- +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Simulation +-- Standard : VHDL 2008 +-------------------------------------------------------------------------------- +-- Description: Tests chaining fofb_processing_dcc_adapter with +-- bpm_pos_flatenizer. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-03-31 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.dot_prod_pkg.all; +use work.fofb_ctrl_pkg.all; +use work.fofb_tb_pkg.all; +use work.fofb_sys_id_pkg.all; + +entity bpm_pos_flatenizer_tb is +end bpm_pos_flatenizer_tb; + +architecture test of bpm_pos_flatenizer_tb is + constant c_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := c_MAX_NUM_P2P_BPM_POS/2; + signal clk : std_logic := '0'; + signal rst_n : std_logic := '0'; + signal clk_dcc : std_logic := '0'; + signal rst_dcc_n : std_logic := '0'; + signal dcc_time_frame_end : std_logic := '0'; + signal dcc_packet : t_fofb_cc_packet; + signal dcc_packet_valid : std_logic := '0'; + signal fofb_proc_bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + signal fofb_proc_bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal fofb_proc_bpm_pos_valid : std_logic; + signal fofb_proc_time_frame_end : std_logic; + signal clear : std_logic; + signal bpm_pos_base_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_flat : t_bpm_pos_arr(c_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); + signal bpm_pos_flat_rcvd : std_logic_vector(c_MAX_NUM_BPM_POS-1 downto 0) := (others => '0'); +begin + f_gen_clk(100_000_000, clk); + f_gen_clk(156_250_000, clk_dcc); + + process + variable v_BPM_POS_BASE_INDEX : natural := 0; + begin + f_wait_cycles(clk, 5); + rst_n <= '1'; + f_wait_cycles(clk_dcc, 5); + rst_dcc_n <= '1'; + + for cycle in 0 to 1 + loop + if cycle = 0 then + v_BPM_POS_BASE_INDEX := 20; + else + v_BPM_POS_BASE_INDEX := 70; + end if; + + bpm_pos_base_index <= to_unsigned(v_BPM_POS_BASE_INDEX, bpm_pos_base_index'length); + f_wait_cycles(clk, 10); + + -- Writes DCC packets with BPM positions matching their (to-be-)assigned + -- IDs. 'fofb_processing_dcc_adapter' serializes BPM positions and tags'em + -- using the following: + -- {BPM position x id, BPM position y id} = {BPM id, BPM id + 256}. + for id in 0 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)-1)-1 + loop + dcc_packet.bpm_data_x <= to_signed(id, dcc_packet.bpm_data_x'length); + dcc_packet.bpm_data_y <= to_signed(id + 256, dcc_packet.bpm_data_y'length); + dcc_packet.bpm_id <= to_unsigned(id, dcc_packet.bpm_id'length); + + dcc_packet_valid <= '1'; + f_wait_cycles(clk_dcc, 1); + dcc_packet_valid <= '0'; + f_wait_cycles(clk_dcc, 10); + end loop; + + for bpm_pos in 0 to c_MAX_NUM_BPM_POS-1 + loop + if bpm_pos_flat_rcvd(bpm_pos) /= '1' then + report "expected a bpm position stored" + severity failure; + end if; + + if to_integer(bpm_pos_flat(bpm_pos)) /= v_BPM_POS_BASE_INDEX + bpm_pos then + report + "wrong bpm position stored: " & + integer'image(to_integer(bpm_pos_flat(bpm_pos))) & " (expected: " & + integer'image(v_BPM_POS_BASE_INDEX + bpm_pos) & ")" + severity failure; + end if; + end loop; + + clear <= '1'; + f_wait_cycles(clk, 1); + clear <= '0'; + f_wait_cycles(clk, 1); + end loop; + + std.env.finish; + end process; + + inst_fofb_processing_dcc_adapter : fofb_processing_dcc_adapter + port map ( + clk_i => clk, + rst_n_i => rst_n, + clk_dcc_i => clk_dcc, + rst_dcc_n_i => rst_dcc_n, + dcc_time_frame_end_i => dcc_time_frame_end, + dcc_packet_i => dcc_packet, + dcc_packet_valid_i => dcc_packet_valid, + fofb_proc_busy_i => '0', + fofb_proc_bpm_pos_o => fofb_proc_bpm_pos, + fofb_proc_bpm_pos_index_o => fofb_proc_bpm_pos_index, + fofb_proc_bpm_pos_valid_o => fofb_proc_bpm_pos_valid, + fofb_proc_time_frame_end_o => fofb_proc_time_frame_end, + acq_dcc_packet_o => open, + acq_dcc_valid_o => open + ); + + uut : bpm_pos_flatenizer + generic map ( + g_MAX_NUM_BPM_POS => c_MAX_NUM_BPM_POS + ) + port map ( + clk_i => clk, + rst_n_i => rst_n, + clear_i => clear, + bpm_pos_base_index_i => bpm_pos_base_index, + bpm_pos_index_i => fofb_proc_bpm_pos_index, + bpm_pos_i => fofb_proc_bpm_pos, + bpm_pos_valid_i => fofb_proc_bpm_pos_valid, + bpm_pos_flat_o => bpm_pos_flat, + bpm_pos_flat_rcvd_o => bpm_pos_flat_rcvd + ); +end architecture test; diff --git a/hdl/testbench/bpm_pos_flatenizer/ghdl/.gitignore b/hdl/testbench/bpm_pos_flatenizer/ghdl/.gitignore new file mode 100644 index 00000000..5c5ee2ca --- /dev/null +++ b/hdl/testbench/bpm_pos_flatenizer/ghdl/.gitignore @@ -0,0 +1,4 @@ +bpm_pos_flatenizer_tb +bpm_pos_flatenizer_tb.ghw +*.cf +*.o diff --git a/hdl/testbench/bpm_pos_flatenizer/ghdl/Manifest.py b/hdl/testbench/bpm_pos_flatenizer/ghdl/Manifest.py new file mode 100644 index 00000000..26839b90 --- /dev/null +++ b/hdl/testbench/bpm_pos_flatenizer/ghdl/Manifest.py @@ -0,0 +1,11 @@ +action = "simulation" +sim_tool = "ghdl" +top_module = "bpm_pos_flatenizer_tb" +target = "xilinx" +syn_device = "xc7a200t" + +modules = {"local" : ["../"]} + +ghdl_opt = "--std=08 -frelaxed -fsynopsys -g" + +sim_post_cmd = "ghdl -r --std=08 %s --wave=%s.ghw --assert-level=error" % (top_module, top_module) From 603b83f286929023968790bef8d28d9fa4398dbd Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 3 Apr 2023 18:34:54 -0300 Subject: [PATCH 16/24] fofb_sys_id/cheby: add wishbone interface files This is a draft ABI designed for testing the acquisition machinery. --- hdl/modules/fofb_sys_id/Manifest.py | 1 + hdl/modules/fofb_sys_id/cheby/build_cheby.sh | 4 + .../cheby/wb_fofb_sys_id_regs.cheby | 32 ++++ .../fofb_sys_id/cheby/wb_fofb_sys_id_regs.h | 48 ++++++ .../fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd | 157 ++++++++++++++++++ .../regs/wb_fofb_sys_id_regs_consts_pkg.vhd | 7 + 6 files changed, 249 insertions(+) create mode 100755 hdl/modules/fofb_sys_id/cheby/build_cheby.sh create mode 100644 hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby create mode 100644 hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h create mode 100644 hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd create mode 100644 hdl/sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd diff --git a/hdl/modules/fofb_sys_id/Manifest.py b/hdl/modules/fofb_sys_id/Manifest.py index 2f4ddef1..6d999231 100644 --- a/hdl/modules/fofb_sys_id/Manifest.py +++ b/hdl/modules/fofb_sys_id/Manifest.py @@ -1,4 +1,5 @@ files = [ + "cheby/wb_fofb_sys_id_regs.vhd", "bpm_pos_flatenizer.vhd", "fofb_sys_id_pkg.vhd" ] diff --git a/hdl/modules/fofb_sys_id/cheby/build_cheby.sh b/hdl/modules/fofb_sys_id/cheby/build_cheby.sh new file mode 100755 index 00000000..155d16d4 --- /dev/null +++ b/hdl/modules/fofb_sys_id/cheby/build_cheby.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +mkdir -p doc +cheby -i wb_fofb_sys_id_regs.cheby --hdl vhdl --gen-hdl wb_fofb_sys_id_regs.vhd --doc html --gen-doc doc/wb_fofb_sys_id_regs.html --gen-c wb_fofb_sys_id_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd diff --git a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby new file mode 100644 index 00000000..d9b196ae --- /dev/null +++ b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby @@ -0,0 +1,32 @@ +memory-map: + bus: wb-32-be + name: wb_fofb_sys_id_regs + description: Interface to FOFB system identification regs + x-hdl: + busgroup: True + children: + - block: + name: bpm_pos_flatenizer + description: Interface to bpm_pos_flatenizer regs + address: 0x00000000 + children: + - reg: + name: max_num_cte + width: 16 + access: ro + address: next + description: | + Maximum number of BPM positions that can be flatenized per axis + - reg: + name: base_bpm_id + width: 8 + access: rw + address: next + description: | + Together with max_num_cte, defines the range of BPM position + indexes being flatenized, which is given by + [base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and + [base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y + positions. The valid range of this register is [0, 255]. + Note that only the P2P BPM positions are being driven to + flatenizer cores. diff --git a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h new file mode 100644 index 00000000..7a6a280f --- /dev/null +++ b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h @@ -0,0 +1,48 @@ +#ifndef __CHEBY__WB_FOFB_SYS_ID_REGS__H__ +#define __CHEBY__WB_FOFB_SYS_ID_REGS__H__ +#define WB_FOFB_SYS_ID_REGS_SIZE 8 /* 0x8 */ + +/* Interface to bpm_pos_flatenizer regs */ +#define WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER 0x0UL +#define WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_SIZE 8 /* 0x8 */ + +/* Maximum number of BPM positions that can be flatenized per axis + */ +#define WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_MAX_NUM_CTE 0x0UL + +/* Together with max_num_cte, defines the range of BPM position +indexes being flatenized, which is given by +[base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and +[base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y +positions. The valid range of this register is [0, 255]. +Note that only the P2P BPM positions are being driven to +flatenizer cores. + */ +#define WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_BASE_BPM_ID 0x4UL + +struct wb_fofb_sys_id_regs { + /* [0x0]: BLOCK Interface to bpm_pos_flatenizer regs */ + struct bpm_pos_flatenizer { + /* [0x0]: REG (ro) Maximum number of BPM positions that can be flatenized per axis + */ + uint16_t max_num_cte; + + /* padding to: 4 words */ + uint8_t __padding_0[2]; + + /* [0x4]: REG (rw) Together with max_num_cte, defines the range of BPM position +indexes being flatenized, which is given by +[base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and +[base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y +positions. The valid range of this register is [0, 255]. +Note that only the P2P BPM positions are being driven to +flatenizer cores. + */ + uint8_t base_bpm_id; + + /* padding to: 4 words */ + uint8_t __padding_1[3]; + } bpm_pos_flatenizer; +}; + +#endif /* __CHEBY__WB_FOFB_SYS_ID_REGS__H__ */ diff --git a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd new file mode 100644 index 00000000..dd788d07 --- /dev/null +++ b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd @@ -0,0 +1,157 @@ +-- Do not edit. Generated on Thu Apr 06 14:13:12 2023 by guilherme.ricioli +-- With Cheby 1.4.0 and these options: +-- -i wb_fofb_sys_id_regs.cheby --hdl vhdl --gen-hdl wb_fofb_sys_id_regs.vhd --doc html --gen-doc doc/wb_fofb_sys_id_regs.html --gen-c wb_fofb_sys_id_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_pkg.all; + +entity wb_fofb_sys_id_regs is + port ( + rst_n_i : in std_logic; + clk_i : in std_logic; + wb_i : in t_wishbone_slave_in; + wb_o : out t_wishbone_slave_out; + + -- Maximum number of BPM positions that can be flatenized per axis + + bpm_pos_flatenizer_max_num_cte_i : in std_logic_vector(15 downto 0); + + -- Together with max_num_cte, defines the range of BPM position + -- indexes being flatenized, which is given by + -- [base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and + -- [base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y + -- positions. The valid range of this register is [0, 255]. + -- Note that only the P2P BPM positions are being driven to + -- flatenizer cores. + + bpm_pos_flatenizer_base_bpm_id_o : out std_logic_vector(7 downto 0) + ); +end wb_fofb_sys_id_regs; + +architecture syn of wb_fofb_sys_id_regs is + signal adr_int : std_logic_vector(2 downto 2); + signal rd_req_int : std_logic; + signal wr_req_int : std_logic; + signal rd_ack_int : std_logic; + signal wr_ack_int : std_logic; + signal wb_en : std_logic; + signal ack_int : std_logic; + signal wb_rip : std_logic; + signal wb_wip : std_logic; + signal bpm_pos_flatenizer_base_bpm_id_reg : std_logic_vector(7 downto 0); + signal bpm_pos_flatenizer_base_bpm_id_wreq : std_logic; + signal bpm_pos_flatenizer_base_bpm_id_wack : std_logic; + signal rd_ack_d0 : std_logic; + signal rd_dat_d0 : std_logic_vector(31 downto 0); + signal wr_req_d0 : std_logic; + signal wr_adr_d0 : std_logic_vector(2 downto 2); + signal wr_dat_d0 : std_logic_vector(31 downto 0); + signal wr_sel_d0 : std_logic_vector(3 downto 0); +begin + + -- WB decode signals + adr_int <= wb_i.adr(2 downto 2); + wb_en <= wb_i.cyc and wb_i.stb; + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_rip <= '0'; + else + wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int; + end if; + end if; + end process; + rd_req_int <= (wb_en and not wb_i.we) and not wb_rip; + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_wip <= '0'; + else + wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int; + end if; + end if; + end process; + wr_req_int <= (wb_en and wb_i.we) and not wb_wip; + + ack_int <= rd_ack_int or wr_ack_int; + wb_o.ack <= ack_int; + wb_o.stall <= not ack_int and wb_en; + wb_o.rty <= '0'; + wb_o.err <= '0'; + + -- pipelining for wr-in+rd-out + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + rd_ack_int <= '0'; + wr_req_d0 <= '0'; + else + rd_ack_int <= rd_ack_d0; + wb_o.dat <= rd_dat_d0; + wr_req_d0 <= wr_req_int; + wr_adr_d0 <= adr_int; + wr_dat_d0 <= wb_i.dat; + wr_sel_d0 <= wb_i.sel; + end if; + end if; + end process; + + -- Register bpm_pos_flatenizer_max_num_cte + + -- Register bpm_pos_flatenizer_base_bpm_id + bpm_pos_flatenizer_base_bpm_id_o <= bpm_pos_flatenizer_base_bpm_id_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + bpm_pos_flatenizer_base_bpm_id_reg <= "00000000"; + bpm_pos_flatenizer_base_bpm_id_wack <= '0'; + else + if bpm_pos_flatenizer_base_bpm_id_wreq = '1' then + bpm_pos_flatenizer_base_bpm_id_reg <= wr_dat_d0(7 downto 0); + end if; + bpm_pos_flatenizer_base_bpm_id_wack <= bpm_pos_flatenizer_base_bpm_id_wreq; + end if; + end if; + end process; + + -- Process for write requests. + process (wr_adr_d0, wr_req_d0, bpm_pos_flatenizer_base_bpm_id_wack) begin + bpm_pos_flatenizer_base_bpm_id_wreq <= '0'; + case wr_adr_d0(2 downto 2) is + when "0" => + -- Reg bpm_pos_flatenizer_max_num_cte + wr_ack_int <= wr_req_d0; + when "1" => + -- Reg bpm_pos_flatenizer_base_bpm_id + bpm_pos_flatenizer_base_bpm_id_wreq <= wr_req_d0; + wr_ack_int <= bpm_pos_flatenizer_base_bpm_id_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + end process; + + -- Process for read requests. + process (adr_int, rd_req_int, bpm_pos_flatenizer_max_num_cte_i, bpm_pos_flatenizer_base_bpm_id_reg) begin + -- By default ack read requests + rd_dat_d0 <= (others => 'X'); + case adr_int(2 downto 2) is + when "0" => + -- Reg bpm_pos_flatenizer_max_num_cte + rd_ack_d0 <= rd_req_int; + rd_dat_d0(15 downto 0) <= bpm_pos_flatenizer_max_num_cte_i; + rd_dat_d0(31 downto 16) <= (others => '0'); + when "1" => + -- Reg bpm_pos_flatenizer_base_bpm_id + rd_ack_d0 <= rd_req_int; + rd_dat_d0(7 downto 0) <= bpm_pos_flatenizer_base_bpm_id_reg; + rd_dat_d0(31 downto 8) <= (others => '0'); + when others => + rd_ack_d0 <= rd_req_int; + end case; + end process; +end syn; diff --git a/hdl/sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd new file mode 100644 index 00000000..89aacb2d --- /dev/null +++ b/hdl/sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd @@ -0,0 +1,7 @@ +package wb_fofb_sys_id_regs_consts_pkg is + constant c_WB_FOFB_SYS_ID_REGS_SIZE : Natural := 8; + constant c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_SIZE : Natural := 8; + constant c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_MAX_NUM_CTE_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_BASE_BPM_ID_ADDR : Natural := 16#4#; +end package wb_fofb_sys_id_regs_consts_pkg; From 7a374235cb6af53cc433e2f19269b7bf8c0ebc35 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 4 Apr 2023 15:01:43 -0300 Subject: [PATCH 17/24] xwb_fofb_sys_id.vhd: add core This core instantiates FOFB system identification cores and exposes some of their signals on a wishbone bus. FOFB_SYS_ID_REGS has SDB version major number "0" because it's a draft ABI (we're following this convention from now on). --- hdl/modules/fofb_ctrl_pkg.vhd | 41 ++++ hdl/modules/fofb_sys_id/Manifest.py | 1 + hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd | 214 ++++++++++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index a0331be2..aa69665f 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -6,6 +6,7 @@ library work; use work.fofb_cc_pkg.all; use work.wishbone_pkg.all; use work.dot_prod_pkg.all; +use work.fofb_sys_id_pkg.all; package fofb_ctrl_pkg is @@ -596,6 +597,29 @@ package fofb_ctrl_pkg is ); end component; + component xwb_fofb_sys_id is + generic ( + g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16; + g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; + g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; + g_WITH_EXTRA_WB_REG : boolean := false + ); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + bpm_pos_valid_i : in std_logic; + bpm_pos_flat_clear_i : in std_logic; + bpm_pos_flat_x_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0); + bpm_pos_flat_x_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0); + bpm_pos_flat_y_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0); + bpm_pos_flat_y_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0); + wb_slv_i : in t_wishbone_slave_in; + wb_slv_o : out t_wishbone_slave_out + ); + end component; + component fofb_processing_dcc_adapter is generic ( -- DCC packet FIFO depth @@ -687,6 +711,23 @@ package fofb_ctrl_pkg is date => x"20230215", name => "FOFB_PROC_REGS "))); + -- FOFB system identification + constant c_xwb_fofb_sys_id_regs_sdb : t_sdb_device := ( + abi_class => x"0000", -- undocumented device + abi_ver_major => x"00", + abi_ver_minor => x"00", + wbd_endian => c_sdb_endian_big, + wbd_width => x"4", -- 32-bit port granularity (0100) + sdb_component => ( + addr_first => x"0000000000000000", + addr_last => x"000000000000FFFF", + product => ( + vendor_id => x"1000000000001215", -- LNLS + device_id => x"4b2f4872", -- Last 8 chars of "FOFB_SYS_ID_REGS" md5sum + version => x"00000001", + date => x"20230404", + name => "FOFB_SYS_ID_REGS "))); + end fofb_ctrl_pkg; package body fofb_ctrl_pkg is diff --git a/hdl/modules/fofb_sys_id/Manifest.py b/hdl/modules/fofb_sys_id/Manifest.py index 6d999231..ce2c3380 100644 --- a/hdl/modules/fofb_sys_id/Manifest.py +++ b/hdl/modules/fofb_sys_id/Manifest.py @@ -1,5 +1,6 @@ files = [ "cheby/wb_fofb_sys_id_regs.vhd", "bpm_pos_flatenizer.vhd", + "xwb_fofb_sys_id.vhd", "fofb_sys_id_pkg.vhd" ] diff --git a/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd b/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd new file mode 100644 index 00000000..38a73eb1 --- /dev/null +++ b/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd @@ -0,0 +1,214 @@ +-------------------------------------------------------------------------------- +-- Title : Wrapper for FOFB system identification cores +-- Project : fofb-ctrl-gw +-------------------------------------------------------------------------------- +-- File : xwb_fofb_sys_id.vhd +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Generic +-- Standard : VHDL'08 +-------------------------------------------------------------------------------- +-- Description: Instantiates FOFB system identification cores and exposes some +-- of their signals on a wishbone bus. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-04-04 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.wishbone_pkg.all; +use work.dot_prod_pkg.all; +use work.fofb_sys_id_pkg.all; + +entity xwb_fofb_sys_id is + generic ( + -- Maximum number of BPM positions to flatenize + g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16; + + -- Wishbone generics + g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; + g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; + g_WITH_EXTRA_WB_REG : boolean := false + ); + port ( + -- Clock + clk_i : in std_logic; + + -- Reset + rst_n_i : in std_logic; + + -- BPM position + bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + + -- BPM position index + bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + + -- BPM position valid + bpm_pos_valid_i : in std_logic; + + -- BPM flatenized positions clear + -- This clears the stored BPM positions. + bpm_pos_flat_clear_i : in std_logic; + + -- BPM positions flatenized (instance x) + bpm_pos_flat_x_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0); + + -- Each bit indicates if the corresponding BPM position was received since + -- the last clearing (or resetting). This is useful for debugging. (instance x) + bpm_pos_flat_x_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0); + + -- BPM positions flatenized (instance y) + bpm_pos_flat_y_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0); + + -- Each bit indicates if the corresponding BPM position was received since + -- the last clearing (or resetting). This is useful for debugging. (instance y) + bpm_pos_flat_y_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0); + + -- Wishbone interface + wb_slv_i : in t_wishbone_slave_in; + wb_slv_o : out t_wishbone_slave_out + ); +end xwb_fofb_sys_id; + +architecture beh of xwb_fofb_sys_id is + + -- Number of bits in Wishbone register interface; plus 2 to account for BYTE addressing. + constant c_PERIPH_ADDR_SIZE : natural := 2+2; + + signal bpm_pos_flatenizer_base_bpm_id : std_logic_vector(7 downto 0); + + -- Wishbone signals + signal wb_slv_adp_out : t_wishbone_master_out; + signal wb_slv_adp_in : t_wishbone_master_in; + signal resized_addr : std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0); + + -- Extra wishbone registering stage signals + signal wb_slave_in : t_wishbone_slave_in_array(0 downto 0); + signal wb_slave_out : t_wishbone_slave_out_array(0 downto 0); + signal wb_slave_in_reg0 : t_wishbone_slave_in_array(0 downto 0); + signal wb_slave_out_reg0 : t_wishbone_slave_out_array(0 downto 0); + +begin + -- BPM positions x flatenizer + cmp_x_bpm_pos_flatenizer : bpm_pos_flatenizer + generic map ( + g_MAX_NUM_BPM_POS => g_MAX_NUM_BPM_POS + ) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + clear_i => bpm_pos_flat_clear_i, + -- The associated index is the same as the DCC packet BPM ID which + -- contains it (ranges from 0 to 255). + bpm_pos_base_index_i => '0' & unsigned(bpm_pos_flatenizer_base_bpm_id), + bpm_pos_index_i => bpm_pos_index_i, + bpm_pos_i => bpm_pos_i, + bpm_pos_valid_i => bpm_pos_valid_i, + bpm_pos_flat_o => bpm_pos_flat_x_o, + bpm_pos_flat_rcvd_o => bpm_pos_flat_x_rcvd_o + ); + + -- BPM positions y flatenizer + cmp_y_bpm_pos_flatenizer : bpm_pos_flatenizer + generic map ( + g_MAX_NUM_BPM_POS => g_MAX_NUM_BPM_POS + ) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + clear_i => bpm_pos_flat_clear_i, + -- The associated index is the same as the DCC packet BPM ID which + -- contains it + 256 (ranges from 256 to 511). + bpm_pos_base_index_i => '1' & unsigned(bpm_pos_flatenizer_base_bpm_id), + bpm_pos_index_i => bpm_pos_index_i, + bpm_pos_i => bpm_pos_i, + bpm_pos_valid_i => bpm_pos_valid_i, + bpm_pos_flat_o => bpm_pos_flat_y_o, + bpm_pos_flat_rcvd_o => bpm_pos_flat_y_rcvd_o + ); + + cmp_wb_fofb_sys_id_regs : entity work.wb_fofb_sys_id_regs + port map ( + rst_n_i => rst_n_i, + clk_i => clk_i, + wb_i => wb_slv_adp_out, + wb_o => wb_slv_adp_in, + bpm_pos_flatenizer_max_num_cte_i => std_logic_vector(to_unsigned(g_MAX_NUM_BPM_POS, 16)), + bpm_pos_flatenizer_base_bpm_id_o => bpm_pos_flatenizer_base_bpm_id + ); + + -- Extra wishbone registering stage for ease timing + -- NOTE: It effectively cuts the bandwidth in half! + gen_with_extra_wb_reg : if g_WITH_EXTRA_WB_REG generate + cmp_register_link : xwb_register_link -- puts a register of delay between crossbars + port map ( + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + slave_i => wb_slave_in_reg0(0), + slave_o => wb_slave_out_reg0(0), + master_i => wb_slave_out(0), + master_o => wb_slave_in(0) + ); + + wb_slave_in_reg0(0) <= wb_slv_i; + wb_slv_o <= wb_slave_out_reg0(0); + else generate + -- External master connection + wb_slave_in(0) <= wb_slv_i; + wb_slv_o <= wb_slave_out(0); + end generate; + + -- Wishbone slave adapter + cmp_slave_adapter : wb_slave_adapter + generic map ( + g_MASTER_USE_STRUCT => true, + g_MASTER_MODE => PIPELINED, + -- TODO: it seems that using cheby without wbgen compatibility requires + -- g_MASTER_GRANULARITY to be byte + g_MASTER_GRANULARITY => BYTE, + g_SLAVE_USE_STRUCT => false, + g_SLAVE_MODE => g_INTERFACE_MODE, + g_SLAVE_GRANULARITY => g_ADDRESS_GRANULARITY + ) + port map ( + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + master_i => wb_slv_adp_in, + master_o => wb_slv_adp_out, + sl_adr_i => resized_addr, + sl_dat_i => wb_slave_in(0).dat, + sl_sel_i => wb_slave_in(0).sel, + sl_cyc_i => wb_slave_in(0).cyc, + sl_stb_i => wb_slave_in(0).stb, + sl_we_i => wb_slave_in(0).we, + sl_dat_o => wb_slave_out(0).dat, + sl_ack_o => wb_slave_out(0).ack, + sl_rty_o => wb_slave_out(0).rty, + sl_err_o => wb_slave_out(0).err, + sl_stall_o => wb_slave_out(0).stall + ); + + gen_wb_slave_in_addr_conn : if g_ADDRESS_GRANULARITY = WORD generate + -- By doing this zeroing we avoid the issue related to BYTE -> WORD + -- conversion slave addressing (possibly performed by the slave adapter + -- component) in which a bit in the MSB of the peripheral addressing part + -- (31 downto c_PERIPH_ADDR_SIZE in our case) is shifted to the internal + -- register adressing part (c_PERIPH_ADDR_SIZE-1 downto 0 in our case). + -- Therefore, possibly changing the these bits! + resized_addr(c_PERIPH_ADDR_SIZE-1 downto 0) + <= wb_slave_in(0).adr(c_PERIPH_ADDR_SIZE-1 downto 0); + resized_addr(c_WISHBONE_ADDRESS_WIDTH-1 downto c_PERIPH_ADDR_SIZE) + <= (others => '0'); + else generate + resized_addr <= wb_slave_in(0).adr; + end generate; + +end architecture beh; From fb4955a1a50c196c6caf94e67ae969e4a153359a Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 4 Apr 2023 15:06:54 -0300 Subject: [PATCH 18/24] xwb_fofb_sys_id_tb.vhd: add testbench --- hdl/testbench/xwb_fofb_sys_id/Manifest.py | 14 ++ hdl/testbench/xwb_fofb_sys_id/ghdl/.gitignore | 4 + .../xwb_fofb_sys_id/ghdl/Manifest.py | 11 + .../xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd | 217 ++++++++++++++++++ 4 files changed, 246 insertions(+) create mode 100644 hdl/testbench/xwb_fofb_sys_id/Manifest.py create mode 100644 hdl/testbench/xwb_fofb_sys_id/ghdl/.gitignore create mode 100644 hdl/testbench/xwb_fofb_sys_id/ghdl/Manifest.py create mode 100644 hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd diff --git a/hdl/testbench/xwb_fofb_sys_id/Manifest.py b/hdl/testbench/xwb_fofb_sys_id/Manifest.py new file mode 100644 index 00000000..b5433ddf --- /dev/null +++ b/hdl/testbench/xwb_fofb_sys_id/Manifest.py @@ -0,0 +1,14 @@ +files = [ + "xwb_fofb_sys_id_tb.vhd", + "../../ip_cores/general-cores/sim/vhdl/sim_wishbone.vhd", + "../../sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd", + "../fofb_tb_pkg.vhd", +] + +modules = { + "local" : [ + "../../ip_cores/general-cores", + "../../ip_cores/CommsCtrlFPGA", + "../../modules", + ], +} diff --git a/hdl/testbench/xwb_fofb_sys_id/ghdl/.gitignore b/hdl/testbench/xwb_fofb_sys_id/ghdl/.gitignore new file mode 100644 index 00000000..97010a38 --- /dev/null +++ b/hdl/testbench/xwb_fofb_sys_id/ghdl/.gitignore @@ -0,0 +1,4 @@ +xwb_fofb_sys_id_tb +xwb_fofb_sys_id_tb.ghw +*.o +*.cf diff --git a/hdl/testbench/xwb_fofb_sys_id/ghdl/Manifest.py b/hdl/testbench/xwb_fofb_sys_id/ghdl/Manifest.py new file mode 100644 index 00000000..eaddb3fe --- /dev/null +++ b/hdl/testbench/xwb_fofb_sys_id/ghdl/Manifest.py @@ -0,0 +1,11 @@ +action = "simulation" +sim_tool = "ghdl" +top_module = "xwb_fofb_sys_id_tb" +target = "xilinx" +syn_device = "xc7a200t" + +modules = {"local" : ["../"]} + +ghdl_opt = "--std=08 -frelaxed" + +sim_post_cmd = "ghdl -r --std=08 %s --wave=%s.ghw --assert-level=error"% (top_module, top_module) diff --git a/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd b/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd new file mode 100644 index 00000000..16d63bc0 --- /dev/null +++ b/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd @@ -0,0 +1,217 @@ +-------------------------------------------------------------------------------- +-- Title : Wrapper for FOFB system identification cores testbench +-------------------------------------------------------------------------------- +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Simulation +-- Standard : VHDL 2008 +-------------------------------------------------------------------------------- +-- Description: Tests the wishbone inteface and wrapped cores. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-04-05 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library std; +use std.env.finish; +use std.textio.all; + +library work; +use work.wishbone_pkg.all; +use work.fofb_ctrl_pkg.all; +use work.dot_prod_pkg.all; +use work.fofb_sys_id_pkg.all; +use work.wb_fofb_sys_id_regs_consts_pkg.all; +use work.sim_wishbone.all; +use work.fofb_tb_pkg.all; + +entity xwb_fofb_sys_id_tb is +end entity xwb_fofb_sys_id_tb; + +architecture test of xwb_fofb_sys_id_tb is + constant c_SYS_CLOCK_FREQ : natural := 100_000_000; + + -- Maximum number of BPM positions to flatenize + -- Each bpm_pos_flatenizer holds half of c_MAX_NUM_P2P_BPM_POS. + constant c_MAX_NUM_BPM_POS : + natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := + c_MAX_NUM_P2P_BPM_POS/2; + + -- DCC packet base BPM id + constant c_BPM_ID_BASE : natural := 20; + constant c_BPM_POS_FLATENIZER_BASE_BPM_ID : + std_logic_vector(31 downto 0) := + std_logic_vector(to_unsigned(c_BPM_ID_BASE, 32)); + + signal clk : std_logic := '0'; + signal rst_n : std_logic := '0'; + signal bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + signal bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal bpm_pos_valid : std_logic := '0'; + signal bpm_pos_flat_clear : std_logic := '0'; + signal bpm_pos_flat_x : t_bpm_pos_arr(c_MAX_NUM_BPM_POS-1 downto 0); + signal bpm_pos_flat_x_rcvd : std_logic_vector(c_MAX_NUM_BPM_POS-1 downto 0); + signal bpm_pos_flat_y : t_bpm_pos_arr(c_MAX_NUM_BPM_POS-1 downto 0); + signal bpm_pos_flat_y_rcvd : std_logic_vector(c_MAX_NUM_BPM_POS-1 downto 0); + + -- Wishbone signals + signal wb_slave_i : t_wishbone_slave_in; + signal wb_slave_o : t_wishbone_slave_out; + +begin + f_gen_clk(c_SYS_CLOCK_FREQ, clk); + + process + variable addr : natural := 0; + variable offs : natural := 0; + variable data : std_logic_vector(31 downto 0) := + (others => '0'); + begin + init(wb_slave_i); + f_wait_cycles(clk, 10); + + -- Resetting cores + rst_n <= '0'; + f_wait_cycles(clk, 1); + rst_n <= '1'; + f_wait_cycles(clk, 10); + + -- Reads back the maximum number of BPMs positions supported by flatenizers + read32_pl(clk, wb_slave_i, wb_slave_o, + c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_MAX_NUM_CTE_ADDR, data); + assert (to_integer(unsigned(data)) = c_MAX_NUM_BPM_POS) + report + "Unexpected maximum number of BPMs positions supported by flatenizers: " + & natural'image(to_integer(unsigned(data))) & " (expected: " & + natural'image(c_MAX_NUM_BPM_POS) & ")" + severity error; + + -- Writes base BPM id + write32_pl(clk, wb_slave_i, wb_slave_o, + c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_BASE_BPM_ID_ADDR, + c_BPM_POS_FLATENIZER_BASE_BPM_ID); + + -- Reads back base BPM id + read32_pl(clk, wb_slave_i, wb_slave_o, + c_WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_BASE_BPM_ID_ADDR, data); + assert (data = c_BPM_POS_FLATENIZER_BASE_BPM_ID) + report "Unexpected base BPM id: " & to_hstring(data) & " (expected: " & + to_hstring(c_BPM_POS_FLATENIZER_BASE_BPM_ID) & ")" + severity error; + + -- Drives BPM positions with the same value of their assigned IDs + for bpm_pos_id in 0 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH))-1 + loop + bpm_pos <= to_signed(bpm_pos_id, bpm_pos'length); + bpm_pos_index <= to_unsigned(bpm_pos_id, bpm_pos_index'length); + + bpm_pos_valid <= '1'; + f_wait_cycles(clk, 1); + bpm_pos_valid <= '0'; + f_wait_cycles(clk, 10); + end loop; + + for bpm_pos_flat_idx in 0 to c_MAX_NUM_BPM_POS-1 + loop + -- Asserts bpm_pos_flat_x_rcvd + assert (bpm_pos_flat_x_rcvd(bpm_pos_flat_idx) = '1') + report "Expected BPM position stored on bpm_pos_flat_x index " & + natural'image(bpm_pos_flat_idx) + severity error; + + -- Asserts bpm_pos_flat_x + assert (to_integer(bpm_pos_flat_x(bpm_pos_flat_idx)) = + c_BPM_ID_BASE + bpm_pos_flat_idx) + report "Unexpected BPM position value on bpm_pos_flat_x: " & + integer'image(to_integer(bpm_pos_flat_x(bpm_pos_flat_idx))) & + " (expected: " & + integer'image(c_BPM_ID_BASE + bpm_pos_flat_idx) & ")" + severity error; + + -- Asserts bpm_pos_flat_y_rcvd + assert (bpm_pos_flat_y_rcvd(bpm_pos_flat_idx) = '1') + report "Expected BPM position stored on bpm_pos_flat_y index " & + natural'image(bpm_pos_flat_idx) + severity error; + + -- Asserts bpm_pos_flat_y + assert (to_integer(bpm_pos_flat_y(bpm_pos_flat_idx)) = + c_BPM_ID_BASE + 256 + bpm_pos_flat_idx) + report "Unexpected BPM position value on bpm_pos_flat_y: " & + integer'image(to_integer(bpm_pos_flat_y(bpm_pos_flat_idx))) & + " (expected: " & + integer'image(c_BPM_ID_BASE + 256 + bpm_pos_flat_idx) & ")" + severity error; + end loop; + + -- Clears flatenizers + bpm_pos_flat_clear <= '1'; + f_wait_cycles(clk, 1); + bpm_pos_flat_clear <= '0'; + f_wait_cycles(clk, 1); + + for bpm_pos_flat_idx in 0 to c_MAX_NUM_BPM_POS-1 + loop + -- Asserts bpm_pos_flat_x_rcvd + assert (bpm_pos_flat_x_rcvd(bpm_pos_flat_idx) = '0') + report "Unexpected BPM position stored on bpm_pos_flat_x index " & + natural'image(bpm_pos_flat_idx) & " after clearing it" + severity error; + + -- Asserts bpm_pos_flat_x + assert (to_integer(bpm_pos_flat_x(bpm_pos_flat_idx)) = 0) + report "Unexpected BPM position value on bpm_pos_flat_x after " & + "clearing it: " & + integer'image(to_integer(bpm_pos_flat_x(bpm_pos_flat_idx))) + severity error; + + -- Asserts bpm_pos_flat_y_rcvd + assert (bpm_pos_flat_y_rcvd(bpm_pos_flat_idx) = '0') + report "Unexpected BPM position stored on bpm_pos_flat_y index " & + natural'image(bpm_pos_flat_idx) & " after clearing it" + severity error; + + -- Asserts bpm_pos_flat_y + assert (to_integer(bpm_pos_flat_y(bpm_pos_flat_idx)) = 0) + report "Unexpected BPM position value on bpm_pos_flat_y after " & + "clearing it: " & + integer'image(to_integer(bpm_pos_flat_x(bpm_pos_flat_idx))) + severity error; + end loop; + + report "success!" + severity note; + + finish; + end process; + + uut : xwb_fofb_sys_id + generic map ( + g_MAX_NUM_BPM_POS => c_MAX_NUM_BPM_POS, + g_INTERFACE_MODE => PIPELINED, + g_ADDRESS_GRANULARITY => BYTE, + g_WITH_EXTRA_WB_REG => false + ) + port map ( + clk_i => clk, + rst_n_i => rst_n, + bpm_pos_i => bpm_pos, + bpm_pos_index_i => bpm_pos_index, + bpm_pos_valid_i => bpm_pos_valid, + bpm_pos_flat_clear_i => bpm_pos_flat_clear, + bpm_pos_flat_x_o => bpm_pos_flat_x, + bpm_pos_flat_x_rcvd_o => bpm_pos_flat_x_rcvd, + bpm_pos_flat_y_o => bpm_pos_flat_y, + bpm_pos_flat_y_rcvd_o => bpm_pos_flat_y_rcvd, + wb_slv_i => wb_slave_i, + wb_slv_o => wb_slave_o + ); +end architecture test; From 66510bd581669c5512fb65be0efa9fc55105c89b Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 10 Apr 2023 12:31:22 -0300 Subject: [PATCH 19/24] afc_ref_fofb_ctrl_gen.vhd: instantiate sys id core Instantiate xwb_fofb_sys_id core, which will be used for system identification purposes. This core allows applying disturbances both on BPMs readings and corrector setpoints. --- .../afc_ref_fofb_ctrl_gen.vhd | 36 +++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 09a23cd9..f16eba8c 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -53,6 +53,8 @@ use work.pcie_cntr_axi_pkg.all; use work.fofb_ctrl_pkg.all; -- FOFC CC use work.fofb_cc_pkg.all; +-- FOFB sys id +use work.fofb_sys_id_pkg.all; -- RTM LAMP definitions use work.rtm_lamp_pkg.all; -- Dot product package @@ -787,7 +789,9 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_FOFB_CC_P2P_ID : natural := 1; constant c_RTM_LAMP_ID : natural := 2; constant c_FOFB_PROCESSING_ID : natural := 3; - constant c_USER_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + 1; + constant c_FOFB_SYS_ID_ID : natural := 4; + -- +2 for accounting for FOFB processing and FOFB system identification cores + constant c_USER_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + 2; constant c_RTM_LAMP_SDB : boolean := (g_RTM = "RTMLAMP"); constant c_USER_SDB_RECORD_ARRAY : t_sdb_record_array(c_USER_NUM_CORES-1 downto 0) := @@ -795,7 +799,8 @@ architecture top of afc_ref_fofb_ctrl_gen is c_FOFB_CC_FMC_OR_RTM_ID => f_sdb_auto_device(c_xwb_fofb_cc_regs_sdb, true), c_FOFB_CC_P2P_ID => f_sdb_auto_device(c_xwb_fofb_cc_regs_sdb, true), c_RTM_LAMP_ID => f_sdb_auto_device(c_xwb_rtm_lamp_regs_sdb, c_RTM_LAMP_SDB), - c_FOFB_PROCESSING_ID => f_sdb_auto_device(c_xwb_fofb_processing_regs_sdb, true) + c_FOFB_PROCESSING_ID => f_sdb_auto_device(c_xwb_fofb_processing_regs_sdb, true), + c_FOFB_SYS_ID_ID => f_sdb_auto_device(c_xwb_fofb_sys_id_regs_sdb, true) ); ----------------------------------------------------------------------------- @@ -1764,6 +1769,33 @@ begin wb_slv_o => user_wb_in(c_FOFB_PROCESSING_ID) ); + ---------------------------------------------------------------------- + -- FOFB SYSTEM IDENTIFICATION -- + ---------------------------------------------------------------------- + + cmp_xwb_fofb_sys_id: xwb_fofb_sys_id + generic map ( + g_MAX_NUM_BPM_POS => c_MAX_NUM_P2P_BPM_POS/2, + g_INTERFACE_MODE => PIPELINED, + g_ADDRESS_GRANULARITY => BYTE, + g_WITH_EXTRA_WB_REG => false + ) + port map ( + clk_i => clk_sys, + rst_n_i => clk_sys_rstn, + bpm_pos_i => fofb_proc_bpm_pos, + bpm_pos_index_i => fofb_proc_bpm_pos_index, + bpm_pos_valid_i => fofb_proc_bpm_pos_valid, + bpm_pos_flat_clear_i => or fofb_sp_valid_arr, + -- TODO: connect on acq channel + bpm_pos_flat_x_o => open, + bpm_pos_flat_x_rcvd_o => open, + bpm_pos_flat_y_o => open, + bpm_pos_flat_y_rcvd_o => open, + wb_slv_i => user_wb_out(c_FOFB_SYS_ID_ID), + wb_slv_o => user_wb_in(c_FOFB_SYS_ID_ID) + ); + ---------------------------------------------------------------------- -- RTM 8SFP OHWR -- ---------------------------------------------------------------------- From 6c160d92bcdac2c64a86db4fa959dff2247d278f Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 10 Apr 2023 12:55:23 -0300 Subject: [PATCH 20/24] afc_ref_fofb_ctrl_gen.vhd: add sys id channel to acq cores --- hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index f16eba8c..c84a399b 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -701,9 +701,10 @@ architecture top of afc_ref_fofb_ctrl_gen is -- is unused and connecting it to the xwb_rtmlamp_ohwr external trigger input. constant c_SP_TRIG_RTM_LAMP_ID : natural := 3; constant c_ACQ_DCC_ID : natural := 1; + constant c_ACQ_SYS_ID_ID : natural := 2; -- Number of channels per acquisition core - constant c_ACQ_NUM_CHANNELS : natural := 2; + constant c_ACQ_NUM_CHANNELS : natural := 3; constant c_FACQ_PARAMS_RTM_LAMP : t_facq_chan_param := ( width => to_unsigned(512, c_ACQ_CHAN_CMPLT_WIDTH_LOG2), @@ -717,10 +718,17 @@ architecture top of afc_ref_fofb_ctrl_gen is atom_width => to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2) ); + constant c_FACQ_PARAMS_SYS_ID : t_facq_chan_param := ( + width => to_unsigned(768, c_ACQ_CHAN_CMPLT_WIDTH_LOG2), + num_atoms => to_unsigned(24, c_ACQ_NUM_ATOMS_WIDTH_LOG2), + atom_width => to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2) + ); + constant c_FACQ_CHANNELS : t_facq_chan_param_array(c_ACQ_NUM_CHANNELS-1 downto 0) := ( c_ACQ_RTM_LAMP_ID => c_FACQ_PARAMS_RTM_LAMP, - c_ACQ_DCC_ID => c_FACQ_PARAMS_DCC + c_ACQ_DCC_ID => c_FACQ_PARAMS_DCC, + c_ACQ_SYS_ID_ID => c_FACQ_PARAMS_SYS_ID ); signal acq_chan_array : t_facq_chan_array2d(c_ACQ_NUM_CORES-1 downto 0, c_ACQ_NUM_CHANNELS-1 downto 0); From 56c3a95a884838cd7a161bfbb62a010bd2361860 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 10 Apr 2023 14:27:56 -0300 Subject: [PATCH 21/24] afc_ref_fofb_ctrl_gen.vhd: instantiate sys id acq/trig mux cores --- .../afc_ref_fofb_ctrl_gen.vhd | 50 ++++++++++++++++--- 1 file changed, 43 insertions(+), 7 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index c84a399b..293ab91d 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -424,6 +424,9 @@ architecture top of afc_ref_fofb_ctrl_gen is -- FOFB CC constant c_NUM_FOFC_CC_CORES : natural := 2; + -- SYS ID + constant c_NUM_SYS_ID_CORES : natural := 1; + constant c_BPMS : integer := 1; constant c_FAI_DW : integer := 16; constant c_DMUX : integer := 2; @@ -469,6 +472,15 @@ architecture top of afc_ref_fofb_ctrl_gen is signal acq_dcc_fmc_packet : t_fofb_cc_packet; signal acq_dcc_fmc_valid : std_logic := '0'; + ----------------------------------------------------------------------------- + -- FOFB system identification signals + ----------------------------------------------------------------------------- + + signal bpm_pos_flat_x : t_bpm_pos_arr(c_MAX_NUM_P2P_BPM_POS/2-1 downto 0); + signal bpm_pos_flat_x_rcvd : std_logic_vector(c_MAX_NUM_P2P_BPM_POS/2-1 downto 0); + signal bpm_pos_flat_y : t_bpm_pos_arr(c_MAX_NUM_P2P_BPM_POS/2-1 downto 0); + signal bpm_pos_flat_y_rcvd : std_logic_vector(c_MAX_NUM_P2P_BPM_POS/2-1 downto 0); + ----------------------------------------------------------------------------- -- RTM signals ----------------------------------------------------------------------------- @@ -675,13 +687,14 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_ACQ_FIFO_SIZE : natural := 256; - -- Number of acquisition cores. Same as the number of DCC - constant c_ACQ_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES; + -- Number of acquisition cores + constant c_ACQ_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + c_NUM_SYS_ID_CORES; -- Acquisition core IDs constant c_ACQ_CORE_RTM_LAMP_ID : natural := 0; constant c_ACQ_CORE_CC_FMC_OR_RTM_ID : natural := 1; constant c_ACQ_CORE_CC_P2P_ID : natural := 2; + constant c_ACQ_CORE_SYS_ID_ID : natural := 3; -- Type of DDR3 core interface constant c_DDR_INTERFACE_TYPE : string := "AXIS"; @@ -758,6 +771,7 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_TRIG_MUX_RTM_LAMP_ID : natural := c_ACQ_CORE_RTM_LAMP_ID; constant c_TRIG_MUX_CC_FMC_ID : natural := c_ACQ_CORE_CC_FMC_OR_RTM_ID; constant c_TRIG_MUX_CC_P2P_ID : natural := c_ACQ_CORE_CC_P2P_ID; + constant c_TRIG_MUX_SYS_ID_ID : natural := c_ACQ_CORE_SYS_ID_ID; constant c_TRIG_MUX_NUM_CORES : natural := c_ACQ_NUM_CORES; @@ -1795,11 +1809,10 @@ begin bpm_pos_index_i => fofb_proc_bpm_pos_index, bpm_pos_valid_i => fofb_proc_bpm_pos_valid, bpm_pos_flat_clear_i => or fofb_sp_valid_arr, - -- TODO: connect on acq channel - bpm_pos_flat_x_o => open, - bpm_pos_flat_x_rcvd_o => open, - bpm_pos_flat_y_o => open, - bpm_pos_flat_y_rcvd_o => open, + bpm_pos_flat_x_o => bpm_pos_flat_x, + bpm_pos_flat_x_rcvd_o => bpm_pos_flat_x_rcvd, + bpm_pos_flat_y_o => bpm_pos_flat_y, + bpm_pos_flat_y_rcvd_o => bpm_pos_flat_y_rcvd, wb_slv_i => user_wb_out(c_FOFB_SYS_ID_ID), wb_slv_o => user_wb_in(c_FOFB_SYS_ID_ID) ); @@ -2124,6 +2137,9 @@ begin fs_clk_array(c_ACQ_CORE_RTM_LAMP_ID) <= clk_sys; fs_rst_n_array(c_ACQ_CORE_RTM_LAMP_ID) <= clk_sys_rstn; + fs_clk_array(c_ACQ_CORE_SYS_ID_ID) <= clk_sys; + fs_rst_n_array(c_ACQ_CORE_SYS_ID_ID) <= clk_sys_rstn; + gen_acq_clks : for i in 0 to c_ACQ_NUM_CORES-1 generate fs_ce_array(i) <= '1'; @@ -2191,6 +2207,26 @@ begin acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).dvalid <= fofb_fod_dat_val(c_FOFB_CC_P2P_ID)(0); acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_CC_P2P_ID, c_ACQ_DCC_ID).pulse; + -------------------- + -- ACQ Core 4 + -------------------- + + -- SYS ID + acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).val(to_integer(c_FACQ_CHANNELS(c_ACQ_SYS_ID_ID).width)-1 downto 0) <= + std_logic_vector(bpm_pos_flat_x(7)) & std_logic_vector(bpm_pos_flat_x(6)) & std_logic_vector(bpm_pos_flat_x(5)) & std_logic_vector(bpm_pos_flat_x(4)) & -- BPM x positions (767 downto 512, 8x32) + std_logic_vector(bpm_pos_flat_x(3)) & std_logic_vector(bpm_pos_flat_x(2)) & std_logic_vector(bpm_pos_flat_x(1)) & std_logic_vector(bpm_pos_flat_x(0)) & + std_logic_vector(bpm_pos_flat_y(7)) & std_logic_vector(bpm_pos_flat_y(6)) & std_logic_vector(bpm_pos_flat_y(5)) & std_logic_vector(bpm_pos_flat_y(4)) & -- BPM y positions (511 downto 256, 8x32) + std_logic_vector(bpm_pos_flat_y(3)) & std_logic_vector(bpm_pos_flat_y(2)) & std_logic_vector(bpm_pos_flat_y(1)) & std_logic_vector(bpm_pos_flat_y(0)) & + -- TODO: These bits should be filled with channels 11-8, but they aren't instantiated yet + std_logic_vector(to_unsigned(0, 64)) & -- FOFB setpoints (255 downto 64, 12x16) + std_logic_vector(fofb_sp_arr(7)) & std_logic_vector(fofb_sp_arr(6)) & std_logic_vector(fofb_sp_arr(5)) & std_logic_vector(fofb_sp_arr(4)) & + std_logic_vector(fofb_sp_arr(3)) & std_logic_vector(fofb_sp_arr(2)) & std_logic_vector(fofb_sp_arr(1)) & std_logic_vector(fofb_sp_arr(0)) & + bpm_pos_flat_x_rcvd & bpm_pos_flat_y_rcvd & -- [DEBUG] Flatenizers' 'received' flag (64 downto 49, 2x8) + f_fofb_cc_packet_to_slv(acq_dcc_fmc_packet)(def_PacketTimeframeCntr16MSB downto def_PacketTimeframeCntr16LSB) & -- [DEBUG] Timeframe counter (49 downto 33, 1x16) + std_logic_vector(to_unsigned(0, 32)); + acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).dvalid <= or fofb_sp_valid_arr; + acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_SYS_ID_ID, c_ACQ_SYS_ID_ID).pulse; + ---------------------------------------------------------------------- -- Trigger -- ---------------------------------------------------------------------- From f12460f26796a1a98fc243c85dc27fdd9d72d5f4 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 13 Apr 2023 09:51:57 -0300 Subject: [PATCH 22/24] afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds 1. Changed FOFB sys id channel width from 768 to 1024 as a workaround for the bug described on [1]; 2. Swapped each 2 16-bit FOFB processing setpoints so they end up being allocated on RAM in descending order after ACQ endianness procedures. 3. Repositioned the acquired signals to keep consistency with other ACQ cores. [1] https://github.com/lnls-dig/infra-cores/issues/18 --- .../afc_ref_fofb_ctrl_gen.vhd | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 293ab91d..949cae3e 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -732,8 +732,11 @@ architecture top of afc_ref_fofb_ctrl_gen is ); constant c_FACQ_PARAMS_SYS_ID : t_facq_chan_param := ( - width => to_unsigned(768, c_ACQ_CHAN_CMPLT_WIDTH_LOG2), - num_atoms => to_unsigned(24, c_ACQ_NUM_ATOMS_WIDTH_LOG2), + -- NOTE: Altough 768 bits would be enough, using this value as width somehow + -- causes ACQ samples to be weirdly misaligned (see https://github.com/lnls-dig/infra-cores/issues/18). + -- This issue isn't manifested when we use 1024 bits. + width => to_unsigned(1024, c_ACQ_CHAN_CMPLT_WIDTH_LOG2), + num_atoms => to_unsigned(32, c_ACQ_NUM_ATOMS_WIDTH_LOG2), atom_width => to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2) ); @@ -2213,17 +2216,18 @@ begin -- SYS ID acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).val(to_integer(c_FACQ_CHANNELS(c_ACQ_SYS_ID_ID).width)-1 downto 0) <= - std_logic_vector(bpm_pos_flat_x(7)) & std_logic_vector(bpm_pos_flat_x(6)) & std_logic_vector(bpm_pos_flat_x(5)) & std_logic_vector(bpm_pos_flat_x(4)) & -- BPM x positions (767 downto 512, 8x32) - std_logic_vector(bpm_pos_flat_x(3)) & std_logic_vector(bpm_pos_flat_x(2)) & std_logic_vector(bpm_pos_flat_x(1)) & std_logic_vector(bpm_pos_flat_x(0)) & - std_logic_vector(bpm_pos_flat_y(7)) & std_logic_vector(bpm_pos_flat_y(6)) & std_logic_vector(bpm_pos_flat_y(5)) & std_logic_vector(bpm_pos_flat_y(4)) & -- BPM y positions (511 downto 256, 8x32) - std_logic_vector(bpm_pos_flat_y(3)) & std_logic_vector(bpm_pos_flat_y(2)) & std_logic_vector(bpm_pos_flat_y(1)) & std_logic_vector(bpm_pos_flat_y(0)) & + std_logic_vector(to_unsigned(0, 288)) & -- [DEBUG] Padding with 0s (1023 downto 736) + bpm_pos_flat_x_rcvd & bpm_pos_flat_y_rcvd & -- [DEBUG] Flatenizers' 'received' flag (735 downto 720, 2x8) + f_fofb_cc_packet_to_slv(acq_dcc_fmc_packet)(def_PacketTimeframeCntr16MSB downto def_PacketTimeframeCntr16LSB) & -- [DEBUG] Timeframe counter (719 downto 704, 1x16) -- TODO: These bits should be filled with channels 11-8, but they aren't instantiated yet - std_logic_vector(to_unsigned(0, 64)) & -- FOFB setpoints (255 downto 64, 12x16) - std_logic_vector(fofb_sp_arr(7)) & std_logic_vector(fofb_sp_arr(6)) & std_logic_vector(fofb_sp_arr(5)) & std_logic_vector(fofb_sp_arr(4)) & - std_logic_vector(fofb_sp_arr(3)) & std_logic_vector(fofb_sp_arr(2)) & std_logic_vector(fofb_sp_arr(1)) & std_logic_vector(fofb_sp_arr(0)) & - bpm_pos_flat_x_rcvd & bpm_pos_flat_y_rcvd & -- [DEBUG] Flatenizers' 'received' flag (64 downto 49, 2x8) - f_fofb_cc_packet_to_slv(acq_dcc_fmc_packet)(def_PacketTimeframeCntr16MSB downto def_PacketTimeframeCntr16LSB) & -- [DEBUG] Timeframe counter (49 downto 33, 1x16) - std_logic_vector(to_unsigned(0, 32)); + std_logic_vector(to_unsigned(0, 64)) & -- FOFB channels setpoints 11-0 (703 downto 512, 12x16) + -- NOTE: These 16-bit values are being swapped at each 2 so they end up being allocated on RAM in descending order after ACQ endianness procedures. + std_logic_vector(fofb_sp_arr(6)) & std_logic_vector(fofb_sp_arr(7)) & std_logic_vector(fofb_sp_arr(4)) & std_logic_vector(fofb_sp_arr(5)) & + std_logic_vector(fofb_sp_arr(2)) & std_logic_vector(fofb_sp_arr(3)) & std_logic_vector(fofb_sp_arr(0)) & std_logic_vector(fofb_sp_arr(1)) & + std_logic_vector(bpm_pos_flat_y(7)) & std_logic_vector(bpm_pos_flat_y(6)) & std_logic_vector(bpm_pos_flat_y(5)) & std_logic_vector(bpm_pos_flat_y(4)) & -- P2P BPM y positions 7-0 (511 downto 256, 8x32) + std_logic_vector(bpm_pos_flat_y(3)) & std_logic_vector(bpm_pos_flat_y(2)) & std_logic_vector(bpm_pos_flat_y(1)) & std_logic_vector(bpm_pos_flat_y(0)) & + std_logic_vector(bpm_pos_flat_x(7)) & std_logic_vector(bpm_pos_flat_x(6)) & std_logic_vector(bpm_pos_flat_x(5)) & std_logic_vector(bpm_pos_flat_x(4)) & -- P2P BPM x positions 7-0 (255 downto 0, 8x32) + std_logic_vector(bpm_pos_flat_x(3)) & std_logic_vector(bpm_pos_flat_x(2)) & std_logic_vector(bpm_pos_flat_x(1)) & std_logic_vector(bpm_pos_flat_x(0)); acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).dvalid <= or fofb_sp_valid_arr; acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_SYS_ID_ID, c_ACQ_SYS_ID_ID).pulse; From 31571b8e6d878597b0057486ec28a8f9ebf69cd9 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 17 Apr 2023 17:41:07 -0300 Subject: [PATCH 23/24] bpm_pos_flatenizer_tb: fix improper usage of consts Only define constants for constraining arrays of arrays and use generics for interface widths. --- hdl/modules/fofb_ctrl_pkg.vhd | 4 +++- hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd | 17 +++++++++++------ hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd | 14 +++++++++----- hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd | 14 ++++++++++++-- .../bpm_pos_flatenizer_tb.vhd | 15 +++++++++------ .../xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd | 2 ++ .../afc_ref_fofb_ctrl_gen.vhd | 2 ++ 7 files changed, 48 insertions(+), 20 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index aa69665f..eebf1432 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -599,7 +599,9 @@ package fofb_ctrl_pkg is component xwb_fofb_sys_id is generic ( - g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16; + g_BPM_POS_INDEX_WIDTH : natural := 9; + g_BPM_POS_WIDTH : natural := c_BPM_POS_WIDTH; + g_MAX_NUM_BPM_POS : natural := c_MAX_NUM_P2P_BPM_POS/2; g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; g_WITH_EXTRA_WB_REG : boolean := false diff --git a/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd b/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd index c2dd3597..756403aa 100644 --- a/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd +++ b/hdl/modules/fofb_sys_id/bpm_pos_flatenizer.vhd @@ -25,12 +25,17 @@ use ieee.numeric_std.all; library work; use work.fofb_sys_id_pkg.all; -use work.dot_prod_pkg.all; entity bpm_pos_flatenizer is generic ( + -- Width of BPM position indexes + g_BPM_POS_INDEX_WIDTH : natural := 9; + + -- Width of BPM positions + g_BPM_POS_WIDTH : natural := c_BPM_POS_WIDTH; + -- Maximum number of BPM positions to flatenize - g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16 + g_MAX_NUM_BPM_POS : natural := c_MAX_NUM_P2P_BPM_POS/2 ); port ( -- Clock @@ -48,13 +53,13 @@ entity bpm_pos_flatenizer is -- indexes: -- ['bpm_pos_base_index_i', 'bpm_pos_base_index_i' + 'g_MAX_NUM_BPM_POS'). -- NOTE: Changing this will clear the stored BPM positions. - bpm_pos_base_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + bpm_pos_base_index_i : in unsigned(g_BPM_POS_INDEX_WIDTH-1 downto 0); -- BPM position index - bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + bpm_pos_index_i : in unsigned(g_BPM_POS_INDEX_WIDTH-1 downto 0); -- BPM position - bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + bpm_pos_i : in signed(g_BPM_POS_WIDTH-1 downto 0); -- BPM position valid bpm_pos_valid_i : in std_logic; @@ -74,7 +79,7 @@ end entity bpm_pos_flatenizer; architecture beh of bpm_pos_flatenizer is signal bpm_pos_flat : t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); signal bpm_pos_flat_rcvd : std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0) := (others => '0'); - signal bpm_pos_base_index_d1 : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_base_index_d1 : unsigned(g_BPM_POS_INDEX_WIDTH-1 downto 0) := (others => '0'); begin process(clk_i) is diff --git a/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd b/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd index e232d72e..9d7f60df 100644 --- a/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd +++ b/hdl/modules/fofb_sys_id/fofb_sys_id_pkg.vhd @@ -28,19 +28,23 @@ use work.dot_prod_pkg.all; package fofb_sys_id_pkg is constant c_MAX_NUM_P2P_BPM_POS : natural := 16; - type t_bpm_pos_arr is array (natural range <>) of signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + + constant c_BPM_POS_WIDTH : natural := c_SP_POS_RAM_DATA_WIDTH; + type t_bpm_pos_arr is array (natural range <>) of signed(c_BPM_POS_WIDTH-1 downto 0); component bpm_pos_flatenizer is generic ( - g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16 + g_BPM_POS_INDEX_WIDTH : natural := 9; + g_BPM_POS_WIDTH : natural := c_BPM_POS_WIDTH; + g_MAX_NUM_BPM_POS : natural := c_MAX_NUM_P2P_BPM_POS/2 ); port ( clk_i : in std_logic; rst_n_i : in std_logic; clear_i : in std_logic; - bpm_pos_base_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); - bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); - bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + bpm_pos_base_index_i : in unsigned(g_BPM_POS_INDEX_WIDTH-1 downto 0); + bpm_pos_index_i : in unsigned(g_BPM_POS_INDEX_WIDTH-1 downto 0); + bpm_pos_i : in signed(g_BPM_POS_WIDTH-1 downto 0); bpm_pos_valid_i : in std_logic; bpm_pos_flat_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); bpm_pos_flat_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0) := (others => '0') diff --git a/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd b/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd index 38a73eb1..9142cd42 100644 --- a/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd +++ b/hdl/modules/fofb_sys_id/xwb_fofb_sys_id.vhd @@ -30,8 +30,14 @@ use work.fofb_sys_id_pkg.all; entity xwb_fofb_sys_id is generic ( + -- Width of BPM position indexes + g_BPM_POS_INDEX_WIDTH : natural := 9; + + -- Width of BPM positions + g_BPM_POS_WIDTH : natural := c_BPM_POS_WIDTH; + -- Maximum number of BPM positions to flatenize - g_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := 16; + g_MAX_NUM_BPM_POS : natural := c_MAX_NUM_P2P_BPM_POS/2; -- Wishbone generics g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; @@ -46,7 +52,7 @@ entity xwb_fofb_sys_id is rst_n_i : in std_logic; -- BPM position - bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); + bpm_pos_i : in signed(c_BPM_POS_WIDTH-1 downto 0); -- BPM position index bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); @@ -100,6 +106,8 @@ begin -- BPM positions x flatenizer cmp_x_bpm_pos_flatenizer : bpm_pos_flatenizer generic map ( + g_BPM_POS_INDEX_WIDTH => g_BPM_POS_INDEX_WIDTH, + g_BPM_POS_WIDTH => g_BPM_POS_WIDTH, g_MAX_NUM_BPM_POS => g_MAX_NUM_BPM_POS ) port map ( @@ -119,6 +127,8 @@ begin -- BPM positions y flatenizer cmp_y_bpm_pos_flatenizer : bpm_pos_flatenizer generic map ( + g_BPM_POS_INDEX_WIDTH => g_BPM_POS_INDEX_WIDTH, + g_BPM_POS_WIDTH => g_BPM_POS_WIDTH, g_MAX_NUM_BPM_POS => g_MAX_NUM_BPM_POS ) port map ( diff --git a/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd b/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd index 275727e1..802d601f 100644 --- a/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd +++ b/hdl/testbench/bpm_pos_flatenizer/bpm_pos_flatenizer_tb.vhd @@ -22,7 +22,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.dot_prod_pkg.all; use work.fofb_ctrl_pkg.all; use work.fofb_tb_pkg.all; use work.fofb_sys_id_pkg.all; @@ -31,7 +30,9 @@ entity bpm_pos_flatenizer_tb is end bpm_pos_flatenizer_tb; architecture test of bpm_pos_flatenizer_tb is - constant c_MAX_NUM_BPM_POS : natural range 1 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)) := c_MAX_NUM_P2P_BPM_POS/2; + constant c_BPM_POS_INDEX_WIDTH : natural := 9; + constant c_MAX_NUM_BPM_POS : natural := c_MAX_NUM_P2P_BPM_POS/2; + signal clk : std_logic := '0'; signal rst_n : std_logic := '0'; signal clk_dcc : std_logic := '0'; @@ -39,12 +40,12 @@ architecture test of bpm_pos_flatenizer_tb is signal dcc_time_frame_end : std_logic := '0'; signal dcc_packet : t_fofb_cc_packet; signal dcc_packet_valid : std_logic := '0'; - signal fofb_proc_bpm_pos : signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0); - signal fofb_proc_bpm_pos_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0); + signal fofb_proc_bpm_pos : signed(c_BPM_POS_WIDTH-1 downto 0); + signal fofb_proc_bpm_pos_index : unsigned(c_BPM_POS_INDEX_WIDTH-1 downto 0); signal fofb_proc_bpm_pos_valid : std_logic; signal fofb_proc_time_frame_end : std_logic; signal clear : std_logic; - signal bpm_pos_base_index : unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal bpm_pos_base_index : unsigned(c_BPM_POS_INDEX_WIDTH-1 downto 0) := (others => '0'); signal bpm_pos_flat : t_bpm_pos_arr(c_MAX_NUM_BPM_POS-1 downto 0) := (others => (others => '0')); signal bpm_pos_flat_rcvd : std_logic_vector(c_MAX_NUM_BPM_POS-1 downto 0) := (others => '0'); begin @@ -74,7 +75,7 @@ begin -- IDs. 'fofb_processing_dcc_adapter' serializes BPM positions and tags'em -- using the following: -- {BPM position x id, BPM position y id} = {BPM id, BPM id + 256}. - for id in 0 to 2**(natural(c_SP_COEFF_RAM_ADDR_WIDTH)-1)-1 + for id in 0 to 2**(c_BPM_POS_INDEX_WIDTH-1)-1 loop dcc_packet.bpm_data_x <= to_signed(id, dcc_packet.bpm_data_x'length); dcc_packet.bpm_data_y <= to_signed(id + 256, dcc_packet.bpm_data_y'length); @@ -131,6 +132,8 @@ begin uut : bpm_pos_flatenizer generic map ( + g_BPM_POS_INDEX_WIDTH => c_BPM_POS_INDEX_WIDTH, + g_BPM_POS_WIDTH => c_BPM_POS_WIDTH, g_MAX_NUM_BPM_POS => c_MAX_NUM_BPM_POS ) port map ( diff --git a/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd b/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd index 16d63bc0..ea1f9d98 100644 --- a/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd +++ b/hdl/testbench/xwb_fofb_sys_id/xwb_fofb_sys_id_tb.vhd @@ -195,6 +195,8 @@ begin uut : xwb_fofb_sys_id generic map ( + g_BPM_POS_INDEX_WIDTH => 9, + g_BPM_POS_WIDTH => c_BPM_POS_WIDTH, g_MAX_NUM_BPM_POS => c_MAX_NUM_BPM_POS, g_INTERFACE_MODE => PIPELINED, g_ADDRESS_GRANULARITY => BYTE, diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 949cae3e..d591f162 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -1800,6 +1800,8 @@ begin cmp_xwb_fofb_sys_id: xwb_fofb_sys_id generic map ( + g_BPM_POS_INDEX_WIDTH => c_SP_COEFF_RAM_ADDR_WIDTH, + g_BPM_POS_WIDTH => c_SP_POS_RAM_DATA_WIDTH, g_MAX_NUM_BPM_POS => c_MAX_NUM_P2P_BPM_POS/2, g_INTERFACE_MODE => PIPELINED, g_ADDRESS_GRANULARITY => BYTE, From 6ede5704de42ad555a2885a0fbb37375561761c9 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 20 Apr 2023 09:21:26 -0300 Subject: [PATCH 24/24] wb_fofb_sys_id_regs,*: remove improper note All BPM positions are being driven to flatenizers (not only P2P ones). --- hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby | 2 -- hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h | 4 ---- hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd | 4 +--- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby index d9b196ae..96bc242e 100644 --- a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby +++ b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.cheby @@ -28,5 +28,3 @@ memory-map: [base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and [base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y positions. The valid range of this register is [0, 255]. - Note that only the P2P BPM positions are being driven to - flatenizer cores. diff --git a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h index 7a6a280f..0e43d91a 100644 --- a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h +++ b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.h @@ -15,8 +15,6 @@ indexes being flatenized, which is given by [base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and [base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y positions. The valid range of this register is [0, 255]. -Note that only the P2P BPM positions are being driven to -flatenizer cores. */ #define WB_FOFB_SYS_ID_REGS_BPM_POS_FLATENIZER_BASE_BPM_ID 0x4UL @@ -35,8 +33,6 @@ indexes being flatenized, which is given by [base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and [base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y positions. The valid range of this register is [0, 255]. -Note that only the P2P BPM positions are being driven to -flatenizer cores. */ uint8_t base_bpm_id; diff --git a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd index dd788d07..615e51e7 100644 --- a/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd +++ b/hdl/modules/fofb_sys_id/cheby/wb_fofb_sys_id_regs.vhd @@ -1,4 +1,4 @@ --- Do not edit. Generated on Thu Apr 06 14:13:12 2023 by guilherme.ricioli +-- Do not edit. Generated on Thu Apr 20 09:20:28 2023 by guilherme.ricioli -- With Cheby 1.4.0 and these options: -- -i wb_fofb_sys_id_regs.cheby --hdl vhdl --gen-hdl wb_fofb_sys_id_regs.vhd --doc html --gen-doc doc/wb_fofb_sys_id_regs.html --gen-c wb_fofb_sys_id_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_sys_id_regs_consts_pkg.vhd @@ -24,8 +24,6 @@ entity wb_fofb_sys_id_regs is -- [base_bpm_id, base_bpm_id + max_num_cte) -> BPM x positions; and -- [base_bpm_id + 256, base_bpm_id + 256 + max_num_cte) -> BPM y -- positions. The valid range of this register is [0, 255]. - -- Note that only the P2P BPM positions are being driven to - -- flatenizer cores. bpm_pos_flatenizer_base_bpm_id_o : out std_logic_vector(7 downto 0) );