From 52fe5357edde2b160cec4bc09686bbd8e153f1a6 Mon Sep 17 00:00:00 2001 From: Melissa Aguiar Date: Tue, 19 Oct 2021 12:03:57 -0300 Subject: [PATCH 1/2] fofb_processing/cheby: register definition files changed --- hdl/modules/fofb_processing/Manifest.py | 2 +- .../fofb_processing/cheby/build_cheby.sh | 2 +- .../fofb_processing/cheby/dot_prod_wb.h | 26 -- .../fofb_processing/cheby/dot_prod_wb.vhd | 241 ------------------ ...wb.cheby => wb_fofb_processing_regs.cheby} | 8 +- .../cheby/wb_fofb_processing_regs.h | 26 ++ .../cheby/wb_fofb_processing_regs.vhd | 241 ++++++++++++++++++ .../fofb_processing/wb_fofb_processing.vhd | 16 +- hdl/sim/regs/wb_fofb_processing_regs.vh | 6 + 9 files changed, 287 insertions(+), 281 deletions(-) delete mode 100644 hdl/modules/fofb_processing/cheby/dot_prod_wb.h delete mode 100644 hdl/modules/fofb_processing/cheby/dot_prod_wb.vhd rename hdl/modules/fofb_processing/cheby/{dot_prod_wb.cheby => wb_fofb_processing_regs.cheby} (79%) create mode 100644 hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h create mode 100644 hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd create mode 100644 hdl/sim/regs/wb_fofb_processing_regs.vh diff --git a/hdl/modules/fofb_processing/Manifest.py b/hdl/modules/fofb_processing/Manifest.py index 4829b91f..9eb6c7c9 100644 --- a/hdl/modules/fofb_processing/Manifest.py +++ b/hdl/modules/fofb_processing/Manifest.py @@ -3,7 +3,7 @@ "dot_prod_coeff_vec.vhd", "dot_prod.vhd", "dot_prod_pkg.vhd", - "cheby/dot_prod_wb.vhd", + "cheby/wb_fofb_processing_regs.vhd", "wb_fofb_processing.vhd", "xwb_fofb_processing.vhd" ]; diff --git a/hdl/modules/fofb_processing/cheby/build_cheby.sh b/hdl/modules/fofb_processing/cheby/build_cheby.sh index 689f3777..6b0f4aae 100755 --- a/hdl/modules/fofb_processing/cheby/build_cheby.sh +++ b/hdl/modules/fofb_processing/cheby/build_cheby.sh @@ -1,3 +1,3 @@ #!/bin/bash -cheby -i dot_prod_wb.cheby --hdl vhdl --gen-wbgen-hdl dot_prod_wb.vhd --doc html --gen-doc doc/dot_prod_wb.html --gen-c dot_prod_wb.h --consts-style verilog --gen-consts ../../../sim/regs/dot_prod_wb.vh +cheby -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_fofb_processing_regs.vhd --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh diff --git a/hdl/modules/fofb_processing/cheby/dot_prod_wb.h b/hdl/modules/fofb_processing/cheby/dot_prod_wb.h deleted file mode 100644 index 234263c1..00000000 --- a/hdl/modules/fofb_processing/cheby/dot_prod_wb.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __CHEBY__DOT_PROD_WB__H__ -#define __CHEBY__DOT_PROD_WB__H__ -#define DOT_PROD_WB_SIZE 12 /* 0xc */ - -/* None */ -#define DOT_PROD_WB_RAM_COEFF_DAT 0x0UL - -/* None */ -#define DOT_PROD_WB_RAM_COEFF_ADDR 0x4UL - -/* None */ -#define DOT_PROD_WB_RAM_WRITE 0x8UL -#define DOT_PROD_WB_RAM_WRITE_ENABLE 0x1UL - -struct dot_prod_wb { - /* [0x0]: REG (rw) (no description) */ - uint32_t ram_coeff_dat; - - /* [0x4]: REG (rw) (no description) */ - uint32_t ram_coeff_addr; - - /* [0x8]: REG (rw) (no description) */ - uint32_t ram_write; -}; - -#endif /* __CHEBY__DOT_PROD_WB__H__ */ diff --git a/hdl/modules/fofb_processing/cheby/dot_prod_wb.vhd b/hdl/modules/fofb_processing/cheby/dot_prod_wb.vhd deleted file mode 100644 index e0671960..00000000 --- a/hdl/modules/fofb_processing/cheby/dot_prod_wb.vhd +++ /dev/null @@ -1,241 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Wishbone slave core for interface to memory -------------------------------------------------------------------------------- --- File : dot_prod_wb.vhdl --- Author : auto-generated by wbgen2 from dot_prod_wb.wb --- Created : Thu Aug 26 20:48:36 2021 --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dot_prod_wb.wb --- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity dot_prod_wb is - port ( - rst_n_i : in std_logic; - clk_sys_i : in std_logic; - wb_adr_i : in std_logic_vector(1 downto 0); - wb_dat_i : in std_logic_vector(31 downto 0); - wb_dat_o : out std_logic_vector(31 downto 0); - wb_cyc_i : in std_logic; - wb_sel_i : in std_logic_vector(3 downto 0); - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_ack_o : out std_logic; - wb_stall_o : out std_logic; - dot_prod_clk_reg_i : in std_logic; - -- Port for asynchronous (clock: dot_prod_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - dot_prod_wb_ram_coeff_dat_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: dot_prod_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - dot_prod_wb_ram_coeff_addr_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: dot_prod_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' - dot_prod_wb_ram_write_enable_o : out std_logic - ); -end dot_prod_wb; - -architecture syn of dot_prod_wb is - - signal dot_prod_wb_ram_coeff_dat_int : std_logic_vector(31 downto 0); - signal dot_prod_wb_ram_coeff_dat_swb : std_logic; - signal dot_prod_wb_ram_coeff_dat_swb_delay : std_logic; - signal dot_prod_wb_ram_coeff_dat_swb_s0 : std_logic; - signal dot_prod_wb_ram_coeff_dat_swb_s1 : std_logic; - signal dot_prod_wb_ram_coeff_dat_swb_s2 : std_logic; - signal dot_prod_wb_ram_coeff_addr_int : std_logic_vector(31 downto 0); - signal dot_prod_wb_ram_coeff_addr_swb : std_logic; - signal dot_prod_wb_ram_coeff_addr_swb_delay : std_logic; - signal dot_prod_wb_ram_coeff_addr_swb_s0 : std_logic; - signal dot_prod_wb_ram_coeff_addr_swb_s1 : std_logic; - signal dot_prod_wb_ram_coeff_addr_swb_s2 : std_logic; - signal dot_prod_wb_ram_write_enable_int : std_logic; - signal dot_prod_wb_ram_write_enable_int_delay : std_logic; - signal dot_prod_wb_ram_write_enable_sync0 : std_logic; - signal dot_prod_wb_ram_write_enable_sync1 : std_logic; - signal dot_prod_wb_ram_write_enable_sync2 : std_logic; - signal ack_sreg : std_logic_vector(9 downto 0); - signal rddata_reg : std_logic_vector(31 downto 0); - signal wrdata_reg : std_logic_vector(31 downto 0); - signal bwsel_reg : std_logic_vector(3 downto 0); - signal rwaddr_reg : std_logic_vector(1 downto 0); - signal ack_in_progress : std_logic; - signal wr_int : std_logic; - signal rd_int : std_logic; - signal allones : std_logic_vector(31 downto 0); - signal allzeros : std_logic_vector(31 downto 0); - -begin - -- Some internal signals assignments. For (foreseen) compatibility with other bus standards. - wrdata_reg <= wb_dat_i; - bwsel_reg <= wb_sel_i; - rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); - wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); - allones <= (others => '1'); - allzeros <= (others => '0'); - -- - -- Main register bank access process. - process (clk_sys_i, rst_n_i) - begin - if (rst_n_i = '0') then - ack_sreg <= "0000000000"; - ack_in_progress <= '0'; - rddata_reg <= "00000000000000000000000000000000"; - dot_prod_wb_ram_coeff_dat_int <= "00000000000000000000000000000000"; - dot_prod_wb_ram_coeff_dat_swb <= '0'; - dot_prod_wb_ram_coeff_dat_swb_delay <= '0'; - dot_prod_wb_ram_coeff_addr_int <= "00000000000000000000000000000000"; - dot_prod_wb_ram_coeff_addr_swb <= '0'; - dot_prod_wb_ram_coeff_addr_swb_delay <= '0'; - dot_prod_wb_ram_write_enable_int <= '0'; - dot_prod_wb_ram_write_enable_int_delay <= '0'; - elsif rising_edge(clk_sys_i) then - -- advance the ACK generator shift register - ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); - ack_sreg(9) <= '0'; - if (ack_in_progress = '1') then - if (ack_sreg(0) = '1') then - ack_in_progress <= '0'; - else - dot_prod_wb_ram_coeff_dat_swb <= dot_prod_wb_ram_coeff_dat_swb_delay; - dot_prod_wb_ram_coeff_dat_swb_delay <= '0'; - dot_prod_wb_ram_coeff_addr_swb <= dot_prod_wb_ram_coeff_addr_swb_delay; - dot_prod_wb_ram_coeff_addr_swb_delay <= '0'; - dot_prod_wb_ram_write_enable_int <= dot_prod_wb_ram_write_enable_int_delay; - dot_prod_wb_ram_write_enable_int_delay <= '0'; - end if; - else - if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then - case rwaddr_reg(1 downto 0) is - when "00" => - if (wb_we_i = '1') then - dot_prod_wb_ram_coeff_dat_int <= wrdata_reg(31 downto 0); - dot_prod_wb_ram_coeff_dat_swb <= '1'; - dot_prod_wb_ram_coeff_dat_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= dot_prod_wb_ram_coeff_dat_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "01" => - if (wb_we_i = '1') then - dot_prod_wb_ram_coeff_addr_int <= wrdata_reg(31 downto 0); - dot_prod_wb_ram_coeff_addr_swb <= '1'; - dot_prod_wb_ram_coeff_addr_swb_delay <= '1'; - end if; - rddata_reg(31 downto 0) <= dot_prod_wb_ram_coeff_addr_int; - ack_sreg(3) <= '1'; - ack_in_progress <= '1'; - when "10" => - if (wb_we_i = '1') then - dot_prod_wb_ram_write_enable_int <= wrdata_reg(0); - dot_prod_wb_ram_write_enable_int_delay <= wrdata_reg(0); - end if; - rddata_reg(0) <= '0'; - rddata_reg(0) <= 'X'; - rddata_reg(1) <= 'X'; - rddata_reg(2) <= 'X'; - rddata_reg(3) <= 'X'; - rddata_reg(4) <= 'X'; - rddata_reg(5) <= 'X'; - rddata_reg(6) <= 'X'; - rddata_reg(7) <= 'X'; - rddata_reg(8) <= 'X'; - rddata_reg(9) <= 'X'; - rddata_reg(10) <= 'X'; - rddata_reg(11) <= 'X'; - rddata_reg(12) <= 'X'; - rddata_reg(13) <= 'X'; - rddata_reg(14) <= 'X'; - rddata_reg(15) <= 'X'; - rddata_reg(16) <= 'X'; - rddata_reg(17) <= 'X'; - rddata_reg(18) <= 'X'; - rddata_reg(19) <= 'X'; - rddata_reg(20) <= 'X'; - rddata_reg(21) <= 'X'; - rddata_reg(22) <= 'X'; - rddata_reg(23) <= 'X'; - rddata_reg(24) <= 'X'; - rddata_reg(25) <= 'X'; - rddata_reg(26) <= 'X'; - rddata_reg(27) <= 'X'; - rddata_reg(28) <= 'X'; - rddata_reg(29) <= 'X'; - rddata_reg(30) <= 'X'; - rddata_reg(31) <= 'X'; - ack_sreg(4) <= '1'; - ack_in_progress <= '1'; - when others => - -- prevent the slave from hanging the bus on invalid address - ack_in_progress <= '1'; - ack_sreg(0) <= '1'; - end case; - end if; - end if; - end if; - end process; - - - -- Drive the data output bus - wb_dat_o <= rddata_reg; - -- asynchronous std_logic_vector register : None (type RW/RO, dot_prod_clk_reg_i <-> clk_sys_i) - process (dot_prod_clk_reg_i, rst_n_i) - begin - if (rst_n_i = '0') then - dot_prod_wb_ram_coeff_dat_swb_s0 <= '0'; - dot_prod_wb_ram_coeff_dat_swb_s1 <= '0'; - dot_prod_wb_ram_coeff_dat_swb_s2 <= '0'; - dot_prod_wb_ram_coeff_dat_o <= "00000000000000000000000000000000"; - elsif rising_edge(dot_prod_clk_reg_i) then - dot_prod_wb_ram_coeff_dat_swb_s0 <= dot_prod_wb_ram_coeff_dat_swb; - dot_prod_wb_ram_coeff_dat_swb_s1 <= dot_prod_wb_ram_coeff_dat_swb_s0; - dot_prod_wb_ram_coeff_dat_swb_s2 <= dot_prod_wb_ram_coeff_dat_swb_s1; - if ((dot_prod_wb_ram_coeff_dat_swb_s2 = '0') and (dot_prod_wb_ram_coeff_dat_swb_s1 = '1')) then - dot_prod_wb_ram_coeff_dat_o <= dot_prod_wb_ram_coeff_dat_int; - end if; - end if; - end process; - - - -- asynchronous std_logic_vector register : None (type RW/RO, dot_prod_clk_reg_i <-> clk_sys_i) - process (dot_prod_clk_reg_i, rst_n_i) - begin - if (rst_n_i = '0') then - dot_prod_wb_ram_coeff_addr_swb_s0 <= '0'; - dot_prod_wb_ram_coeff_addr_swb_s1 <= '0'; - dot_prod_wb_ram_coeff_addr_swb_s2 <= '0'; - dot_prod_wb_ram_coeff_addr_o <= "00000000000000000000000000000000"; - elsif rising_edge(dot_prod_clk_reg_i) then - dot_prod_wb_ram_coeff_addr_swb_s0 <= dot_prod_wb_ram_coeff_addr_swb; - dot_prod_wb_ram_coeff_addr_swb_s1 <= dot_prod_wb_ram_coeff_addr_swb_s0; - dot_prod_wb_ram_coeff_addr_swb_s2 <= dot_prod_wb_ram_coeff_addr_swb_s1; - if ((dot_prod_wb_ram_coeff_addr_swb_s2 = '0') and (dot_prod_wb_ram_coeff_addr_swb_s1 = '1')) then - dot_prod_wb_ram_coeff_addr_o <= dot_prod_wb_ram_coeff_addr_int; - end if; - end if; - end process; - - - process (dot_prod_clk_reg_i, rst_n_i) - begin - if (rst_n_i = '0') then - dot_prod_wb_ram_write_enable_o <= '0'; - dot_prod_wb_ram_write_enable_sync0 <= '0'; - dot_prod_wb_ram_write_enable_sync1 <= '0'; - dot_prod_wb_ram_write_enable_sync2 <= '0'; - elsif rising_edge(dot_prod_clk_reg_i) then - dot_prod_wb_ram_write_enable_sync0 <= dot_prod_wb_ram_write_enable_int; - dot_prod_wb_ram_write_enable_sync1 <= dot_prod_wb_ram_write_enable_sync0; - dot_prod_wb_ram_write_enable_sync2 <= dot_prod_wb_ram_write_enable_sync1; - dot_prod_wb_ram_write_enable_o <= dot_prod_wb_ram_write_enable_sync2 and (not dot_prod_wb_ram_write_enable_sync1); - end if; - end process; - - - rwaddr_reg <= wb_adr_i; - wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); - -- ACK signal generation. Just pass the LSB of ACK counter. - wb_ack_o <= ack_sreg(0); -end syn; diff --git a/hdl/modules/fofb_processing/cheby/dot_prod_wb.cheby b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby similarity index 79% rename from hdl/modules/fofb_processing/cheby/dot_prod_wb.cheby rename to hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby index b1449ee8..4496374b 100644 --- a/hdl/modules/fofb_processing/cheby/dot_prod_wb.cheby +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby @@ -1,6 +1,6 @@ memory-map: bus: wb-32-be - name: dot_prod_wb + name: wb_fofb_processing description: interface to memory children: - reg: @@ -10,7 +10,7 @@ memory-map: access: rw x-wbgen: type: SLV - clock: dot_prod_clk_reg_i + clock: fofb_processing_clk_reg_i - reg: name: ram_coeff_addr address: 0x00000004 @@ -18,7 +18,7 @@ memory-map: access: rw x-wbgen: type: SLV - clock: dot_prod_clk_reg_i + clock: fofb_processing_clk_reg_i - reg: name: ram_write address: 0x00000008 @@ -32,4 +32,4 @@ memory-map: range: 0 x-wbgen: type: MONOSTABLE - clock: dot_prod_clk_reg_i + clock: fofb_processing_clk_reg_i diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h new file mode 100644 index 00000000..821920d7 --- /dev/null +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h @@ -0,0 +1,26 @@ +#ifndef __CHEBY__WB_FOFB_PROCESSING__H__ +#define __CHEBY__WB_FOFB_PROCESSING__H__ +#define WB_FOFB_PROCESSING_SIZE 12 /* 0xc */ + +/* None */ +#define WB_FOFB_PROCESSING_RAM_COEFF_DAT 0x0UL + +/* None */ +#define WB_FOFB_PROCESSING_RAM_COEFF_ADDR 0x4UL + +/* None */ +#define WB_FOFB_PROCESSING_RAM_WRITE 0x8UL +#define WB_FOFB_PROCESSING_RAM_WRITE_ENABLE 0x1UL + +struct wb_fofb_processing { + /* [0x0]: REG (rw) (no description) */ + uint32_t ram_coeff_dat; + + /* [0x4]: REG (rw) (no description) */ + uint32_t ram_coeff_addr; + + /* [0x8]: REG (rw) (no description) */ + uint32_t ram_write; +}; + +#endif /* __CHEBY__WB_FOFB_PROCESSING__H__ */ diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd new file mode 100644 index 00000000..c101252d --- /dev/null +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd @@ -0,0 +1,241 @@ +------------------------------------------------------------------------------- +-- Title : Wishbone slave core for interface to memory +------------------------------------------------------------------------------- +-- File : wb_fofb_processing_regs.vhdl +-- Author : auto-generated by wbgen2 from wb_fofb_processing_regs.wb +-- Created : Tue Oct 19 11:48:48 2021 +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fofb_processing_regs.wb +-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity wb_fofb_processing is + port ( + rst_n_i : in std_logic; + clk_sys_i : in std_logic; + wb_adr_i : in std_logic_vector(1 downto 0); + wb_dat_i : in std_logic_vector(31 downto 0); + wb_dat_o : out std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_sel_i : in std_logic_vector(3 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_ack_o : out std_logic; + wb_stall_o : out std_logic; + fofb_processing_clk_reg_i : in std_logic; + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' + wb_fofb_processing_ram_coeff_dat_o : out std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' + wb_fofb_processing_ram_coeff_addr_o : out std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' + wb_fofb_processing_ram_write_enable_o : out std_logic + ); +end wb_fofb_processing; + +architecture syn of wb_fofb_processing is + + signal wb_fofb_processing_ram_coeff_dat_int : std_logic_vector(31 downto 0); + signal wb_fofb_processing_ram_coeff_dat_swb : std_logic; + signal wb_fofb_processing_ram_coeff_dat_swb_delay : std_logic; + signal wb_fofb_processing_ram_coeff_dat_swb_s0 : std_logic; + signal wb_fofb_processing_ram_coeff_dat_swb_s1 : std_logic; + signal wb_fofb_processing_ram_coeff_dat_swb_s2 : std_logic; + signal wb_fofb_processing_ram_coeff_addr_int : std_logic_vector(31 downto 0); + signal wb_fofb_processing_ram_coeff_addr_swb : std_logic; + signal wb_fofb_processing_ram_coeff_addr_swb_delay : std_logic; + signal wb_fofb_processing_ram_coeff_addr_swb_s0 : std_logic; + signal wb_fofb_processing_ram_coeff_addr_swb_s1 : std_logic; + signal wb_fofb_processing_ram_coeff_addr_swb_s2 : std_logic; + signal wb_fofb_processing_ram_write_enable_int : std_logic; + signal wb_fofb_processing_ram_write_enable_int_delay : std_logic; + signal wb_fofb_processing_ram_write_enable_sync0 : std_logic; + signal wb_fofb_processing_ram_write_enable_sync1 : std_logic; + signal wb_fofb_processing_ram_write_enable_sync2 : std_logic; + signal ack_sreg : std_logic_vector(9 downto 0); + signal rddata_reg : std_logic_vector(31 downto 0); + signal wrdata_reg : std_logic_vector(31 downto 0); + signal bwsel_reg : std_logic_vector(3 downto 0); + signal rwaddr_reg : std_logic_vector(1 downto 0); + signal ack_in_progress : std_logic; + signal wr_int : std_logic; + signal rd_int : std_logic; + signal allones : std_logic_vector(31 downto 0); + signal allzeros : std_logic_vector(31 downto 0); + +begin + -- Some internal signals assignments. For (foreseen) compatibility with other bus standards. + wrdata_reg <= wb_dat_i; + bwsel_reg <= wb_sel_i; + rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); + wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); + allones <= (others => '1'); + allzeros <= (others => '0'); + -- + -- Main register bank access process. + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + ack_sreg <= "0000000000"; + ack_in_progress <= '0'; + rddata_reg <= "00000000000000000000000000000000"; + wb_fofb_processing_ram_coeff_dat_int <= "00000000000000000000000000000000"; + wb_fofb_processing_ram_coeff_dat_swb <= '0'; + wb_fofb_processing_ram_coeff_dat_swb_delay <= '0'; + wb_fofb_processing_ram_coeff_addr_int <= "00000000000000000000000000000000"; + wb_fofb_processing_ram_coeff_addr_swb <= '0'; + wb_fofb_processing_ram_coeff_addr_swb_delay <= '0'; + wb_fofb_processing_ram_write_enable_int <= '0'; + wb_fofb_processing_ram_write_enable_int_delay <= '0'; + elsif rising_edge(clk_sys_i) then + -- advance the ACK generator shift register + ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); + ack_sreg(9) <= '0'; + if (ack_in_progress = '1') then + if (ack_sreg(0) = '1') then + ack_in_progress <= '0'; + else + wb_fofb_processing_ram_coeff_dat_swb <= wb_fofb_processing_ram_coeff_dat_swb_delay; + wb_fofb_processing_ram_coeff_dat_swb_delay <= '0'; + wb_fofb_processing_ram_coeff_addr_swb <= wb_fofb_processing_ram_coeff_addr_swb_delay; + wb_fofb_processing_ram_coeff_addr_swb_delay <= '0'; + wb_fofb_processing_ram_write_enable_int <= wb_fofb_processing_ram_write_enable_int_delay; + wb_fofb_processing_ram_write_enable_int_delay <= '0'; + end if; + else + if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then + case rwaddr_reg(1 downto 0) is + when "00" => + if (wb_we_i = '1') then + wb_fofb_processing_ram_coeff_dat_int <= wrdata_reg(31 downto 0); + wb_fofb_processing_ram_coeff_dat_swb <= '1'; + wb_fofb_processing_ram_coeff_dat_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= wb_fofb_processing_ram_coeff_dat_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "01" => + if (wb_we_i = '1') then + wb_fofb_processing_ram_coeff_addr_int <= wrdata_reg(31 downto 0); + wb_fofb_processing_ram_coeff_addr_swb <= '1'; + wb_fofb_processing_ram_coeff_addr_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= wb_fofb_processing_ram_coeff_addr_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "10" => + if (wb_we_i = '1') then + wb_fofb_processing_ram_write_enable_int <= wrdata_reg(0); + wb_fofb_processing_ram_write_enable_int_delay <= wrdata_reg(0); + end if; + rddata_reg(0) <= '0'; + rddata_reg(0) <= 'X'; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(4) <= '1'; + ack_in_progress <= '1'; + when others => + -- prevent the slave from hanging the bus on invalid address + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end case; + end if; + end if; + end if; + end process; + + + -- Drive the data output bus + wb_dat_o <= rddata_reg; + -- asynchronous std_logic_vector register : None (type RW/RO, fofb_processing_clk_reg_i <-> clk_sys_i) + process (fofb_processing_clk_reg_i, rst_n_i) + begin + if (rst_n_i = '0') then + wb_fofb_processing_ram_coeff_dat_swb_s0 <= '0'; + wb_fofb_processing_ram_coeff_dat_swb_s1 <= '0'; + wb_fofb_processing_ram_coeff_dat_swb_s2 <= '0'; + wb_fofb_processing_ram_coeff_dat_o <= "00000000000000000000000000000000"; + elsif rising_edge(fofb_processing_clk_reg_i) then + wb_fofb_processing_ram_coeff_dat_swb_s0 <= wb_fofb_processing_ram_coeff_dat_swb; + wb_fofb_processing_ram_coeff_dat_swb_s1 <= wb_fofb_processing_ram_coeff_dat_swb_s0; + wb_fofb_processing_ram_coeff_dat_swb_s2 <= wb_fofb_processing_ram_coeff_dat_swb_s1; + if ((wb_fofb_processing_ram_coeff_dat_swb_s2 = '0') and (wb_fofb_processing_ram_coeff_dat_swb_s1 = '1')) then + wb_fofb_processing_ram_coeff_dat_o <= wb_fofb_processing_ram_coeff_dat_int; + end if; + end if; + end process; + + + -- asynchronous std_logic_vector register : None (type RW/RO, fofb_processing_clk_reg_i <-> clk_sys_i) + process (fofb_processing_clk_reg_i, rst_n_i) + begin + if (rst_n_i = '0') then + wb_fofb_processing_ram_coeff_addr_swb_s0 <= '0'; + wb_fofb_processing_ram_coeff_addr_swb_s1 <= '0'; + wb_fofb_processing_ram_coeff_addr_swb_s2 <= '0'; + wb_fofb_processing_ram_coeff_addr_o <= "00000000000000000000000000000000"; + elsif rising_edge(fofb_processing_clk_reg_i) then + wb_fofb_processing_ram_coeff_addr_swb_s0 <= wb_fofb_processing_ram_coeff_addr_swb; + wb_fofb_processing_ram_coeff_addr_swb_s1 <= wb_fofb_processing_ram_coeff_addr_swb_s0; + wb_fofb_processing_ram_coeff_addr_swb_s2 <= wb_fofb_processing_ram_coeff_addr_swb_s1; + if ((wb_fofb_processing_ram_coeff_addr_swb_s2 = '0') and (wb_fofb_processing_ram_coeff_addr_swb_s1 = '1')) then + wb_fofb_processing_ram_coeff_addr_o <= wb_fofb_processing_ram_coeff_addr_int; + end if; + end if; + end process; + + + process (fofb_processing_clk_reg_i, rst_n_i) + begin + if (rst_n_i = '0') then + wb_fofb_processing_ram_write_enable_o <= '0'; + wb_fofb_processing_ram_write_enable_sync0 <= '0'; + wb_fofb_processing_ram_write_enable_sync1 <= '0'; + wb_fofb_processing_ram_write_enable_sync2 <= '0'; + elsif rising_edge(fofb_processing_clk_reg_i) then + wb_fofb_processing_ram_write_enable_sync0 <= wb_fofb_processing_ram_write_enable_int; + wb_fofb_processing_ram_write_enable_sync1 <= wb_fofb_processing_ram_write_enable_sync0; + wb_fofb_processing_ram_write_enable_sync2 <= wb_fofb_processing_ram_write_enable_sync1; + wb_fofb_processing_ram_write_enable_o <= wb_fofb_processing_ram_write_enable_sync2 and (not wb_fofb_processing_ram_write_enable_sync1); + end if; + end process; + + + rwaddr_reg <= wb_adr_i; + wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); + -- ACK signal generation. Just pass the LSB of ACK counter. + wb_ack_o <= ack_sreg(0); +end syn; diff --git a/hdl/modules/fofb_processing/wb_fofb_processing.vhd b/hdl/modules/fofb_processing/wb_fofb_processing.vhd index 7989ffb2..c814428f 100644 --- a/hdl/modules/fofb_processing/wb_fofb_processing.vhd +++ b/hdl/modules/fofb_processing/wb_fofb_processing.vhd @@ -277,7 +277,7 @@ begin resized_addr(c_WISHBONE_ADDRESS_WIDTH-1 downto c_PERIPH_ADDR_SIZE) <= (others => '0'); - cmp_dot_prod_wb: dot_prod_wb + cmp_dot_prod_wb: wb_fofb_processing_regs port map( rst_n_i => rst_sys_n_i, clk_sys_i => clk_sys_i, @@ -292,18 +292,18 @@ begin wb_ack_o => wb_slv_adp_in.ack, wb_stall_o => wb_slv_adp_in.stall, - dot_prod_clk_reg_i => clk_i, + fofb_processing_clk_reg_i => clk_i, - -- Port for asynchronous (clock: matmul_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - dot_prod_wb_ram_coeff_dat_o + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' + wb_fofb_processing_ram_coeff_dat_o => ram_coeff_dat_s, - -- Port for asynchronous (clock: matmul_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - dot_prod_wb_ram_coeff_addr_o + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' + wb_fofb_processing_ram_coeff_addr_o => ram_coeff_addr_s, - -- Port for asynchronous (clock: matmul_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' - dot_prod_wb_ram_write_enable_o + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' + wb_fofb_processing_ram_write_enable_o => ram_write_enable_s ); diff --git a/hdl/sim/regs/wb_fofb_processing_regs.vh b/hdl/sim/regs/wb_fofb_processing_regs.vh new file mode 100644 index 00000000..0e97b00a --- /dev/null +++ b/hdl/sim/regs/wb_fofb_processing_regs.vh @@ -0,0 +1,6 @@ +`define WB_FOFB_PROCESSING_SIZE 12 +`define ADDR_WB_FOFB_PROCESSING_RAM_COEFF_DAT 'h0 +`define ADDR_WB_FOFB_PROCESSING_RAM_COEFF_ADDR 'h4 +`define ADDR_WB_FOFB_PROCESSING_RAM_WRITE 'h8 +`define WB_FOFB_PROCESSING_RAM_WRITE_ENABLE_OFFSET 0 +`define WB_FOFB_PROCESSING_RAM_WRITE_ENABLE 'h1 From cab05a3b547c8da7d90dbd8f950bd7d0b5f0129b Mon Sep 17 00:00:00 2001 From: Melissa Aguiar Date: Thu, 21 Oct 2021 10:07:28 -0300 Subject: [PATCH 2/2] fofb_processing: cheby files changed and g_EXTRA_BITS for accumulator added --- hdl/modules/fofb_ctrl_pkg.vhd | 8 +- .../cheby/wb_fofb_processing_regs.cheby | 2 +- .../cheby/wb_fofb_processing_regs.h | 18 +-- .../cheby/wb_fofb_processing_regs.vhd | 148 +++++++++--------- hdl/modules/fofb_processing/dot_prod.vhd | 31 ++-- .../fofb_processing/dot_prod_coeff_vec.vhd | 26 +-- hdl/modules/fofb_processing/dot_prod_pkg.vhd | 39 +++-- .../fofb_processing/fofb_processing.vhd | 9 +- .../fofb_processing_channel.vhd | 29 ++-- .../fofb_processing/wb_fofb_processing.vhd | 13 +- .../fofb_processing/xwb_fofb_processing.vhd | 7 +- hdl/sim/regs/wb_fofb_processing_regs.vh | 12 +- hdl/testbench/fofb_processing/dot_tb.vhd | 1 - .../afc_ref_fofb_ctrl_gen.vhd | 4 +- 14 files changed, 189 insertions(+), 158 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index 3b305c4a..63076d4b 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -505,7 +505,6 @@ package fofb_ctrl_pkg is generic ( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -531,6 +530,9 @@ package fofb_ctrl_pkg is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Number of channels g_CHANNELS : natural := 8; @@ -586,7 +588,6 @@ package fofb_ctrl_pkg is generic ( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -612,6 +613,9 @@ package fofb_ctrl_pkg is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Number of channels g_CHANNELS : natural := 8; diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby index 4496374b..4dd2e58d 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.cheby @@ -1,6 +1,6 @@ memory-map: bus: wb-32-be - name: wb_fofb_processing + name: wb_fofb_processing_regs description: interface to memory children: - reg: diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h index 821920d7..fd960aa0 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h @@ -1,18 +1,18 @@ -#ifndef __CHEBY__WB_FOFB_PROCESSING__H__ -#define __CHEBY__WB_FOFB_PROCESSING__H__ -#define WB_FOFB_PROCESSING_SIZE 12 /* 0xc */ +#ifndef __CHEBY__WB_FOFB_PROCESSING_REGS__H__ +#define __CHEBY__WB_FOFB_PROCESSING_REGS__H__ +#define WB_FOFB_PROCESSING_REGS_SIZE 12 /* 0xc */ /* None */ -#define WB_FOFB_PROCESSING_RAM_COEFF_DAT 0x0UL +#define WB_FOFB_PROCESSING_REGS_RAM_COEFF_DAT 0x0UL /* None */ -#define WB_FOFB_PROCESSING_RAM_COEFF_ADDR 0x4UL +#define WB_FOFB_PROCESSING_REGS_RAM_COEFF_ADDR 0x4UL /* None */ -#define WB_FOFB_PROCESSING_RAM_WRITE 0x8UL -#define WB_FOFB_PROCESSING_RAM_WRITE_ENABLE 0x1UL +#define WB_FOFB_PROCESSING_REGS_RAM_WRITE 0x8UL +#define WB_FOFB_PROCESSING_REGS_RAM_WRITE_ENABLE 0x1UL -struct wb_fofb_processing { +struct wb_fofb_processing_regs { /* [0x0]: REG (rw) (no description) */ uint32_t ram_coeff_dat; @@ -23,4 +23,4 @@ struct wb_fofb_processing { uint32_t ram_write; }; -#endif /* __CHEBY__WB_FOFB_PROCESSING__H__ */ +#endif /* __CHEBY__WB_FOFB_PROCESSING_REGS__H__ */ diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd index c101252d..cf52319e 100644 --- a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd +++ b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- File : wb_fofb_processing_regs.vhdl -- Author : auto-generated by wbgen2 from wb_fofb_processing_regs.wb --- Created : Tue Oct 19 11:48:48 2021 +-- Created : Thu Oct 21 09:13:16 2021 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fofb_processing_regs.wb @@ -14,7 +14,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity wb_fofb_processing is +entity wb_fofb_processing_regs is port ( rst_n_i : in std_logic; clk_sys_i : in std_logic; @@ -29,33 +29,33 @@ entity wb_fofb_processing is wb_stall_o : out std_logic; fofb_processing_clk_reg_i : in std_logic; -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - wb_fofb_processing_ram_coeff_dat_o : out std_logic_vector(31 downto 0); + wb_fofb_processing_regs_ram_coeff_dat_o : out std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - wb_fofb_processing_ram_coeff_addr_o : out std_logic_vector(31 downto 0); + wb_fofb_processing_regs_ram_coeff_addr_o : out std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fofb_processing_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' - wb_fofb_processing_ram_write_enable_o : out std_logic + wb_fofb_processing_regs_ram_write_enable_o : out std_logic ); -end wb_fofb_processing; +end wb_fofb_processing_regs; -architecture syn of wb_fofb_processing is +architecture syn of wb_fofb_processing_regs is - signal wb_fofb_processing_ram_coeff_dat_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_ram_coeff_dat_swb : std_logic; - signal wb_fofb_processing_ram_coeff_dat_swb_delay : std_logic; - signal wb_fofb_processing_ram_coeff_dat_swb_s0 : std_logic; - signal wb_fofb_processing_ram_coeff_dat_swb_s1 : std_logic; - signal wb_fofb_processing_ram_coeff_dat_swb_s2 : std_logic; - signal wb_fofb_processing_ram_coeff_addr_int : std_logic_vector(31 downto 0); - signal wb_fofb_processing_ram_coeff_addr_swb : std_logic; - signal wb_fofb_processing_ram_coeff_addr_swb_delay : std_logic; - signal wb_fofb_processing_ram_coeff_addr_swb_s0 : std_logic; - signal wb_fofb_processing_ram_coeff_addr_swb_s1 : std_logic; - signal wb_fofb_processing_ram_coeff_addr_swb_s2 : std_logic; - signal wb_fofb_processing_ram_write_enable_int : std_logic; - signal wb_fofb_processing_ram_write_enable_int_delay : std_logic; - signal wb_fofb_processing_ram_write_enable_sync0 : std_logic; - signal wb_fofb_processing_ram_write_enable_sync1 : std_logic; - signal wb_fofb_processing_ram_write_enable_sync2 : std_logic; + signal wb_fofb_processing_regs_ram_coeff_dat_int : std_logic_vector(31 downto 0); + signal wb_fofb_processing_regs_ram_coeff_dat_swb : std_logic; + signal wb_fofb_processing_regs_ram_coeff_dat_swb_delay : std_logic; + signal wb_fofb_processing_regs_ram_coeff_dat_swb_s0 : std_logic; + signal wb_fofb_processing_regs_ram_coeff_dat_swb_s1 : std_logic; + signal wb_fofb_processing_regs_ram_coeff_dat_swb_s2 : std_logic; + signal wb_fofb_processing_regs_ram_coeff_addr_int : std_logic_vector(31 downto 0); + signal wb_fofb_processing_regs_ram_coeff_addr_swb : std_logic; + signal wb_fofb_processing_regs_ram_coeff_addr_swb_delay : std_logic; + signal wb_fofb_processing_regs_ram_coeff_addr_swb_s0 : std_logic; + signal wb_fofb_processing_regs_ram_coeff_addr_swb_s1 : std_logic; + signal wb_fofb_processing_regs_ram_coeff_addr_swb_s2 : std_logic; + signal wb_fofb_processing_regs_ram_write_enable_int : std_logic; + signal wb_fofb_processing_regs_ram_write_enable_int_delay : std_logic; + signal wb_fofb_processing_regs_ram_write_enable_sync0 : std_logic; + signal wb_fofb_processing_regs_ram_write_enable_sync1 : std_logic; + signal wb_fofb_processing_regs_ram_write_enable_sync2 : std_logic; signal ack_sreg : std_logic_vector(9 downto 0); signal rddata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0); @@ -83,14 +83,14 @@ begin ack_sreg <= "0000000000"; ack_in_progress <= '0'; rddata_reg <= "00000000000000000000000000000000"; - wb_fofb_processing_ram_coeff_dat_int <= "00000000000000000000000000000000"; - wb_fofb_processing_ram_coeff_dat_swb <= '0'; - wb_fofb_processing_ram_coeff_dat_swb_delay <= '0'; - wb_fofb_processing_ram_coeff_addr_int <= "00000000000000000000000000000000"; - wb_fofb_processing_ram_coeff_addr_swb <= '0'; - wb_fofb_processing_ram_coeff_addr_swb_delay <= '0'; - wb_fofb_processing_ram_write_enable_int <= '0'; - wb_fofb_processing_ram_write_enable_int_delay <= '0'; + wb_fofb_processing_regs_ram_coeff_dat_int <= "00000000000000000000000000000000"; + wb_fofb_processing_regs_ram_coeff_dat_swb <= '0'; + wb_fofb_processing_regs_ram_coeff_dat_swb_delay <= '0'; + wb_fofb_processing_regs_ram_coeff_addr_int <= "00000000000000000000000000000000"; + wb_fofb_processing_regs_ram_coeff_addr_swb <= '0'; + wb_fofb_processing_regs_ram_coeff_addr_swb_delay <= '0'; + wb_fofb_processing_regs_ram_write_enable_int <= '0'; + wb_fofb_processing_regs_ram_write_enable_int_delay <= '0'; elsif rising_edge(clk_sys_i) then -- advance the ACK generator shift register ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); @@ -99,38 +99,38 @@ begin if (ack_sreg(0) = '1') then ack_in_progress <= '0'; else - wb_fofb_processing_ram_coeff_dat_swb <= wb_fofb_processing_ram_coeff_dat_swb_delay; - wb_fofb_processing_ram_coeff_dat_swb_delay <= '0'; - wb_fofb_processing_ram_coeff_addr_swb <= wb_fofb_processing_ram_coeff_addr_swb_delay; - wb_fofb_processing_ram_coeff_addr_swb_delay <= '0'; - wb_fofb_processing_ram_write_enable_int <= wb_fofb_processing_ram_write_enable_int_delay; - wb_fofb_processing_ram_write_enable_int_delay <= '0'; + wb_fofb_processing_regs_ram_coeff_dat_swb <= wb_fofb_processing_regs_ram_coeff_dat_swb_delay; + wb_fofb_processing_regs_ram_coeff_dat_swb_delay <= '0'; + wb_fofb_processing_regs_ram_coeff_addr_swb <= wb_fofb_processing_regs_ram_coeff_addr_swb_delay; + wb_fofb_processing_regs_ram_coeff_addr_swb_delay <= '0'; + wb_fofb_processing_regs_ram_write_enable_int <= wb_fofb_processing_regs_ram_write_enable_int_delay; + wb_fofb_processing_regs_ram_write_enable_int_delay <= '0'; end if; else if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then case rwaddr_reg(1 downto 0) is when "00" => if (wb_we_i = '1') then - wb_fofb_processing_ram_coeff_dat_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_ram_coeff_dat_swb <= '1'; - wb_fofb_processing_ram_coeff_dat_swb_delay <= '1'; + wb_fofb_processing_regs_ram_coeff_dat_int <= wrdata_reg(31 downto 0); + wb_fofb_processing_regs_ram_coeff_dat_swb <= '1'; + wb_fofb_processing_regs_ram_coeff_dat_swb_delay <= '1'; end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_ram_coeff_dat_int; + rddata_reg(31 downto 0) <= wb_fofb_processing_regs_ram_coeff_dat_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; when "01" => if (wb_we_i = '1') then - wb_fofb_processing_ram_coeff_addr_int <= wrdata_reg(31 downto 0); - wb_fofb_processing_ram_coeff_addr_swb <= '1'; - wb_fofb_processing_ram_coeff_addr_swb_delay <= '1'; + wb_fofb_processing_regs_ram_coeff_addr_int <= wrdata_reg(31 downto 0); + wb_fofb_processing_regs_ram_coeff_addr_swb <= '1'; + wb_fofb_processing_regs_ram_coeff_addr_swb_delay <= '1'; end if; - rddata_reg(31 downto 0) <= wb_fofb_processing_ram_coeff_addr_int; + rddata_reg(31 downto 0) <= wb_fofb_processing_regs_ram_coeff_addr_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; when "10" => if (wb_we_i = '1') then - wb_fofb_processing_ram_write_enable_int <= wrdata_reg(0); - wb_fofb_processing_ram_write_enable_int_delay <= wrdata_reg(0); + wb_fofb_processing_regs_ram_write_enable_int <= wrdata_reg(0); + wb_fofb_processing_regs_ram_write_enable_int_delay <= wrdata_reg(0); end if; rddata_reg(0) <= '0'; rddata_reg(0) <= 'X'; @@ -184,16 +184,16 @@ begin process (fofb_processing_clk_reg_i, rst_n_i) begin if (rst_n_i = '0') then - wb_fofb_processing_ram_coeff_dat_swb_s0 <= '0'; - wb_fofb_processing_ram_coeff_dat_swb_s1 <= '0'; - wb_fofb_processing_ram_coeff_dat_swb_s2 <= '0'; - wb_fofb_processing_ram_coeff_dat_o <= "00000000000000000000000000000000"; + wb_fofb_processing_regs_ram_coeff_dat_swb_s0 <= '0'; + wb_fofb_processing_regs_ram_coeff_dat_swb_s1 <= '0'; + wb_fofb_processing_regs_ram_coeff_dat_swb_s2 <= '0'; + wb_fofb_processing_regs_ram_coeff_dat_o <= "00000000000000000000000000000000"; elsif rising_edge(fofb_processing_clk_reg_i) then - wb_fofb_processing_ram_coeff_dat_swb_s0 <= wb_fofb_processing_ram_coeff_dat_swb; - wb_fofb_processing_ram_coeff_dat_swb_s1 <= wb_fofb_processing_ram_coeff_dat_swb_s0; - wb_fofb_processing_ram_coeff_dat_swb_s2 <= wb_fofb_processing_ram_coeff_dat_swb_s1; - if ((wb_fofb_processing_ram_coeff_dat_swb_s2 = '0') and (wb_fofb_processing_ram_coeff_dat_swb_s1 = '1')) then - wb_fofb_processing_ram_coeff_dat_o <= wb_fofb_processing_ram_coeff_dat_int; + wb_fofb_processing_regs_ram_coeff_dat_swb_s0 <= wb_fofb_processing_regs_ram_coeff_dat_swb; + wb_fofb_processing_regs_ram_coeff_dat_swb_s1 <= wb_fofb_processing_regs_ram_coeff_dat_swb_s0; + wb_fofb_processing_regs_ram_coeff_dat_swb_s2 <= wb_fofb_processing_regs_ram_coeff_dat_swb_s1; + if ((wb_fofb_processing_regs_ram_coeff_dat_swb_s2 = '0') and (wb_fofb_processing_regs_ram_coeff_dat_swb_s1 = '1')) then + wb_fofb_processing_regs_ram_coeff_dat_o <= wb_fofb_processing_regs_ram_coeff_dat_int; end if; end if; end process; @@ -203,16 +203,16 @@ begin process (fofb_processing_clk_reg_i, rst_n_i) begin if (rst_n_i = '0') then - wb_fofb_processing_ram_coeff_addr_swb_s0 <= '0'; - wb_fofb_processing_ram_coeff_addr_swb_s1 <= '0'; - wb_fofb_processing_ram_coeff_addr_swb_s2 <= '0'; - wb_fofb_processing_ram_coeff_addr_o <= "00000000000000000000000000000000"; + wb_fofb_processing_regs_ram_coeff_addr_swb_s0 <= '0'; + wb_fofb_processing_regs_ram_coeff_addr_swb_s1 <= '0'; + wb_fofb_processing_regs_ram_coeff_addr_swb_s2 <= '0'; + wb_fofb_processing_regs_ram_coeff_addr_o <= "00000000000000000000000000000000"; elsif rising_edge(fofb_processing_clk_reg_i) then - wb_fofb_processing_ram_coeff_addr_swb_s0 <= wb_fofb_processing_ram_coeff_addr_swb; - wb_fofb_processing_ram_coeff_addr_swb_s1 <= wb_fofb_processing_ram_coeff_addr_swb_s0; - wb_fofb_processing_ram_coeff_addr_swb_s2 <= wb_fofb_processing_ram_coeff_addr_swb_s1; - if ((wb_fofb_processing_ram_coeff_addr_swb_s2 = '0') and (wb_fofb_processing_ram_coeff_addr_swb_s1 = '1')) then - wb_fofb_processing_ram_coeff_addr_o <= wb_fofb_processing_ram_coeff_addr_int; + wb_fofb_processing_regs_ram_coeff_addr_swb_s0 <= wb_fofb_processing_regs_ram_coeff_addr_swb; + wb_fofb_processing_regs_ram_coeff_addr_swb_s1 <= wb_fofb_processing_regs_ram_coeff_addr_swb_s0; + wb_fofb_processing_regs_ram_coeff_addr_swb_s2 <= wb_fofb_processing_regs_ram_coeff_addr_swb_s1; + if ((wb_fofb_processing_regs_ram_coeff_addr_swb_s2 = '0') and (wb_fofb_processing_regs_ram_coeff_addr_swb_s1 = '1')) then + wb_fofb_processing_regs_ram_coeff_addr_o <= wb_fofb_processing_regs_ram_coeff_addr_int; end if; end if; end process; @@ -221,15 +221,15 @@ begin process (fofb_processing_clk_reg_i, rst_n_i) begin if (rst_n_i = '0') then - wb_fofb_processing_ram_write_enable_o <= '0'; - wb_fofb_processing_ram_write_enable_sync0 <= '0'; - wb_fofb_processing_ram_write_enable_sync1 <= '0'; - wb_fofb_processing_ram_write_enable_sync2 <= '0'; + wb_fofb_processing_regs_ram_write_enable_o <= '0'; + wb_fofb_processing_regs_ram_write_enable_sync0 <= '0'; + wb_fofb_processing_regs_ram_write_enable_sync1 <= '0'; + wb_fofb_processing_regs_ram_write_enable_sync2 <= '0'; elsif rising_edge(fofb_processing_clk_reg_i) then - wb_fofb_processing_ram_write_enable_sync0 <= wb_fofb_processing_ram_write_enable_int; - wb_fofb_processing_ram_write_enable_sync1 <= wb_fofb_processing_ram_write_enable_sync0; - wb_fofb_processing_ram_write_enable_sync2 <= wb_fofb_processing_ram_write_enable_sync1; - wb_fofb_processing_ram_write_enable_o <= wb_fofb_processing_ram_write_enable_sync2 and (not wb_fofb_processing_ram_write_enable_sync1); + wb_fofb_processing_regs_ram_write_enable_sync0 <= wb_fofb_processing_regs_ram_write_enable_int; + wb_fofb_processing_regs_ram_write_enable_sync1 <= wb_fofb_processing_regs_ram_write_enable_sync0; + wb_fofb_processing_regs_ram_write_enable_sync2 <= wb_fofb_processing_regs_ram_write_enable_sync1; + wb_fofb_processing_regs_ram_write_enable_o <= wb_fofb_processing_regs_ram_write_enable_sync2 and (not wb_fofb_processing_regs_ram_write_enable_sync1); end if; end process; diff --git a/hdl/modules/fofb_processing/dot_prod.vhd b/hdl/modules/fofb_processing/dot_prod.vhd index a2862808..4035436f 100644 --- a/hdl/modules/fofb_processing/dot_prod.vhd +++ b/hdl/modules/fofb_processing/dot_prod.vhd @@ -74,7 +74,7 @@ end dot_prod; architecture behave of dot_prod is - constant c_REGS_MSB : natural := 2 * g_A_WIDTH + g_EXTRA_WIDTH - 1; + constant c_REGS_MSB : natural := g_A_WIDTH + g_B_WIDTH + g_EXTRA_WIDTH - 1; signal result_s : signed(g_C_WIDTH-1 downto 0) := (others =>'0'); -- Registers for input values @@ -82,7 +82,8 @@ architecture behave of dot_prod is signal b_reg_s : signed(g_B_WIDTH-1 downto 0) := (others =>'0'); -- Registers for intermediate values - signal mult_reg_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); + signal mult_reg_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); signal adder_out_s : signed(c_REGS_MSB downto 0) := (others =>'0'); signal adder_reg1_s : signed(c_REGS_MSB downto 0) := (others =>'0'); signal adder_reg2_s : signed(c_REGS_MSB-g_OUT_FIXED downto 0) @@ -96,12 +97,18 @@ architecture behave of dot_prod is signal valid_reg5_s : std_logic := '0'; -- Registers for the correct DSP48 inference - signal mult_dsp1_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); - signal mult_dsp2_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); - signal mult_dsp3_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); - signal mult_dsp4_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); - signal mult_dsp5_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); - signal mult_dsp6_s : signed(2*g_A_WIDTH-1 downto 0) := (others =>'0'); + signal mult_dsp1_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); + signal mult_dsp2_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); + signal mult_dsp3_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); + signal mult_dsp4_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); + signal mult_dsp5_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); + signal mult_dsp6_s : signed(g_A_WIDTH+g_B_WIDTH-1 downto 0) + := (others =>'0'); signal valid_dsp1_s : std_logic := '0'; signal valid_dsp2_s : std_logic := '0'; signal valid_dsp3_s : std_logic := '0'; @@ -114,7 +121,7 @@ architecture behave of dot_prod is is constant len : integer := x'length; constant mid : integer := len / 2; - alias y : std_logic_vector(len-1 downto 0) is x; + alias y : std_logic_vector(len-1 downto 0) is x; begin if len = 1 then return y(0); @@ -128,7 +135,7 @@ architecture behave of dot_prod is is constant len : integer := x'length; constant mid : integer := len / 2; - alias y : std_logic_vector(len-1 downto 0) is x; + alias y : std_logic_vector(len-1 downto 0) is x; begin if len = 1 then return y(0); @@ -148,9 +155,9 @@ architecture behave of dot_prod is function f_saturate(x : std_logic_vector; x_new_msb : natural) return std_logic_vector is - constant x_old_msb : natural := x'left; + constant x_old_msb : natural := x'left; variable v_is_in_range : std_logic; - variable v_x_sat : std_logic_vector(x_new_msb downto 0); + variable v_x_sat : std_logic_vector(x_new_msb downto 0); begin -- Check if signed overflow (all bits 0) or signed underflow (all bits 1) v_is_in_range := (not vector_OR(x(x_old_msb downto x_new_msb)) or diff --git a/hdl/modules/fofb_processing/dot_prod_coeff_vec.vhd b/hdl/modules/fofb_processing/dot_prod_coeff_vec.vhd index 163c8919..f4191f22 100644 --- a/hdl/modules/fofb_processing/dot_prod_coeff_vec.vhd +++ b/hdl/modules/fofb_processing/dot_prod_coeff_vec.vhd @@ -28,7 +28,6 @@ use work.genram_pkg.all; entity dot_prod_coeff_vec is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -49,7 +48,10 @@ entity dot_prod_coeff_vec is g_C_WIDTH : natural := 16; -- Fixed point representation for output - g_OUT_FIXED : natural := 26 + g_OUT_FIXED : natural := 26; + + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4 ); port( -- Core clock @@ -84,19 +86,19 @@ architecture behave of dot_prod_coeff_vec is signal dcc_data_s : signed(g_A_WIDTH-1 downto 0) := (others => '0'); signal dcc_data_reg_s : signed(g_A_WIDTH-1 downto 0) := (others => '0'); - signal ram_coeff_dat_s : std_logic_vector(g_DATA_WIDTH-1 downto 0) := (others => '0'); + signal ram_coeff_dat_s : std_logic_vector(g_B_WIDTH-1 downto 0) := (others => '0'); signal dcc_addr_reg_s : std_logic_vector(g_ID_WIDTH-1 downto 0) := (others => '0'); signal valid_i_s, valid_reg_s : std_logic := '0'; -- DPRAM port A (write) signal wea_s : std_logic := '0'; signal aa_s : std_logic_vector(g_ID_WIDTH-1 downto 0) := (others => '0'); - signal qa_s : std_logic_vector(g_DATA_WIDTH-1 downto 0) := (others => '0'); + signal qa_s : std_logic_vector(g_B_WIDTH-1 downto 0) := (others => '0'); -- DPRAM port B (read) signal web_s : std_logic := '0'; - signal db_s : std_logic_vector(g_DATA_WIDTH-1 downto 0) := (others => '0'); - signal ram_coeff_s : std_logic_vector(g_DATA_WIDTH-1 downto 0) := (others => '0'); + signal db_s : std_logic_vector(g_B_WIDTH-1 downto 0) := (others => '0'); + signal ram_coeff_s : std_logic_vector(g_B_WIDTH-1 downto 0) := (others => '0'); begin @@ -128,7 +130,7 @@ begin cmp_ram_interface : generic_dpram generic map ( - g_DATA_WIDTH => g_DATA_WIDTH, + g_DATA_WIDTH => g_B_WIDTH, g_SIZE => g_SIZE, g_WITH_BYTE_ENABLE => g_WITH_BYTE_ENABLE, g_ADDR_CONFLICT_RESOLUTION => g_ADDR_CONFLICT_RESOLUTION, @@ -162,15 +164,15 @@ begin generic map ( -- Width for input a[k] - g_A_WIDTH => g_A_WIDTH, + g_A_WIDTH => g_A_WIDTH, -- Width for input b[k] - g_B_WIDTH => g_B_WIDTH, + g_B_WIDTH => g_B_WIDTH, -- Width for output - g_C_WIDTH => g_C_WIDTH, + g_C_WIDTH => g_C_WIDTH, -- Fixed point representation for output - g_OUT_FIXED => g_OUT_FIXED, + g_OUT_FIXED => g_OUT_FIXED, -- Extra bits for accumulator - g_EXTRA_WIDTH => 4 + g_EXTRA_WIDTH => g_EXTRA_WIDTH ) port map ( diff --git a/hdl/modules/fofb_processing/dot_prod_pkg.vhd b/hdl/modules/fofb_processing/dot_prod_pkg.vhd index 65ef199b..6aacd140 100644 --- a/hdl/modules/fofb_processing/dot_prod_pkg.vhd +++ b/hdl/modules/fofb_processing/dot_prod_pkg.vhd @@ -86,7 +86,6 @@ package dot_prod_pkg is component dot_prod_coeff_vec is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -107,7 +106,10 @@ package dot_prod_pkg is g_C_WIDTH : natural := 16; -- Fixed point representation for output - g_OUT_FIXED : natural := 26 + g_OUT_FIXED : natural := 26; + + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4 ); port( -- Core clock @@ -141,7 +143,6 @@ package dot_prod_pkg is component fofb_processing_channel is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -162,7 +163,10 @@ package dot_prod_pkg is g_C_WIDTH : natural := 16; -- Fixed point representation for output - g_OUT_FIXED : natural := 26 + g_OUT_FIXED : natural := 26; + + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4 ); port( --------------------------------------------------------------------------- @@ -199,7 +203,6 @@ package dot_prod_pkg is component fofb_processing is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -225,6 +228,9 @@ package dot_prod_pkg is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Number of channels g_CHANNELS : natural := 8 ); @@ -258,7 +264,7 @@ package dot_prod_pkg is ); end component fofb_processing; - component dot_prod_wb is + component wb_fofb_processing_regs is port( rst_n_i : in std_logic; clk_sys_i : in std_logic; @@ -271,18 +277,17 @@ package dot_prod_pkg is wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; - dot_prod_clk_reg_i : in std_logic; - - -- Port for asynchronous (clock: matmul_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - dot_prod_wb_ram_coeff_dat_o : out std_logic_vector(31 downto 0); - - -- Port for asynchronous (clock: matmul_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - dot_prod_wb_ram_coeff_addr_o : out std_logic_vector(31 downto 0); - - -- Port for asynchronous (clock: matmul_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' - dot_prod_wb_ram_write_enable_o + fofb_processing_clk_reg_i : in std_logic; + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' + wb_fofb_processing_regs_ram_coeff_dat_o + : out std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' + wb_fofb_processing_regs_ram_coeff_addr_o + : out std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fofb_processing_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' + wb_fofb_processing_regs_ram_write_enable_o : out std_logic ); - end component dot_prod_wb; + end component wb_fofb_processing_regs; end package dot_prod_pkg; diff --git a/hdl/modules/fofb_processing/fofb_processing.vhd b/hdl/modules/fofb_processing/fofb_processing.vhd index d681f8c1..dc2a1e53 100644 --- a/hdl/modules/fofb_processing/fofb_processing.vhd +++ b/hdl/modules/fofb_processing/fofb_processing.vhd @@ -28,7 +28,6 @@ use work.genram_pkg.all; entity fofb_processing is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -54,6 +53,9 @@ entity fofb_processing is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Number of channels g_CHANNELS : natural := 8 ); @@ -118,7 +120,6 @@ begin generic map ( -- Standard parameters of generic_dpram - g_DATA_WIDTH => g_DATA_WIDTH, g_SIZE => g_SIZE, g_WITH_BYTE_ENABLE => g_WITH_BYTE_ENABLE, g_ADDR_CONFLICT_RESOLUTION => g_ADDR_CONFLICT_RESOLUTION, @@ -134,7 +135,9 @@ begin -- Width for output g_C_WIDTH => g_C_WIDTH, -- Fixed point representation for output - g_OUT_FIXED => g_OUT_FIXED + g_OUT_FIXED => g_OUT_FIXED, + -- Extra bits for accumulator + g_EXTRA_WIDTH => g_EXTRA_WIDTH ) port map ( diff --git a/hdl/modules/fofb_processing/fofb_processing_channel.vhd b/hdl/modules/fofb_processing/fofb_processing_channel.vhd index 463d1724..3378470d 100644 --- a/hdl/modules/fofb_processing/fofb_processing_channel.vhd +++ b/hdl/modules/fofb_processing/fofb_processing_channel.vhd @@ -26,7 +26,6 @@ use work.dot_prod_pkg.all; entity fofb_processing_channel is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -46,6 +45,9 @@ entity fofb_processing_channel is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Width for output g_C_WIDTH : natural := 16 ); @@ -89,23 +91,24 @@ begin generic map ( -- Standard parameters of generic_dpram - g_DATA_WIDTH => g_DATA_WIDTH, - g_SIZE => g_SIZE, - g_WITH_BYTE_ENABLE => g_WITH_BYTE_ENABLE, - g_ADDR_CONFLICT_RESOLUTION => g_ADDR_CONFLICT_RESOLUTION, - g_INIT_FILE => g_INIT_FILE, - g_DUAL_CLOCK => g_DUAL_CLOCK, - g_FAIL_IF_FILE_NOT_FOUND => g_FAIL_IF_FILE_NOT_FOUND, + g_SIZE => g_SIZE, + g_WITH_BYTE_ENABLE => g_WITH_BYTE_ENABLE, + g_ADDR_CONFLICT_RESOLUTION => g_ADDR_CONFLICT_RESOLUTION, + g_INIT_FILE => g_INIT_FILE, + g_DUAL_CLOCK => g_DUAL_CLOCK, + g_FAIL_IF_FILE_NOT_FOUND => g_FAIL_IF_FILE_NOT_FOUND, -- Width for inputs x and y - g_A_WIDTH => g_A_WIDTH, + g_A_WIDTH => g_A_WIDTH, -- Width for ram data - g_B_WIDTH => g_B_WIDTH, + g_B_WIDTH => g_B_WIDTH, -- Width for dcc addr - g_ID_WIDTH => g_ID_WIDTH, + g_ID_WIDTH => g_ID_WIDTH, -- Width for output - g_C_WIDTH => g_C_WIDTH, + g_C_WIDTH => g_C_WIDTH, -- Fixed point representation for output - g_OUT_FIXED => g_OUT_FIXED + g_OUT_FIXED => g_OUT_FIXED, + -- Extra bits for accumulator + g_EXTRA_WIDTH => g_EXTRA_WIDTH ) port map ( diff --git a/hdl/modules/fofb_processing/wb_fofb_processing.vhd b/hdl/modules/fofb_processing/wb_fofb_processing.vhd index c814428f..a1a6db99 100644 --- a/hdl/modules/fofb_processing/wb_fofb_processing.vhd +++ b/hdl/modules/fofb_processing/wb_fofb_processing.vhd @@ -34,7 +34,6 @@ use work.fofb_ctrl_pkg.all; entity wb_fofb_processing is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -60,6 +59,9 @@ entity wb_fofb_processing is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Number of channels g_CHANNELS : natural := 8; @@ -144,7 +146,6 @@ begin cmp_fofb_processing_interface: fofb_processing generic map( -- Standard parameters of generic_dpram - g_DATA_WIDTH => g_DATA_WIDTH, g_SIZE => g_SIZE, g_WITH_BYTE_ENABLE => g_WITH_BYTE_ENABLE, g_ADDR_CONFLICT_RESOLUTION => g_ADDR_CONFLICT_RESOLUTION, @@ -164,6 +165,8 @@ begin g_C_WIDTH => g_C_WIDTH, -- Fixed point representation for output g_OUT_FIXED => g_OUT_FIXED, + -- Extra bits for accumulator + g_EXTRA_WIDTH => g_EXTRA_WIDTH, -- Number of channels g_CHANNELS => g_CHANNELS ) @@ -295,15 +298,15 @@ begin fofb_processing_clk_reg_i => clk_i, -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - wb_fofb_processing_ram_coeff_dat_o + wb_fofb_processing_regs_ram_coeff_dat_o => ram_coeff_dat_s, -- Port for asynchronous (clock: fofb_processing_clk_reg_i) std_logic_vector field: 'None' in reg: 'None' - wb_fofb_processing_ram_coeff_addr_o + wb_fofb_processing_regs_ram_coeff_addr_o => ram_coeff_addr_s, -- Port for asynchronous (clock: fofb_processing_clk_reg_i) MONOSTABLE field: 'None' in reg: 'None' - wb_fofb_processing_ram_write_enable_o + wb_fofb_processing_regs_ram_write_enable_o => ram_write_enable_s ); diff --git a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd index 07351415..527466ec 100644 --- a/hdl/modules/fofb_processing/xwb_fofb_processing.vhd +++ b/hdl/modules/fofb_processing/xwb_fofb_processing.vhd @@ -34,7 +34,6 @@ use work.fofb_ctrl_pkg.all; entity xwb_fofb_processing is generic( -- Standard parameters of generic_dpram - g_DATA_WIDTH : natural := 32; g_SIZE : natural := 512; g_WITH_BYTE_ENABLE : boolean := false; g_ADDR_CONFLICT_RESOLUTION : string := "read_first"; @@ -60,6 +59,9 @@ entity xwb_fofb_processing is -- Fixed point representation for output g_OUT_FIXED : natural := 26; + -- Extra bits for accumulator + g_EXTRA_WIDTH : natural := 4; + -- Number of channels g_CHANNELS : natural := 8; @@ -108,7 +110,6 @@ begin cmp_wb_fofb_processing : wb_fofb_processing generic map( -- Standard parameters of generic_dpram - g_DATA_WIDTH => g_DATA_WIDTH, g_SIZE => g_SIZE, g_WITH_BYTE_ENABLE => g_WITH_BYTE_ENABLE, g_ADDR_CONFLICT_RESOLUTION => g_ADDR_CONFLICT_RESOLUTION, @@ -128,6 +129,8 @@ begin g_C_WIDTH => g_C_WIDTH, -- Fixed point representation for output g_OUT_FIXED => g_OUT_FIXED, + -- Extra bits for accumulator + g_EXTRA_WIDTH => g_EXTRA_WIDTH, -- Wishbone parameters g_INTERFACE_MODE => g_INTERFACE_MODE, diff --git a/hdl/sim/regs/wb_fofb_processing_regs.vh b/hdl/sim/regs/wb_fofb_processing_regs.vh index 0e97b00a..2ad26bd4 100644 --- a/hdl/sim/regs/wb_fofb_processing_regs.vh +++ b/hdl/sim/regs/wb_fofb_processing_regs.vh @@ -1,6 +1,6 @@ -`define WB_FOFB_PROCESSING_SIZE 12 -`define ADDR_WB_FOFB_PROCESSING_RAM_COEFF_DAT 'h0 -`define ADDR_WB_FOFB_PROCESSING_RAM_COEFF_ADDR 'h4 -`define ADDR_WB_FOFB_PROCESSING_RAM_WRITE 'h8 -`define WB_FOFB_PROCESSING_RAM_WRITE_ENABLE_OFFSET 0 -`define WB_FOFB_PROCESSING_RAM_WRITE_ENABLE 'h1 +`define WB_FOFB_PROCESSING_REGS_SIZE 12 +`define ADDR_WB_FOFB_PROCESSING_REGS_RAM_COEFF_DAT 'h0 +`define ADDR_WB_FOFB_PROCESSING_REGS_RAM_COEFF_ADDR 'h4 +`define ADDR_WB_FOFB_PROCESSING_REGS_RAM_WRITE 'h8 +`define WB_FOFB_PROCESSING_REGS_RAM_WRITE_ENABLE_OFFSET 0 +`define WB_FOFB_PROCESSING_REGS_RAM_WRITE_ENABLE 'h1 diff --git a/hdl/testbench/fofb_processing/dot_tb.vhd b/hdl/testbench/fofb_processing/dot_tb.vhd index 1f64607c..21b60ec6 100644 --- a/hdl/testbench/fofb_processing/dot_tb.vhd +++ b/hdl/testbench/fofb_processing/dot_tb.vhd @@ -72,7 +72,6 @@ begin generic map ( -- Standard parameters of generic_dpram - g_DATA_WIDTH => 32, g_SIZE => 512, g_WITH_BYTE_ENABLE => false, g_ADDR_CONFLICT_RESOLUTION => "read_first", diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 59a29635..2b603a66 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -435,6 +435,7 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_RAM_SIZE : natural := 2**NodeW; constant c_SP_OUT_WIDTH : natural := 16; constant c_OUT_FIXED : natural := 26; + constant c_EXTRA_WIDTH : natural := 4; constant c_dcc_fod_s : t_dot_prod_record_fod := (valid => '0', data => (others => '0'), @@ -1676,7 +1677,6 @@ begin generic map ( -- Standard parameters of generic_dpram - g_DATA_WIDTH => c_DATA_WIDTH, g_SIZE => c_RAM_SIZE, g_WITH_BYTE_ENABLE => false, g_ADDR_CONFLICT_RESOLUTION => "read_first", @@ -1695,6 +1695,8 @@ begin g_C_WIDTH => c_SP_OUT_WIDTH, -- Fixed point representation for output g_OUT_FIXED => c_OUT_FIXED, + -- Extra bits for accumulator + g_EXTRA_WIDTH => c_EXTRA_WIDTH, -- Number of channels g_CHANNELS => c_CHANNELS,