LDMIA instruction issues when using one of target registers as base address register

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What steps will reproduce the problem?
1. Try an ELF image that has somewhere an instruction of type:
         LDMIA r5!,{r3-r5}
2. Run the simulation while printing the r5 values or used a debugger
3. Monitor r5 values before and after this instruction

What is the expected output? What do you see instead?

Here the final value of register r5 is the incremented address and not loaded 
value. Per ARM guidelines, it should be loaded value:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/BABEFCIB.ht
ml

What version of the product are you using? On what operating system?
Current version of ARM ISS.

Please provide any additional information below.
I patched the problem with following fix and it seems to work well for me:

File armemu.cpp

void
arm::LoadMult(uint32_t instr, uint32_t address, uint32_t WBBase)
{

..
..
    if (m_Aborted) {
        if (BIT (21) && LHSReg != 15) {
            if (!(m_AbortSig))
            {
            }
        }
        TAKEABORT;
    }
    //Dont change the base address register if it is target as well
    //Vikas Paliwal ([email protected])
    //else if (BIT (21) && LHSReg != 15 ) {
    else if (BIT (21) && LHSReg != 15 && !BIT(LHSReg)) {
            LSBase = WBBase;
    }
    /* chy 2005-11-24, over */

}

It would be helpful if you could confirm if this is indeed an issue.

Regards,
Vikas

Original issue reported on code.google.com by [email protected] on 7 Sep 2011 at 8:44

Attachments:

• armemu.cpp