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Now, these are the microarchitectures supporting this instruction, while there can be skylake i3, there could also be skylake i5 and i7 depending on the manufacture process of a cpu it can be downgraded to any of these and will have disabled cores.
So unless I'm missing something here on what how these codes relates to the instruction introductory process, I think it should be changed to a list of instruction introductory microarchitecture and the family could vary, but it doesn't depend on the family.
It might be correct for the very first instructions where the jump from 80286 -> 80386 just introduced more instructions (and other stuff) but I think this rule breaks down later on, so I think it needs to be revised.
The text was updated successfully, but these errors were encountered:
(Reported by Kashio. His arguments are correct, the "processor family" codes comes from the past when the classification was simpler.)
The processor family which describes the instruction's introductory processor doesn't make sense.
The list of available families right now are:
Let's take for example instruction
CLFLUSHOPT
which was introduced in:According to https://en.wikichip.org/wiki/x86/persistent_memory_extensions
Now, these are the microarchitectures supporting this instruction, while there can be skylake i3, there could also be skylake i5 and i7 depending on the manufacture process of a cpu it can be downgraded to any of these and will have disabled cores.
So unless I'm missing something here on what how these codes relates to the instruction introductory process, I think it should be changed to a list of instruction introductory microarchitecture and the family could vary, but it doesn't depend on the family.
It might be correct for the very first instructions where the jump from 80286 -> 80386 just introduced more instructions (and other stuff) but I think this rule breaks down later on, so I think it needs to be revised.
The text was updated successfully, but these errors were encountered: