adc

ADC

Standard delta sigma ADC

Delta sigma ADCs can achieve a resolution of up to 15 bits at sampling rates of tens of kHz (TU Delft web page)

Lattice provide some information and IP:

• Leveraging FPGA and CPLD Digital Logic to Implement ADC Converter, Lattice Semiconductor White Paper, March 2010
• Lattice has ∆∑ IP for the MachXO and XP2 families. The design uses about 60 LUTs and achieves a sample rate of 7.63kHz (62.5MHz clock). See Simple Sigma-Delta ADC (archive.org). It looks like the IP will run on an iCE40 as well.

Using TDCs

Much more interesting :-)

Very high sample rates can be achieved.

• A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology.
• TU Delft has a nice website FPGA designs forreconfigurable converters:
  • Basic FPGA TDC design
  • 200 MS/s ADC implemented in a FPGA employing TDCs, from TU Delft web page.
• Low resource FPGA-based Time to Digital Converter, Balla et al., 2012 demonstrates a 32 channel TDC with a precision of 255 ps on a Xilinx Virtex-5.