diff --git a/src/modm/platform/core/stm32/module.lb b/src/modm/platform/core/stm32/module.lb
index de7c732d45..9f53cfc2ea 100644
--- a/src/modm/platform/core/stm32/module.lb
+++ b/src/modm/platform/core/stm32/module.lb
@@ -39,7 +39,7 @@ def prepare(module, options):
                 default="sram")
             )
 
-    module.depends(":platform:cortex-m")
+    module.depends(":platform:cortex-m", ":cmsis:device")
     return True
 
 
@@ -47,7 +47,8 @@ def build(env):
     target = env[":target"].identifier
     env.substitutions = {
         "target": target,
-        "vector_table_location": env.get(":platform:core:vector_table_location", "rom")
+        "vector_table_location": env.get(":platform:core:vector_table_location", "rom"),
+        "regs": env.query(":cmsis:device:registers"),
     }
     env.outbasepath = "modm/src/modm/platform/core"
     # startup helper code
diff --git a/src/modm/platform/core/stm32/startup_platform.c.in b/src/modm/platform/core/stm32/startup_platform.c.in
index 85085967d8..b3dd623ebb 100644
--- a/src/modm/platform/core/stm32/startup_platform.c.in
+++ b/src/modm/platform/core/stm32/startup_platform.c.in
@@ -28,75 +28,30 @@
 void
 __modm_initialize_platform(void)
 {
+%% if regs.set("RCC", "APB\d?ENR\d?", "SYSCFG.*?EN|AFIOEN")
 	// Enable SYSCFG
-%% if target.family in ["c0", "g0"]
-	RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN; __DSB();
-%% elif target.family == "f0"
-	RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; __DSB();
-%% elif target.family == "f1"
-	RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; __DSB();
-%% elif target.family == "h7"
-	RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; __DSB();
-%% elif target.family == "u5"
-	RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; __DSB();
-%% else
-	RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; __DSB();
+	{{regs.result}}
 %% endif
-
+%% if regs.set("RCC", "A[HP]B\d?ENR\d?", "(?:PWR|BKP)EN")
 	// Enable power to backup domain
-%% if target.family == "f1"
-	RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN; __DSB();
-%% elif target.family in ["f0", "f2", "f3", "f4", "f7", "l0", "l1"]
-	RCC->APB1ENR |= RCC_APB1ENR_PWREN; __DSB();
-%% elif target.family in ["c0", "g0", "u0"]
-	RCC->APBENR1 |= RCC_APBENR1_PWREN; __DSB();
-%% elif target.family in ["g4", "l4", "l5"]
-	RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN; __DSB();
-%% elif target.family == "u5"
-	RCC->AHB3ENR |= RCC_AHB3ENR_PWREN; __DSB();
+	{{regs.result}} __DSB();
 %% endif
-
-%% if target.family in ["f0", "f1", "f2", "f3", "f4", "l0", "l1"]
-	PWR->CR |= PWR_CR_DBP;
-%% elif target.family in ["f7", "g0", "g4", "h7", "l4", "l5", "u0", "wb", "wl"]
-	PWR->CR1 |= PWR_CR1_DBP;
-%% elif target.family == "h5"
-	PWR->DBPCR |= PWR_DBPCR_DBP;
-%% elif target.family in ["u5", "wba"]
-	PWR->DBPR |= PWR_DBPR_DBP;
+%% if regs.set("PWR", ".*?", "DBP")
+	// Enable access to backup domain
+	{{regs.result}}
 %% endif
-
-%% if target.family == "f4"
-	// Only the more powerful F4 targets have CCM or Backup SRAM
-#ifdef RCC_AHB1ENR_CCMDATARAMEN
-	// Enable Core Coupled Memory (CCM) and backup SRAM (BKPSRAM)
-	RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN | RCC_AHB1ENR_BKPSRAMEN;
-#endif
-%% elif target.family == "f7"
+%% if regs.set("RCC", "A[HP]B\d?ENR\d?", "(?:BKPS?|DTCM|CCMDATA)RAM\d?EN")
+	// Enable internal memories
+	{{regs.result}}
+%% endif
+%% if regs.set("PWR|RCC", "CR2|SVMCR", ".*?SV")
+	// Enable VDDIO voltages
+	{{regs.result}}
+%% endif
+%% if regs.search("RCC_DCKCFGR2_.*?")
 	// Reset from DFU settings to reset values.
 	RCC->DCKCFGR2 = 0;
-	// Enable Data Tighly Coupled Memory (DTCM) and backup SRAM (BKPSRAM)
-	RCC->AHB1ENR |= RCC_AHB1ENR_DTCMRAMEN | RCC_AHB1ENR_BKPSRAMEN;
-%% elif target.family == "h7"
-	// Enable all SRAMs
-	%% if target.name[0].isnumeric()
-	RCC->AHB2ENR |= RCC_AHB2ENR_SRAM1EN | RCC_AHB2ENR_SRAM2EN;
-	%% else
-	RCC->AHB2ENR |= RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN;
-	%% endif
-	RCC->AHB4ENR |= RCC_AHB4ENR_BKPRAMEN;
-%% elif target.family in ["g4", "l4", "l5"]
-#ifdef PWR_CR2_IOSV
-	// Enable VDDIO2
-	PWR->CR2 |= PWR_CR2_IOSV;
-#endif
-%% elif target.family == "u5"
-	// Enable power for VDDIO2 and USB
-	PWR->SVMCR |= PWR_SVMCR_ASV | PWR_SVMCR_IO2SV | PWR_SVMCR_USV;
-	// Enable Backup SRAM (BKPSRAM)
-	RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
 %% endif
-
 %% if vector_table_location == "ram"
 	__DSB();
 	// Remap SRAM to 0x0 for vector table relocation without VTOR register