diff --git a/impl/mdtang_m60k_process_config.json b/impl/mdtang_m60k_process_config.json
new file mode 100644
index 0000000..d8164c0
--- /dev/null
+++ b/impl/mdtang_m60k_process_config.json
@@ -0,0 +1,90 @@
+{
+ "BACKGROUND_PROGRAMMING" : "off",
+ "COMPRESS" : false,
+ "CPU" : false,
+ "CRC_CHECK" : true,
+ "Clock_Route_Order" : 0,
+ "Convert_SDP32_36_to_SDP16_18" : true,
+ "Correct_Hold_Violation" : true,
+ "DONE" : false,
+ "DOWNLOAD_SPEED" : "default",
+ "Disable_Insert_Pad" : false,
+ "ENABLE_CTP" : false,
+ "ENABLE_MERGE_MODE" : false,
+ "ENCRYPTION_KEY" : false,
+ "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
+ "ERROR_DECTION_AND_CORRECTION" : false,
+ "ERROR_DECTION_ONLY" : false,
+ "ERROR_INJECTION" : false,
+ "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
+ "Enable_DSRM" : false,
+ "FORMAT" : "binary",
+ "FREQUENCY_DIVIDER" : "1",
+ "Generate_Constraint_File_of_Ports" : false,
+ "Generate_IBIS_File" : false,
+ "Generate_Plain_Text_Timing_Report" : false,
+ "Generate_Post_PNR_Simulation_Model_File" : false,
+ "Generate_Post_Place_File" : false,
+ "Generate_SDF_File" : false,
+ "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
+ "Global_Freq" : "default",
+ "GwSyn_Loop_Limit" : 2000,
+ "HOTBOOT" : false,
+ "I2C" : false,
+ "I2C_SLAVE_ADDR" : "00",
+ "IncludePath" : [
+
+ ],
+ "Incremental_Compile" : "",
+ "Initialize_Primitives" : false,
+ "JTAG" : false,
+ "MODE_IO" : false,
+ "MSPI" : false,
+ "MSPI_JUMP" : false,
+ "MULTIBOOT_ADDRESS_WIDTH" : "24",
+ "MULTIBOOT_MODE" : "Normal",
+ "MULTIBOOT_SPI_FLASH_ADDRESS" : "000000",
+ "MULTIJUMP_ADDRESS_WIDTH" : "24",
+ "MULTIJUMP_MODE" : "Normal",
+ "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
+ "Multi_Boot" : false,
+ "OUTPUT_BASE_NAME" : "mdtang_m60k",
+ "POWER_ON_RESET_MONITOR" : true,
+ "PRINT_BSRAM_VALUE" : true,
+ "PROGRAM_DONE_BYPASS" : false,
+ "PlaceInRegToIob" : true,
+ "PlaceIoRegToIob" : true,
+ "PlaceOutRegToIob" : true,
+ "Place_Option" : "0",
+ "Process_Configuration_Verion" : "1.0",
+ "Promote_Physical_Constraint_Warning_to_Error" : true,
+ "READY" : false,
+ "RECONFIG_N" : false,
+ "Ram_RW_Check" : false,
+ "Replicate_Resources" : false,
+ "Report_Auto-Placed_Io_Information" : false,
+ "Route_Maxfan" : 23,
+ "Route_Option" : "0",
+ "Run_Timing_Driven" : true,
+ "SECURE_MODE" : false,
+ "SECURITY_BIT" : true,
+ "SEU_HANDLER" : false,
+ "SEU_HANDLER_CHECKSUM" : false,
+ "SEU_HANDLER_MODE" : "auto",
+ "SSPI" : false,
+ "STOP_SEU_HANDLER" : false,
+ "Show_All_Warnings" : false,
+ "Synthesize_tool" : "GowinSyn",
+ "TclPre" : "",
+ "TopModule" : "mdtang_top",
+ "USERCODE" : "default",
+ "Unused_Pin" : "As_input_tri_stated_with_pull_up",
+ "VCC" : "0.9",
+ "VCCAUX" : "3.3",
+ "VCCX" : "3.3",
+ "VHDL_Standard" : "VHDL_Std_1993",
+ "Verilog_Standard" : "Vlg_Std_Sysv2017",
+ "WAKE_UP" : "0",
+ "show_all_warnings" : false,
+ "turn_off_bg" : false
+}
\ No newline at end of file
diff --git a/m60k.tcl b/m60k.tcl
new file mode 100644
index 0000000..9434652
--- /dev/null
+++ b/m60k.tcl
@@ -0,0 +1,9 @@
+
+add_file -type cst "src/m138k/m138k.cst"
+add_file -type sdc "src/mdtang.sdc"
+set_device GW5AT-LV60PG484AC1/I0 -device_version B
+
+set_option -output_base_name mdtang-m60k
+
+source build.tcl
+
diff --git a/mdtang.gprj b/mdtang.gprj
index 22c97b8..84c70cb 100644
--- a/mdtang.gprj
+++ b/mdtang.gprj
@@ -80,7 +80,6 @@
         <File path="src/m138k/pll.v" type="file.verilog" enable="1"/>
         <File path="src/m138k/pll_27.v" type="file.verilog" enable="1"/>
         <File path="src/m138k/pll_74.v" type="file.verilog" enable="1"/>
-        <File path="src/m138k/ram68k.v" type="file.verilog" enable="1"/>
         <File path="src/mdtang_top.sv" type="file.verilog" enable="1"/>
         <File path="src/memory/rv_sdram_adapter.v" type="file.verilog" enable="1"/>
         <File path="src/memory/sdram.v" type="file.verilog" enable="1"/>
@@ -97,11 +96,6 @@
         <File path="src/t80/t80_mcode.v" type="file.verilog" enable="1"/>
         <File path="src/t80/t80_reg.v" type="file.verilog" enable="1"/>
         <File path="src/t80/t80s.v" type="file.verilog" enable="1"/>
-        <File path="src/tv80/tv80_alu.v" type="file.verilog" enable="1"/>
-        <File path="src/tv80/tv80_core.v" type="file.verilog" enable="1"/>
-        <File path="src/tv80/tv80_mcode.v" type="file.verilog" enable="1"/>
-        <File path="src/tv80/tv80_reg.v" type="file.verilog" enable="1"/>
-        <File path="src/tv80/tv80s.v" type="file.verilog" enable="1"/>
         <File path="src/vdp/vdp.v" type="file.verilog" enable="1"/>
         <File path="src/vdp/vdp_common.v" type="file.verilog" enable="1"/>
         <File path="src/vdp/vram.v" type="file.verilog" enable="1"/>
diff --git a/mdtang_m60k.gprj b/mdtang_m60k.gprj
new file mode 100644
index 0000000..b68c212
--- /dev/null
+++ b/mdtang_m60k.gprj
@@ -0,0 +1,106 @@
+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE gowin-fpga-project>
+<Project>
+    <Template>FPGA</Template>
+    <Version>5</Version>
+    <Device name="GW5AT-60B" pn="GW5AT-LV60PG484AC1/I0">gw5at60b-002</Device>
+    <FileList>
+        <File path="src/common/dpram.v" type="file.verilog" enable="1"/>
+        <File path="src/common/dpram32_block.v" type="file.verilog" enable="1"/>
+        <File path="src/common/dpram_block.v" type="file.verilog" enable="1"/>
+        <File path="src/fx68k/fx68k.sv" type="file.verilog" enable="1"/>
+        <File path="src/fx68k/fx68kAlu.sv" type="file.verilog" enable="1"/>
+        <File path="src/fx68k/uaddrPla.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/audio_info_frame.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/audio_sample_packet.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/hdmi.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/packet_assembler.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/packet_picker.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/serializer.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
+        <File path="src/iosys/dualshock_controller.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/framebuffer.sv" type="file.verilog" enable="1"/>
+        <File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/iosys.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/picorv32.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/simplespimaster1x.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/simpleuart.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/spi_master.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/spiflash.v" type="file.verilog" enable="1"/>
+        <File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/adpcm/jt10_adpcm_div.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_acc.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_csr.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_div.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_dout.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg_cnt.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg_comb.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg_ctrl.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg_final.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg_pure.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_eg_step.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_exprom.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_kon.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_lfo.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_logsin.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_mmr.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_mod.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_op.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pcm_interpol.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pg.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pg_comb.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pg_dt.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pg_inc.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pg_sum.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_pm.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_reg.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_rst.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_sh.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_sh24.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_sh_rst.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_single_acc.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_sumch.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_timers.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/jt12_top.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/mixer/jt12_comb.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/mixer/jt12_decim.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/mixer/jt12_fm_uprate.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/mixer/jt12_genmix.v" type="file.verilog" enable="1"/>
+        <File path="src/jt12/mixer/jt12_interpol.v" type="file.verilog" enable="1"/>
+        <File path="src/jt89/jt89.v" type="file.verilog" enable="1"/>
+        <File path="src/jt89/jt89_mixer.v" type="file.verilog" enable="1"/>
+        <File path="src/jt89/jt89_noise.v" type="file.verilog" enable="1"/>
+        <File path="src/jt89/jt89_tone.v" type="file.verilog" enable="1"/>
+        <File path="src/jt89/jt89_vol.v" type="file.verilog" enable="1"/>
+        <File path="src/m138k/pll.v" type="file.verilog" enable="1"/>
+        <File path="src/m138k/pll_27.v" type="file.verilog" enable="1"/>
+        <File path="src/m138k/pll_74.v" type="file.verilog" enable="1"/>
+        <File path="src/mdtang_top.sv" type="file.verilog" enable="1"/>
+        <File path="src/memory/rv_sdram_adapter.v" type="file.verilog" enable="1"/>
+        <File path="src/memory/sdram.v" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/audio_iir_filter.v" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/fourway.v" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/gen_io.sv" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/genesis_lpf.v" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/lightgun.sv" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/multitap.sv" type="file.verilog" enable="1"/>
+        <File path="src/peripherals/teamplayer.sv" type="file.verilog" enable="1"/>
+        <File path="src/system.sv" type="file.verilog" enable="1"/>
+        <File path="src/t80/t80.v" type="file.verilog" enable="1"/>
+        <File path="src/t80/t80_alu.v" type="file.verilog" enable="1"/>
+        <File path="src/t80/t80_mcode.v" type="file.verilog" enable="1"/>
+        <File path="src/t80/t80_reg.v" type="file.verilog" enable="1"/>
+        <File path="src/t80/t80s.v" type="file.verilog" enable="1"/>
+        <File path="src/vdp/vdp.v" type="file.verilog" enable="1"/>
+        <File path="src/vdp/vdp_common.v" type="file.verilog" enable="1"/>
+        <File path="src/vdp/vram.v" type="file.verilog" enable="1"/>
+        <File path="src/m138k/m138k.cst" type="file.cst" enable="1"/>
+        <File path="src/cpu.gao" type="file.gao" enable="0"/>
+        <File path="src/iosys.gao" type="file.gao" enable="0"/>
+    </FileList>
+</Project>
diff --git a/verilator/README.md b/verilator/README.md
new file mode 100644
index 0000000..02eb240
--- /dev/null
+++ b/verilator/README.md
@@ -0,0 +1,17 @@
+
+## MDTang simulation suite
+
+This directory contains a verilator-based RTL simulator for MDTang.
+
+You can run the simulation as follows,
+
+```
+make
+ln -s obj_dir/Vmdtang_top sim
+ln -s ../src/fx68k/*.mem .
+./sim hello.bin
+```
+
+You can replace `hello.bin` with any game rom or test rom. Then follow instructions printed by the simulator for gamepad input, tracing and etc.
+
+You can also get sound output with `make audio`.
\ No newline at end of file