From 84f09ae3113cec140c20c643a779d07d2008ad32 Mon Sep 17 00:00:00 2001 From: Nathaniel Mitchell Date: Tue, 10 Dec 2024 14:50:53 -0800 Subject: [PATCH] Update portio HAL to import halbase and simplify api Signed-off-by: Nathaniel Mitchell --- chipsec/cfg/parsers/registers/io.py | 4 +- chipsec/cfg/parsers/registers/iobar.py | 4 +- chipsec/hal/common/cmos.py | 24 +++--- chipsec/hal/common/ec.py | 22 ++--- chipsec/hal/common/interrupts.py | 6 +- chipsec/hal/common/io.py | 111 ++++++++++++------------- chipsec/hal/common/iobar.py | 8 +- chipsec/hal/intel/spi.py | 69 +++++++-------- chipsec/library/exceptions.py | 2 + chipsec/modules/tools/vmm/iofuzz.py | 26 +++--- chipsec/modules/tools/vmm/pcie_fuzz.py | 18 ++-- chipsec/modules/tools/vmm/venom.py | 4 +- chipsec/utilcmd/io_cmd.py | 20 +---- 13 files changed, 150 insertions(+), 168 deletions(-) diff --git a/chipsec/cfg/parsers/registers/io.py b/chipsec/cfg/parsers/registers/io.py index ea16efcf28..5a7f696d15 100644 --- a/chipsec/cfg/parsers/registers/io.py +++ b/chipsec/cfg/parsers/registers/io.py @@ -59,10 +59,10 @@ def read(self): """Read the object""" self.logger.log_debug(f'reading {self.name}') _cs = cs() - self.value = _cs.hals.PortIO.read_port(self.io_port, self.size) + self.value = _cs.hals.Io.read(self.io_port, self.size) return self.value def write(self, value): """Write the object""" _cs = cs() - _cs.hals.PortIO.write_port(self.io_port, value, self.size) + _cs.hals.Io.write(self.io_port, value, self.size) diff --git a/chipsec/cfg/parsers/registers/iobar.py b/chipsec/cfg/parsers/registers/iobar.py index c0c7866c67..4020d81328 100644 --- a/chipsec/cfg/parsers/registers/iobar.py +++ b/chipsec/cfg/parsers/registers/iobar.py @@ -67,7 +67,7 @@ def read(self): if self.io_port is None: (self.bar_base, self.bar_size) = _cs.hals.PortIObar.get_IO_BAR_base_address(self.bar, self.instance) self.io_port = self.bar_base + self.offset - self.value = _cs.hals.PortIO.read_port(self.io_port, self.size) + self.value = _cs.hals.Io.read(self.io_port, self.size) self.logger.log_debug('done reading') return self.value @@ -77,4 +77,4 @@ def write(self, value): if self.io_port is None: (self.bar_base, self.bar_size) = _cs.hals.PortIObar.get_IO_BAR_base_address(self.bar, self.instance.instance) self.io_port = self.bar_base + self.offset - _cs.hals.PortIO.write_port(self.io_port, value, self.size) + _cs.hals.Io.write(self.io_port, value, self.size) diff --git a/chipsec/hal/common/cmos.py b/chipsec/hal/common/cmos.py index 867e106893..7b9d1a4904 100644 --- a/chipsec/hal/common/cmos.py +++ b/chipsec/hal/common/cmos.py @@ -52,35 +52,35 @@ def __init__(self, cs): super(CMOS, self).__init__(cs) def read_cmos_high(self, offset: int) -> int: - self.cs.hals.PortIO.write_port_byte(CMOS_ADDR_PORT_HIGH, offset) - return self.cs.hals.PortIO.read_port_byte(CMOS_DATA_PORT_HIGH) + self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, offset) + return self.cs.hals.Io.read(CMOS_DATA_PORT_HIGH) def write_cmos_high(self, offset: int, value: int) -> None: - self.cs.hals.PortIO.write_port_byte(CMOS_ADDR_PORT_HIGH, offset) - self.cs.hals.PortIO.write_port_byte(CMOS_DATA_PORT_HIGH, value) + self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, offset) + self.cs.hals.Io.write(CMOS_DATA_PORT_HIGH, value) def read_cmos_low(self, offset: int) -> int: - self.cs.hals.PortIO.write_port_byte(CMOS_ADDR_PORT_LOW, 0x80 | offset) - return self.cs.hals.PortIO.read_port_byte(CMOS_DATA_PORT_LOW) + self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, 0x80 | offset) + return self.cs.hals.Io.read(CMOS_DATA_PORT_LOW) def write_cmos_low(self, offset: int, value: int) -> None: - self.cs.hals.PortIO.write_port_byte(CMOS_ADDR_PORT_LOW, offset) - self.cs.hals.PortIO.write_port_byte(CMOS_DATA_PORT_LOW, value) + self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, offset) + self.cs.hals.Io.write(CMOS_DATA_PORT_LOW, value) def dump_low(self) -> List[int]: cmos_buf = [0xFF] * 0x80 - orig = self.cs.hals.PortIO.read_port_byte(CMOS_ADDR_PORT_LOW) + orig = self.cs.hals.Io.read(CMOS_ADDR_PORT_LOW) for off in range(0x80): cmos_buf[off] = self.read_cmos_low(off) - self.cs.hals.PortIO.write_port_byte(CMOS_ADDR_PORT_LOW, orig) + self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, orig) return cmos_buf def dump_high(self) -> List[int]: cmos_buf = [0xFF] * 0x80 - orig = self.cs.hals.PortIO.read_port_byte(CMOS_ADDR_PORT_HIGH) + orig = self.cs.hals.Io.read(CMOS_ADDR_PORT_HIGH) for off in range(0x80): cmos_buf[off] = self.read_cmos_high(off) - self.cs.hals.PortIO.write_port_byte(CMOS_ADDR_PORT_HIGH, orig) + self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, orig) return cmos_buf def dump(self) -> None: diff --git a/chipsec/hal/common/ec.py b/chipsec/hal/common/ec.py index 03eafdd11c..0b44e7088d 100644 --- a/chipsec/hal/common/ec.py +++ b/chipsec/hal/common/ec.py @@ -84,29 +84,29 @@ class EC(hal_base.HALBase): # Wait for EC input buffer empty def _wait_ec_inbuf_empty(self) -> bool: to = 1000 - while (self.cs.hals.PortIO.read_port_byte(IO_PORT_EC_STATUS) & EC_STS_IBF) and to: + while (self.cs.hals.Io.read(IO_PORT_EC_STATUS) & EC_STS_IBF) and to: to = to - 1 return True # Wait for EC output buffer full def _wait_ec_outbuf_full(self) -> bool: to = 1000 - while not (self.cs.hals.PortIO.read_port_byte(IO_PORT_EC_STATUS) & EC_STS_OBF) and to: + while not (self.cs.hals.Io.read(IO_PORT_EC_STATUS) & EC_STS_OBF) and to: to = to - 1 return True def write_command(self, command: int) -> None: self._wait_ec_inbuf_empty() - return self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_COMMAND, command) + return self.cs.hals.Io.write(IO_PORT_EC_COMMAND, command) def write_data(self, data: int) -> None: self._wait_ec_inbuf_empty() - return self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_DATA, data) + return self.cs.hals.Io.write(IO_PORT_EC_DATA, data) def read_data(self) -> Optional[int]: if not self._wait_ec_outbuf_full(): return None - return self.cs.hals.PortIO.read_port_byte(IO_PORT_EC_DATA) + return self.cs.hals.Io.read(IO_PORT_EC_DATA) def read_memory(self, offset: int) -> Optional[int]: self.write_command(EC_COMMAND_ACPI_READ) @@ -167,17 +167,17 @@ def write_range(self, start_offset: int, buffer: bytes) -> bool: # EC Intex I/O access # def read_idx(self, offset: int) -> int: - self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF) - self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF) - value = self.cs.hals.PortIO.read_port_byte(IO_PORT_EC_INDEX_DATA) + self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF) + self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF) + value = self.cs.hals.Io.read(IO_PORT_EC_INDEX_DATA) self.logger.log_hal(f'[ec] index read: offset 0x{offset:02X} > 0x{value:02X}:') return value def write_idx(self, offset: int, value: int) -> bool: self.logger.log_hal(f'[ec] index write: offset 0x{offset:02X} < 0x{value:02X}:') - self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF) - self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF) - self.cs.hals.PortIO.write_port_byte(IO_PORT_EC_INDEX_DATA, value & 0xFF) + self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF) + self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF) + self.cs.hals.Io.write(IO_PORT_EC_INDEX_DATA, value & 0xFF) return True diff --git a/chipsec/hal/common/interrupts.py b/chipsec/hal/common/interrupts.py index ab40f834e3..0c4d7787ac 100644 --- a/chipsec/hal/common/interrupts.py +++ b/chipsec/hal/common/interrupts.py @@ -76,14 +76,14 @@ def send_SW_SMI_timed(self, thread_id: int, SMI_code_port_value: int, SMI_data_p def send_SMI_APMC(self, SMI_code_port_value: int, SMI_data_port_value: int) -> None: logger().log_hal(f"[intr] sending SMI via APMC ports: code 0xB2 <- 0x{SMI_code_port_value:02X}, data 0xB3 <- 0x{SMI_data_port_value:02X}") - self.cs.hals.PortIO.write_port_byte(SMI_DATA_PORT, SMI_data_port_value) - return self.cs.hals.PortIO.write_port_byte(SMI_APMC_PORT, SMI_code_port_value) + self.cs.hals.Io.write_port_byte(SMI_DATA_PORT, SMI_data_port_value) + return self.cs.hals.Io.write_port_byte(SMI_APMC_PORT, SMI_code_port_value) def send_NMI(self) -> None: logger().log_hal("[intr] Sending NMI# through TCO1_CTL[NMI_NOW]") reg, ba = self.cs.device.get_IO_space("TCOBASE") tcobase = self.cs.register.read_field(reg, ba) - return self.cs.hals.PortIO.write_port_byte(tcobase + NMI_TCO1_CTL + 1, NMI_NOW) + return self.cs.hals.Io.write_port_byte(tcobase + NMI_TCO1_CTL + 1, NMI_NOW) def find_ACPI_SMI_Buffer(self) -> Optional[UEFI_TABLE.CommBuffInfo]: logger().log_hal("Parsing ACPI tables to identify Communication Buffer") diff --git a/chipsec/hal/common/io.py b/chipsec/hal/common/io.py index 9a9bd3c7ff..48df6ce17a 100644 --- a/chipsec/hal/common/io.py +++ b/chipsec/hal/common/io.py @@ -23,92 +23,87 @@ Access to Port I/O usage: - >>> read_port_byte( 0x61 ) - >>> read_port_word( 0x61 ) - >>> read_port_dword( 0x61 ) - >>> write_port_byte( 0x71, 0 ) - >>> write_port_word( 0x71, 0 ) - >>> write_port_dword( 0x71, 0 ) + >>> read(0x61, 1) + >>> read_port_byte(0x61) + >>> read_port_word(0x61) + >>> read_port_dword(0x61) + >>> read_range(0x71, 0x4, 1) + >>> dump_range(0x71, 0x4, 1) + >>> write(0x71, 0, 1) + >>> write_port_byte(0x61, 0xAA) + >>> write_port_word(0x61, 0xAAAA) + >>> write_port_dword(0x61, 0xAAAAAAAA) + """ from typing import List +from chipsec.hal.hal_base import HALBase +from chipsec.library.exceptions import SizeRuntimeError from chipsec.library.logger import logger -class PortIO: #TODO: Refactor to derive from HALBase +class Io(HALBase): def __init__(self, cs): + super(Io, self).__init__(cs) self.helper = cs.helper - self.cs = cs + self.valid_sizes = [1, 2, 4] - def _read_port(self, io_port: int, size: int) -> int: + def read(self, io_port: int, size: int) -> int: + if size not in self.valid_sizes: + message = f'[HAL] [PortIO] Size of {size} is invalid. Valid sizes: {self.valid_sizes}' + logger().log_bad(message) + raise SizeRuntimeError(message) value = self.helper.read_io_port(io_port, size) - if logger().HAL: - logger().log(f"[io] IN 0x{io_port:04X}: value = 0x{value:08X}, size = 0x{size:02X}") + logger().log_hal(f"[io] IN 0x{io_port:04X}: value = 0x{value:08X}, size = 0x{size:02X}") return value - def _write_port(self, io_port: int, value: int, size: int) -> int: - if logger().HAL: - logger().log(f"[io] OUT 0x{io_port:04X}: value = 0x{value:08X}, size = 0x{size:02X}") + def write(self, io_port: int, value: int, size: int) -> int: + if size not in self.valid_sizes: + message = f'[HAL] [PortIO] Size of {size} is invalid. Valid sizes: {self.valid_sizes}' + logger().log_bad(message) + raise SizeRuntimeError(message) + logger().log_hal(f"[io] OUT 0x{io_port:04X}: value = 0x{value:08X}, size = 0x{size:02X}") status = self.helper.write_io_port(io_port, value, size) return status - def read_port_dword(self, io_port: int) -> int: - value = self.helper.read_io_port(io_port, 4) - if logger().HAL: - logger().log(f"[io] reading dword from I/O port 0x{io_port:04X} -> 0x{value:08X}") - return value - - def read_port_word(self, io_port: int) -> int: - value = self.helper.read_io_port(io_port, 2) - if logger().HAL: - logger().log(f"[io] reading word from I/O port 0x{io_port:04X} -> 0x{value:04X}") - return value - - def read_port_byte(self, io_port: int) -> int: - value = self.helper.read_io_port(io_port, 1) - if logger().HAL: - logger().log(f"[io] reading byte from I/O port 0x{io_port:04X} -> 0x{value:02X}") - return value - - def write_port_byte(self, io_port: int, value: int) -> int: - if logger().HAL: - logger().log(f"[io] writing byte to I/O port 0x{io_port:04X} <- 0x{value:02X}") - status = self.helper.write_io_port(io_port, value, 1) - return status - - def write_port_word(self, io_port: int, value: int) -> int: - if logger().HAL: - logger().log(f"[io] writing word to I/O port 0x{io_port:04X} <- 0x{value:04X}") - status = self.helper.write_io_port(io_port, value, 2) - return status - - def write_port_dword(self, io_port: int, value: int) -> int: - if logger().HAL: - logger().log(f"[io] writing dword to I/O port 0x{io_port:04X} <- 0x{value:08X}") - status = self.helper.write_io_port(io_port, value, 4) - return status # # Read registers from I/O range # - def read_IO(self, range_base: int, range_size: int, size: int = 1) -> List[int]: + def read_range(self, range_base: int, range_size: int, size: int = 1) -> List[int]: n = range_size // size io_ports = [] for i in range(n): - io_ports.append(self._read_port(range_base + i * size, size)) + io_ports.append(self.read(range_base + i * size, size)) return io_ports # # Dump I/O range # - def dump_IO(self, range_base: int, range_size: int, size: int = 1) -> None: - n = range_size // size - fmt = f'0{size * 2:d}X' + def dump_range(self, range_base: int, range_size: int, size: int = 1) -> None: logger().log(f"[io] I/O register range [0x{range_base:04X}:0x{range_base:04X}+{range_size:04X}]:") - for i in range(n): - reg = self._read_port(range_base + i * size, size) - logger().log(f'+{size * i:04X}: {reg:{fmt}}') + read_ranges = self.read_range(range_base, range_size, size) + for i, read_val in enumerate(read_ranges): + logger().log(f'+{size * i:04X}: {read_val:{f'0{size * 2:d}X'}}') + + def read_port_byte(self, io_port: int) -> int: + return self.read(io_port, 1) + + def read_port_word(self, io_port: int) -> int: + return self.read(io_port, 2) + + def read_port_dword(self, io_port: int) -> int: + return self.read(io_port, 4) + + def write_port_byte(self, io_port: int, value: int) -> int: + return self.write(io_port, value, 1) + + def write_port_word(self, io_port: int, value: int) -> int: + return self.write(io_port, value, 2) + + def write_port_dword(self, io_port: int, value: int) -> int: + return self.write(io_port, value, 4) -haldata = {"arch":['FFFF'], 'name': ['PortIO']} +haldata = {"arch":['FFFF'], 'name': ['Io']} diff --git a/chipsec/hal/common/iobar.py b/chipsec/hal/common/iobar.py index 1244712482..fe85d522aa 100644 --- a/chipsec/hal/common/iobar.py +++ b/chipsec/hal/common/iobar.py @@ -115,7 +115,7 @@ def read_IO_BAR_reg(self, bar_name: str, offset: int, size: int) -> int: io_port = bar_base + offset if offset > bar_size and logger().HAL: logger().log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})') - value = self.cs.hals.PortIO._read_port(io_port, size) + value = self.cs.hals.Io.read(io_port, size) return value # @@ -128,7 +128,7 @@ def write_IO_BAR_reg(self, bar_name: str, offset: int, size: int, value: int) -> io_port = bar_base + offset if offset > bar_size and logger().HAL: logger().log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})') - return self.cs.hals.PortIO._write_port(io_port, value, size) + return self.cs.hals.Io.write(io_port, value, size) # # Check if I/O range is enabled by BAR name @@ -189,7 +189,7 @@ def read_IO_BAR(self, bar_name: str, size: int = 1) -> List[int]: n = range_size // size io_ports = [] for i in range(n): - io_ports.append(self.cs.hals.PortIO._read_port(range_base + i * size, size)) + io_ports.append(self.cs.hals.Io.read(range_base + i * size, size)) return io_ports # @@ -201,7 +201,7 @@ def dump_IO_BAR(self, bar_name: str, size: int = 1) -> None: fmt = f'0{size * 2:d}X' logger().log(f"[iobar] I/O BAR {bar_name}:") for i in range(n): - reg = self.cs.hals.PortIO._read_port(range_base + i * size, size) + reg = self.cs.hals.Io.read(range_base + i * size, size) logger().log(f'{size * i:+04X}: {reg:{fmt}}') diff --git a/chipsec/hal/intel/spi.py b/chipsec/hal/intel/spi.py index 2e12f9bd9c..4d7d05ef5d 100644 --- a/chipsec/hal/intel/spi.py +++ b/chipsec/hal/intel/spi.py @@ -198,8 +198,8 @@ class SPI(hal_base.HALBase): def __init__(self, cs): super(SPI, self).__init__(cs) self.instance = 0 + self.mmio = cs.hals.MMIO self.get_registers() - # self.mmio = cs.hals.MMIO # self.rcba_spi_base = self.get_SPI_MMIO_base() # We try to map SPIBAR in the process memory, this will increase the # speed of MMIO access later on. @@ -211,34 +211,34 @@ def __init__(self, cs): # Reading definitions of SPI flash controller registers # which are required to send SPI cycles once for performance reasons def get_registers(self) -> None: - self.hsfs = self.cs.register.get_list_by_name('8086.SPI.HSFS', self.instance) - self.hsfc = self.cs.register.get_list_by_name('8086.SPI.HSFC', self.instance) - self.faddr = self.cs.register.get_list_by_name('8086.SPI.FADDR', self.instance) - self.fdata0 = self.cs.register.get_list_by_name('8086.SPI.FDATA0', self.instance) - self.fdata1 = self.cs.register.get_list_by_name('8086.SPI.FDATA1', self.instance) - self.fdata2 = self.cs.register.get_list_by_name('8086.SPI.FDATA2', self.instance) - self.fdata3 = self.cs.register.get_list_by_name('8086.SPI.FDATA3', self.instance) - self.fdata4 = self.cs.register.get_list_by_name('8086.SPI.FDATA4', self.instance) - self.fdata5 = self.cs.register.get_list_by_name('8086.SPI.FDATA5', self.instance) - self.fdata6 = self.cs.register.get_list_by_name('8086.SPI.FDATA6', self.instance) - self.fdata7 = self.cs.register.get_list_by_name('8086.SPI.FDATA7', self.instance) - self.fdata8 = self.cs.register.get_list_by_name('8086.SPI.FDATA8', self.instance) - self.fdata9 = self.cs.register.get_list_by_name('8086.SPI.FDATA9', self.instance) - self.fdata10 = self.cs.register.get_list_by_name('8086.SPI.FDATA10', self.instance) - self.fdata11 = self.cs.register.get_list_by_name('8086.SPI.FDATA11', self.instance) - self.fdata12 = self.cs.register.get_list_by_name('8086.SPI.FDATA12', self.instance) - self.fdata13 = self.cs.register.get_list_by_name('8086.SPI.FDATA13', self.instance) - self.fdata14 = self.cs.register.get_list_by_name('8086.SPI.FDATA14', self.instance) - self.fdata15 = self.cs.register.get_list_by_name('8086.SPI.FDATA15', self.instance) - self.ptinx = self.cs.register.get_list_by_name('8086.SPI.PTINX', self.instance) - self.ptdata = self.cs.register.get_list_by_name('8086.SPI.PTDATA', self.instance) - self.fdoc = self.cs.register.get_list_by_name('8086.SPI.FDOC', self.instance) - self.fdod = self.cs.register.get_list_by_name('8086.SPI.FDOD', self.instance) - self.frap = self.cs.register.get_list_by_name('8086.SPI.FRAP', self.instance) - self.bfpr = self.cs.register.get_list_by_name('8086.SPI.BFPR', self.instance) - self.ble = self.cs.control.get_list_by_name('BiosLockEnable', self.instance) - self.bioswe = self.cs.control.get_list_by_name('BiosWriteEnable', self.instance) - self.smmbwp = self.cs.control.get_list_by_name('SmmBiosWriteProtection', self.instance) + self.hsfs = self.cs.register.get_instance_by_name('8086.SPI.HSFS', self.instance) + self.hsfc = self.cs.register.get_instance_by_name('8086.SPI.HSFC', self.instance) + self.faddr = self.cs.register.get_instance_by_name('8086.SPI.FADDR', self.instance) + self.fdata0 = self.cs.register.get_instance_by_name('8086.SPI.FDATA0', self.instance) + self.fdata1 = self.cs.register.get_instance_by_name('8086.SPI.FDATA1', self.instance) + self.fdata2 = self.cs.register.get_instance_by_name('8086.SPI.FDATA2', self.instance) + self.fdata3 = self.cs.register.get_instance_by_name('8086.SPI.FDATA3', self.instance) + self.fdata4 = self.cs.register.get_instance_by_name('8086.SPI.FDATA4', self.instance) + self.fdata5 = self.cs.register.get_instance_by_name('8086.SPI.FDATA5', self.instance) + self.fdata6 = self.cs.register.get_instance_by_name('8086.SPI.FDATA6', self.instance) + self.fdata7 = self.cs.register.get_instance_by_name('8086.SPI.FDATA7', self.instance) + self.fdata8 = self.cs.register.get_instance_by_name('8086.SPI.FDATA8', self.instance) + self.fdata9 = self.cs.register.get_instance_by_name('8086.SPI.FDATA9', self.instance) + self.fdata10 = self.cs.register.get_instance_by_name('8086.SPI.FDATA10', self.instance) + self.fdata11 = self.cs.register.get_instance_by_name('8086.SPI.FDATA11', self.instance) + self.fdata12 = self.cs.register.get_instance_by_name('8086.SPI.FDATA12', self.instance) + self.fdata13 = self.cs.register.get_instance_by_name('8086.SPI.FDATA13', self.instance) + self.fdata14 = self.cs.register.get_instance_by_name('8086.SPI.FDATA14', self.instance) + self.fdata15 = self.cs.register.get_instance_by_name('8086.SPI.FDATA15', self.instance) + self.ptinx = self.cs.register.get_instance_by_name('8086.SPI.PTINX', self.instance) + self.ptdata = self.cs.register.get_instance_by_name('8086.SPI.PTDATA', self.instance) + self.fdoc = self.cs.register.get_instance_by_name('8086.SPI.FDOC', self.instance) + self.fdod = self.cs.register.get_instance_by_name('8086.SPI.FDOD', self.instance) + self.frap = self.cs.register.get_instance_by_name('8086.SPI.FRAP', self.instance) + self.bfpr = self.cs.register.get_instance_by_name('8086.SPI.BFPR', self.instance) + self.ble = self.cs.control.get_instance_by_name('BiosLockEnable', self.instance) + self.bioswe = self.cs.control.get_instance_by_name('BiosWriteEnable', self.instance) + self.smmbwp = self.cs.control.get_instance_by_name('SmmBiosWriteProtection', self.instance) self.get_SPI_MMIO_base() # self.hsfs_off = self.cs.register.get_def("HSFS")['offset'] # self.hsfc_off = self.cs.register.get_def("HSFC")['offset'] @@ -274,8 +274,8 @@ def set_instance(self, instance: int) -> None: def get_SPI_MMIO_base(self) -> int: spi_base = 0 - if self.mmio.is_MMIO_BAR_defined('SPIBAR'): - (spi_base, _) = self.mmio.get_MMIO_BAR_base_address('SPIBAR') + if self.mmio.is_MMIO_BAR_defined('8086.SPI.SPIBAR'): + (spi_base, _) = self.mmio.get_MMIO_BAR_base_address('8086.SPI.SPIBAR') else: self.logger.log_hal('[spi] get_SPI_MMIO_base(): SPIBAR not defined. Returning spi_base = 0.') self.logger.log_hal(f'[spi] SPI MMIO base: 0x{spi_base:016X} (assuming below 4GB)') @@ -291,11 +291,12 @@ def get_SPI_region(self, spi_region_id: int) -> Tuple[int, int, int]: freg_name = SPI_REGION[spi_region_id] if not self.cs.register.is_defined(freg_name): return (0, 0, 0) - freg = self.cs.register.read(freg_name) + freg = self.cs.register.get_instance_by_name(freg_name, self.instance) + freg_val = freg.read() # Region Base corresponds to FLA bits 24:12 - range_base = self.cs.register.get_field(freg_name, freg, 'RB') << SPI_FLA_SHIFT + range_base = freg.get_field('RB') << SPI_FLA_SHIFT # Region Limit corresponds to FLA bits 24:12 - range_limit = self.cs.register.get_field(freg_name, freg, 'RL') << SPI_FLA_SHIFT + range_limit = freg.get_field('RL') << SPI_FLA_SHIFT # FLA bits 11:0 are assumed to be FFFh for the limit comparison range_limit |= SPI_FLA_PAGE_MASK return (range_base, range_limit, freg) diff --git a/chipsec/library/exceptions.py b/chipsec/library/exceptions.py index 9e66736d1b..1255e00420 100644 --- a/chipsec/library/exceptions.py +++ b/chipsec/library/exceptions.py @@ -76,6 +76,8 @@ class HALInitializationError (RuntimeError): class AcpiRuntimeError (RuntimeError): pass +class SizeRuntimeError (RuntimeError): + pass class CmosRuntimeError (RuntimeError): pass diff --git a/chipsec/modules/tools/vmm/iofuzz.py b/chipsec/modules/tools/vmm/iofuzz.py index 8c6ec42e05..2e17367a00 100644 --- a/chipsec/modules/tools/vmm/iofuzz.py +++ b/chipsec/modules/tools/vmm/iofuzz.py @@ -106,22 +106,22 @@ def fuzz_ports(self, iterations, write_count, random_order=False): self.logger.log(f'[*] Fuzzing I/O port 0x{io_addr:04X}') self.logger.log(' Reading port') - port_value = self.cs.hals.PortIO.read_port_byte(io_addr) + port_value = self.cs.hals.Io.read(io_addr) if _FUZZ_SPECIAL_VALUES: self.logger.log(' Writing special 1-2-4 byte values') try: - self.cs.hals.PortIO.write_port_byte(io_addr, port_value) - self.cs.hals.PortIO.write_port_byte(io_addr, (~port_value) & 0xFF) - self.cs.hals.PortIO.write_port_byte(io_addr, 0xFF) - self.cs.hals.PortIO.write_port_byte(io_addr, 0x00) - self.cs.hals.PortIO.write_port_byte(io_addr, 0x5A) - self.cs.hals.PortIO.write_port_word(io_addr, 0xFFFF) - self.cs.hals.PortIO.write_port_word(io_addr, 0x0000) - self.cs.hals.PortIO.write_port_word(io_addr, 0x5AA5) - self.cs.hals.PortIO.write_port_dword(io_addr, 0xFFFFFFFF) - self.cs.hals.PortIO.write_port_dword(io_addr, 0x00000000) - self.cs.hals.PortIO.write_port_word(io_addr, 0x5AA55AA5) + self.cs.hals.Io.write_port_byte(io_addr, port_value) + self.cs.hals.Io.write_port_byte(io_addr, (~port_value) & 0xFF) + self.cs.hals.Io.write_port_byte(io_addr, 0xFF) + self.cs.hals.Io.write_port_byte(io_addr, 0x00) + self.cs.hals.Io.write_port_byte(io_addr, 0x5A) + self.cs.hals.Io.write_port_word(io_addr, 0xFFFF) + self.cs.hals.Io.write_port_word(io_addr, 0x0000) + self.cs.hals.Io.write_port_word(io_addr, 0x5AA5) + self.cs.hals.Io.write_port_dword(io_addr, 0xFFFFFFFF) + self.cs.hals.Io.write_port_dword(io_addr, 0x00000000) + self.cs.hals.Io.write_port_word(io_addr, 0x5AA55AA5) except: pass @@ -129,7 +129,7 @@ def fuzz_ports(self, iterations, write_count, random_order=False): for v in range(MAX_PORT_VALUE + 1): for _ in range(write_count): try: - self.cs.hals.PortIO.write_port_byte(io_addr, v) + self.cs.hals.Io.write_port_byte(io_addr, v) except: pass diff --git a/chipsec/modules/tools/vmm/pcie_fuzz.py b/chipsec/modules/tools/vmm/pcie_fuzz.py index a9e1058237..bb607e4e3b 100644 --- a/chipsec/modules/tools/vmm/pcie_fuzz.py +++ b/chipsec/modules/tools/vmm/pcie_fuzz.py @@ -84,15 +84,15 @@ def fuzz_io_bar(self, bar, size=0x100): port_off = 0 # Issue 8/16/32-bit I/O requests with various values to all I/O ports (aligned and unaligned) for port_off in range(size): - port_value = self.cs.hals.PortIO.read_port_byte(bar + port_off) - self.cs.hals.PortIO.write_port_byte(bar + port_off, port_value) - self.cs.hals.PortIO.write_port_byte(bar + port_off, ~port_value & 0xFF) - self.cs.hals.PortIO.write_port_byte(bar + port_off, 0xFF) - self.cs.hals.PortIO.write_port_byte(bar + port_off, 0x00) - self.cs.hals.PortIO.write_port_word(bar + port_off, 0xFFFF) - self.cs.hals.PortIO.write_port_word(bar + port_off, 0x0000) - self.cs.hals.PortIO.write_port_dword(bar + port_off, 0xFFFFFFFF) - self.cs.hals.PortIO.write_port_dword(bar + port_off, 0x00000000) + port_value = self.cs.hals.Io.read(bar + port_off) + self.cs.hals.Io.write_port_byte(bar + port_off, port_value) + self.cs.hals.Io.write_port_byte(bar + port_off, ~port_value & 0xFF) + self.cs.hals.Io.write_port_byte(bar + port_off, 0xFF) + self.cs.hals.Io.write_port_byte(bar + port_off, 0x00) + self.cs.hals.Io.write_port_word(bar + port_off, 0xFFFF) + self.cs.hals.Io.write_port_word(bar + port_off, 0x0000) + self.cs.hals.Io.write_port_dword(bar + port_off, 0xFFFFFFFF) + self.cs.hals.Io.write_port_dword(bar + port_off, 0x00000000) def fuzz_offset(self, bar, reg_off, reg_value, is64bit): self.cs.hals.MMIO.write_MMIO_reg(bar, reg_off, reg_value) # same value diff --git a/chipsec/modules/tools/vmm/venom.py b/chipsec/modules/tools/vmm/venom.py index 7c3338241b..b65d1b4ee9 100644 --- a/chipsec/modules/tools/vmm/venom.py +++ b/chipsec/modules/tools/vmm/venom.py @@ -64,9 +64,9 @@ def __init__(self): BaseModule.__init__(self) def venom_impl(self): - self.cs.hals.PortIO.write_port_byte(FDC_PORT_DATA_FIFO, FD_CMD) + self.cs.hals.Io.write_port_byte(FDC_PORT_DATA_FIFO, FD_CMD) for _ in range(ITER_COUNT): - self.cs.hals.PortIO.write_port_byte(FDC_PORT_DATA_FIFO, FDC_CMD_WRVAL) + self.cs.hals.Io.write_port_byte(FDC_PORT_DATA_FIFO, FDC_CMD_WRVAL) return True def run(self, module_argv): diff --git a/chipsec/utilcmd/io_cmd.py b/chipsec/utilcmd/io_cmd.py index 8c5e528866..90591fa78f 100644 --- a/chipsec/utilcmd/io_cmd.py +++ b/chipsec/utilcmd/io_cmd.py @@ -75,28 +75,12 @@ def io_list(self) -> None: self._iobar.list_IO_BARs() def io_read(self) -> None: - if 0x1 == self._width: - value = self.cs.hals.PortIO.read_port_byte(self._port) - elif 0x2 == self._width: - value = self.cs.hals.PortIO.read_port_word(self._port) - elif 0x4 == self._width: - value = self.cs.hals.PortIO.read_port_dword(self._port) - else: - self.logger.log("Invalid read size requested. 1,2,4 supported") - return + value = self.cs.hals.Io.read(self._port, self._width) self.logger.log(f'[CHIPSEC] IN 0x{self._port:04X} -> 0x{value:08X} (size = 0x{self._width:02X})') return def io_write(self) -> None: - if 0x1 == self._width: - self.cs.hals.PortIO.write_port_byte(self._port, self._value) - elif 0x2 == self._width: - self.cs.hals.PortIO.write_port_word(self._port, self._value) - elif 0x4 == self._width: - self.cs.hals.PortIO.write_port_dword(self._port, self._value) - else: - self.logger.log("Invalid write size requested. 1,2,4 supported") - return + self.cs.hals.Io.write(self._port, self._value, self._width) self.logger.log( f'[CHIPSEC] OUT 0x{self._port:04X} <- 0x{self._value:08X} (size = 0x{self._width:02X})') return