From 0f920e6ba1974d9fa09d4247792529f67ca5feca Mon Sep 17 00:00:00 2001 From: dskleingeld <11743287+dskleingeld@users.noreply.github.com> Date: Thu, 22 Apr 2021 02:36:02 +0200 Subject: [PATCH 1/6] script to detect msb and lsb for all tasks --- fix_svd.py | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 fix_svd.py diff --git a/fix_svd.py b/fix_svd.py new file mode 100644 index 0000000..faa5faf --- /dev/null +++ b/fix_svd.py @@ -0,0 +1,77 @@ +#!/usr/bin/env python3.8 +import re +from typing import List, Optional, Tuple +from dataclasses import dataclass +from collections import namedtuple + + +lsb_re = re.compile(r"^\s+(\d)\s+$") +msb_re = re.compile(r"^\s+(\d)\s+$") + + +@dataclass +class TaskField: + lsb: int + msb: int + + @staticmethod + def from_lines(lines: List[str]): + lsb = lsb_re.match(lines[2]) + msb = msb_re.match(lines[3]) + if lsb is None or msb is None: + return None + + field = TaskField(int(lsb.group(1)), int(msb.group(1))) + return field + + +@dataclass +class Task: + reg_range: Tuple[int, int] + field: Optional[TaskField] + + @staticmethod + def from_lines(i: int, lines: List[str]): + # find end of register + reg_range = None + for j, line in enumerate(lines[i:]): + if "" in line: + reg_range = (i, i+j+1) + break + + if reg_range is None: + raise ValueError(f"register at line {i} has no end") + + # has field? + field = None + lines = lines[reg_range[0]:reg_range[1]] + for j, line in enumerate(lines): + if "" not in line: + continue + if "TASKS_" not in lines[j+1]: + continue + field = TaskField.from_lines(lines[j:]) + break + return Task(reg_range, field) + + +if __name__ == "__main__": + + file = open("nrf52840.svd", "r") + lines = file.readlines() + tasks = [] + + for i, line in enumerate(lines): + if "TASKS_" not in line: + continue + if "" not in lines[i-1]: + continue + + task = Task.from_lines(i, lines) + tasks.append(task) + + for task in tasks: + if task.field.lsb != 0: + print("not all tasks have lsb = 0") + if task.field.msb != 0: + print("not all tasks have msb = 0") From caa560c6fd41506582cae0436c45d2132062ee2e Mon Sep 17 00:00:00 2001 From: dskleingeld <11743287+dskleingeld@users.noreply.github.com> Date: Thu, 22 Apr 2021 12:35:17 +0200 Subject: [PATCH 2/6] script extended to fix TASKS_ entries --- fix_svd.py | 63 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/fix_svd.py b/fix_svd.py index faa5faf..27e05c8 100644 --- a/fix_svd.py +++ b/fix_svd.py @@ -2,11 +2,11 @@ import re from typing import List, Optional, Tuple from dataclasses import dataclass -from collections import namedtuple lsb_re = re.compile(r"^\s+(\d)\s+$") msb_re = re.compile(r"^\s+(\d)\s+$") +name_re = re.compile(r"^\s+(\w+)\s+$") @dataclass @@ -27,11 +27,18 @@ def from_lines(lines: List[str]): @dataclass class Task: + name: str reg_range: Tuple[int, int] field: Optional[TaskField] @staticmethod def from_lines(i: int, lines: List[str]): + # extract register name + name_match = name_re.match(lines[i]) + if name_match is None: + raise ValueError(f"register at line {i} has no name") + name = name_match.group(1) + # find end of register reg_range = None for j, line in enumerate(lines[i:]): @@ -52,13 +59,10 @@ def from_lines(i: int, lines: List[str]): continue field = TaskField.from_lines(lines[j:]) break - return Task(reg_range, field) - + return Task(name, reg_range, field) -if __name__ == "__main__": - file = open("nrf52840.svd", "r") - lines = file.readlines() +def extract_tasks(lines: List[str]) -> List[Task]: tasks = [] for i, line in enumerate(lines): @@ -70,8 +74,55 @@ def from_lines(i: int, lines: List[str]): task = Task.from_lines(i, lines) tasks.append(task) + return tasks + + +def check_task_assumptions(): + """ check if every TASKS_ register has a field with the same + name that has a single bit (lsb and msb, both zero) + """ + file = open("nrf52840.svd", "r") + lines = file.readlines() + tasks = extract_tasks(lines) + for task in tasks: + if task.field is None: + print("some tasks have no task field") + continue + if task.field.lsb != 0: print("not all tasks have lsb = 0") if task.field.msb != 0: print("not all tasks have msb = 0") + + +def to_insert(taskname: str, num_spaces: int) -> List[str]: + indent = "".ljust(num_spaces) + return ([ + indent + " \n", + indent + " \n", + indent + f" {taskname}\n", + indent + " 0\n", + indent + " 0\n", + indent + " \n", + indent + " \n"]) + + +if __name__ == "__main__": + check_task_assumptions() + + file = open("nrf52832.svd", "r") + lines = file.readlines() + tasks = extract_tasks(lines) + + # this assumes the fields key is not present + for task in reversed(tasks): + pos = task.reg_range[1] - 1 + reg_line = lines[task.reg_range[1]] + indent = len(reg_line) - len(reg_line.lstrip(" ")) + ins = to_insert(task.name, indent) + # print(ins) + lines[pos:pos] = ins + + file = open("nrf52832_fixed.svd", "w") + file.writelines(lines) From 31d4bad05dc79050ee5afbcc21a7831e68b08fa9 Mon Sep 17 00:00:00 2001 From: dskleingeld <11743287+dskleingeld@users.noreply.github.com> Date: Thu, 22 Apr 2021 12:45:07 +0200 Subject: [PATCH 3/6] expanded python script to also add fields to EVENTS_ registers --- fix_svd.py | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/fix_svd.py b/fix_svd.py index 27e05c8..8e677c7 100644 --- a/fix_svd.py +++ b/fix_svd.py @@ -26,7 +26,7 @@ def from_lines(lines: List[str]): @dataclass -class Task: +class Register: name: str reg_range: Tuple[int, int] field: Optional[TaskField] @@ -55,45 +55,46 @@ def from_lines(i: int, lines: List[str]): for j, line in enumerate(lines): if "" not in line: continue - if "TASKS_" not in lines[j+1]: + if ""+name not in lines[j+1]: continue field = TaskField.from_lines(lines[j:]) break - return Task(name, reg_range, field) + return Register(name, reg_range, field) -def extract_tasks(lines: List[str]) -> List[Task]: +def extract_registers(name_prompt: str, lines: List[str]) -> List[Register]: tasks = [] for i, line in enumerate(lines): - if "TASKS_" not in line: + # if "TASKS_" not in line: + if name_prompt not in line: continue if "" not in lines[i-1]: continue - task = Task.from_lines(i, lines) + task = Register.from_lines(i, lines) tasks.append(task) return tasks -def check_task_assumptions(): +def check_assumptions(name_prompt: str): """ check if every TASKS_ register has a field with the same name that has a single bit (lsb and msb, both zero) """ file = open("nrf52840.svd", "r") lines = file.readlines() - tasks = extract_tasks(lines) + tasks = extract_registers(name_prompt, lines) for task in tasks: if task.field is None: - print("some tasks have no task field") + print("some registers have no field") continue if task.field.lsb != 0: - print("not all tasks have lsb = 0") + print("not all registers have lsb = 0") if task.field.msb != 0: - print("not all tasks have msb = 0") + print("not all registers have msb = 0") def to_insert(taskname: str, num_spaces: int) -> List[str]: @@ -108,21 +109,24 @@ def to_insert(taskname: str, num_spaces: int) -> List[str]: indent + " \n"]) +TASK_PROMT = "TASKS_" +EVENT_PROMT = "EVENTS_" if __name__ == "__main__": - check_task_assumptions() + check_assumptions(TASK_PROMT) + check_assumptions(EVENT_PROMT) file = open("nrf52832.svd", "r") lines = file.readlines() - tasks = extract_tasks(lines) + registers = extract_registers(TASK_PROMT, lines) + registers += extract_registers(EVENT_PROMT, lines) + registers = sorted(registers, key=lambda r: r.reg_range[0]) # this assumes the fields key is not present - for task in reversed(tasks): + for task in reversed(registers): pos = task.reg_range[1] - 1 reg_line = lines[task.reg_range[1]] indent = len(reg_line) - len(reg_line.lstrip(" ")) - ins = to_insert(task.name, indent) - # print(ins) - lines[pos:pos] = ins + lines[pos:pos] = to_insert(task.name, indent) file = open("nrf52832_fixed.svd", "w") file.writelines(lines) From 608b4bd772ac769e4593b8993131afbf0945701c Mon Sep 17 00:00:00 2001 From: dskleingeld <11743287+dskleingeld@users.noreply.github.com> Date: Thu, 22 Apr 2021 14:01:32 +0200 Subject: [PATCH 4/6] let update use fixed svd --- update.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/update.sh b/update.sh index 95cb8c8..673772e 100755 --- a/update.sh +++ b/update.sh @@ -10,7 +10,7 @@ rustup component add rustfmt rm -rf src mkdir src -svd2rust -i ./nrf52832.svd +svd2rust -i ./nrf52832_fixed.svd form -i lib.rs -o src rm lib.rs cargo fmt From 3b115da0d28d55355ca181fe25fc5ed93af49229 Mon Sep 17 00:00:00 2001 From: dskleingeld <11743287+dskleingeld@users.noreply.github.com> Date: Thu, 22 Apr 2021 14:02:26 +0200 Subject: [PATCH 5/6] fixed svd and rebuilds crate --- nrf52832_fixed.svd | 44814 +++++++++++++++++++++++++ src/aar/events_end.rs | 40 +- src/aar/events_notresolved.rs | 40 +- src/aar/events_resolved.rs | 40 +- src/aar/tasks_start.rs | 30 +- src/aar/tasks_stop.rs | 30 +- src/ccm/events_endcrypt.rs | 40 +- src/ccm/events_endksgen.rs | 40 +- src/ccm/events_error.rs | 40 +- src/ccm/tasks_crypt.rs | 30 +- src/ccm/tasks_ksgen.rs | 30 +- src/ccm/tasks_stop.rs | 30 +- src/clock/events_ctto.rs | 40 +- src/clock/events_done.rs | 40 +- src/clock/events_hfclkstarted.rs | 40 +- src/clock/events_lfclkstarted.rs | 40 +- src/clock/tasks_cal.rs | 30 +- src/clock/tasks_ctstart.rs | 30 +- src/clock/tasks_ctstop.rs | 30 +- src/clock/tasks_hfclkstart.rs | 30 +- src/clock/tasks_hfclkstop.rs | 30 +- src/clock/tasks_lfclkstart.rs | 30 +- src/clock/tasks_lfclkstop.rs | 30 +- src/comp/events_cross.rs | 40 +- src/comp/events_down.rs | 40 +- src/comp/events_ready.rs | 40 +- src/comp/events_up.rs | 40 +- src/comp/tasks_sample.rs | 30 +- src/comp/tasks_start.rs | 30 +- src/comp/tasks_stop.rs | 30 +- src/ecb/events_endecb.rs | 40 +- src/ecb/events_errorecb.rs | 40 +- src/ecb/tasks_startecb.rs | 30 +- src/ecb/tasks_stopecb.rs | 30 +- src/gpiote/events_port.rs | 40 +- src/i2s/events_rxptrupd.rs | 40 +- src/i2s/events_stopped.rs | 40 +- src/i2s/events_txptrupd.rs | 40 +- src/i2s/tasks_start.rs | 30 +- src/i2s/tasks_stop.rs | 30 +- src/lpcomp/events_cross.rs | 40 +- src/lpcomp/events_down.rs | 40 +- src/lpcomp/events_ready.rs | 40 +- src/lpcomp/events_up.rs | 40 +- src/lpcomp/tasks_sample.rs | 30 +- src/lpcomp/tasks_start.rs | 30 +- src/lpcomp/tasks_stop.rs | 30 +- src/nfct/events_autocolresstarted.rs | 40 +- src/nfct/events_collision.rs | 40 +- src/nfct/events_endrx.rs | 40 +- src/nfct/events_endtx.rs | 40 +- src/nfct/events_error.rs | 40 +- src/nfct/events_fielddetected.rs | 40 +- src/nfct/events_fieldlost.rs | 40 +- src/nfct/events_ready.rs | 40 +- src/nfct/events_rxerror.rs | 40 +- src/nfct/events_rxframeend.rs | 40 +- src/nfct/events_rxframestart.rs | 40 +- src/nfct/events_selected.rs | 40 +- src/nfct/events_started.rs | 40 +- src/nfct/events_txframeend.rs | 40 +- src/nfct/events_txframestart.rs | 40 +- src/nfct/tasks_activate.rs | 30 +- src/nfct/tasks_disable.rs | 30 +- src/nfct/tasks_enablerxdata.rs | 30 +- src/nfct/tasks_goidle.rs | 30 +- src/nfct/tasks_gosleep.rs | 30 +- src/nfct/tasks_sense.rs | 30 +- src/nfct/tasks_starttx.rs | 30 +- src/pdm/events_end.rs | 40 +- src/pdm/events_started.rs | 40 +- src/pdm/events_stopped.rs | 40 +- src/pdm/tasks_start.rs | 30 +- src/pdm/tasks_stop.rs | 30 +- src/power/events_pofwarn.rs | 40 +- src/power/events_sleepenter.rs | 40 +- src/power/events_sleepexit.rs | 40 +- src/power/tasks_constlat.rs | 30 +- src/power/tasks_lowpwr.rs | 30 +- src/pwm0/events_loopsdone.rs | 40 +- src/pwm0/events_pwmperiodend.rs | 40 +- src/pwm0/events_stopped.rs | 40 +- src/pwm0/tasks_nextstep.rs | 30 +- src/pwm0/tasks_stop.rs | 30 +- src/qdec/events_accof.rs | 40 +- src/qdec/events_dblrdy.rs | 40 +- src/qdec/events_reportrdy.rs | 40 +- src/qdec/events_samplerdy.rs | 40 +- src/qdec/events_stopped.rs | 40 +- src/qdec/tasks_rdclracc.rs | 30 +- src/qdec/tasks_rdclrdbl.rs | 30 +- src/qdec/tasks_readclracc.rs | 30 +- src/qdec/tasks_start.rs | 30 +- src/qdec/tasks_stop.rs | 30 +- src/radio/events_address.rs | 40 +- src/radio/events_bcmatch.rs | 40 +- src/radio/events_crcerror.rs | 40 +- src/radio/events_crcok.rs | 40 +- src/radio/events_devmatch.rs | 40 +- src/radio/events_devmiss.rs | 40 +- src/radio/events_disabled.rs | 40 +- src/radio/events_end.rs | 40 +- src/radio/events_payload.rs | 40 +- src/radio/events_ready.rs | 40 +- src/radio/events_rssiend.rs | 40 +- src/radio/tasks_bcstart.rs | 30 +- src/radio/tasks_bcstop.rs | 30 +- src/radio/tasks_disable.rs | 30 +- src/radio/tasks_rssistart.rs | 30 +- src/radio/tasks_rssistop.rs | 30 +- src/radio/tasks_rxen.rs | 30 +- src/radio/tasks_start.rs | 30 +- src/radio/tasks_stop.rs | 30 +- src/radio/tasks_txen.rs | 30 +- src/rng/events_valrdy.rs | 40 +- src/rng/tasks_start.rs | 30 +- src/rng/tasks_stop.rs | 30 +- src/rtc0/events_ovrflw.rs | 40 +- src/rtc0/events_tick.rs | 40 +- src/rtc0/tasks_clear.rs | 30 +- src/rtc0/tasks_start.rs | 30 +- src/rtc0/tasks_stop.rs | 30 +- src/rtc0/tasks_trigovrflw.rs | 30 +- src/saadc/events_calibratedone.rs | 40 +- src/saadc/events_done.rs | 40 +- src/saadc/events_end.rs | 40 +- src/saadc/events_resultdone.rs | 40 +- src/saadc/events_started.rs | 40 +- src/saadc/events_stopped.rs | 40 +- src/saadc/tasks_calibrateoffset.rs | 30 +- src/saadc/tasks_sample.rs | 30 +- src/saadc/tasks_start.rs | 30 +- src/saadc/tasks_stop.rs | 30 +- src/spi0/events_ready.rs | 40 +- src/spim0/events_end.rs | 40 +- src/spim0/events_endrx.rs | 40 +- src/spim0/events_endtx.rs | 40 +- src/spim0/events_started.rs | 40 +- src/spim0/events_stopped.rs | 40 +- src/spim0/tasks_resume.rs | 30 +- src/spim0/tasks_start.rs | 30 +- src/spim0/tasks_stop.rs | 30 +- src/spim0/tasks_suspend.rs | 30 +- src/spis0/events_acquired.rs | 40 +- src/spis0/events_end.rs | 40 +- src/spis0/events_endrx.rs | 40 +- src/spis0/tasks_acquire.rs | 30 +- src/spis0/tasks_release.rs | 30 +- src/temp/events_datardy.rs | 40 +- src/temp/tasks_start.rs | 30 +- src/temp/tasks_stop.rs | 30 +- src/timer0/tasks_clear.rs | 30 +- src/timer0/tasks_count.rs | 30 +- src/timer0/tasks_shutdown.rs | 30 +- src/timer0/tasks_start.rs | 30 +- src/timer0/tasks_stop.rs | 30 +- src/timer3/tasks_clear.rs | 30 +- src/timer3/tasks_count.rs | 30 +- src/timer3/tasks_shutdown.rs | 30 +- src/timer3/tasks_start.rs | 30 +- src/timer3/tasks_stop.rs | 30 +- src/twi0/events_bb.rs | 40 +- src/twi0/events_error.rs | 40 +- src/twi0/events_rxdready.rs | 40 +- src/twi0/events_stopped.rs | 40 +- src/twi0/events_suspended.rs | 40 +- src/twi0/events_txdsent.rs | 40 +- src/twi0/tasks_resume.rs | 30 +- src/twi0/tasks_startrx.rs | 30 +- src/twi0/tasks_starttx.rs | 30 +- src/twi0/tasks_stop.rs | 30 +- src/twi0/tasks_suspend.rs | 30 +- src/twim0/events_error.rs | 40 +- src/twim0/events_lastrx.rs | 40 +- src/twim0/events_lasttx.rs | 40 +- src/twim0/events_rxstarted.rs | 40 +- src/twim0/events_stopped.rs | 40 +- src/twim0/events_suspended.rs | 40 +- src/twim0/events_txstarted.rs | 40 +- src/twim0/tasks_resume.rs | 30 +- src/twim0/tasks_startrx.rs | 30 +- src/twim0/tasks_starttx.rs | 30 +- src/twim0/tasks_stop.rs | 30 +- src/twim0/tasks_suspend.rs | 30 +- src/twis0/events_error.rs | 40 +- src/twis0/events_read.rs | 40 +- src/twis0/events_rxstarted.rs | 40 +- src/twis0/events_stopped.rs | 40 +- src/twis0/events_txstarted.rs | 40 +- src/twis0/events_write.rs | 40 +- src/twis0/tasks_preparerx.rs | 30 +- src/twis0/tasks_preparetx.rs | 30 +- src/twis0/tasks_resume.rs | 30 +- src/twis0/tasks_stop.rs | 30 +- src/twis0/tasks_suspend.rs | 30 +- src/uart0/events_cts.rs | 40 +- src/uart0/events_error.rs | 40 +- src/uart0/events_ncts.rs | 40 +- src/uart0/events_rxdrdy.rs | 40 +- src/uart0/events_rxto.rs | 40 +- src/uart0/events_txdrdy.rs | 40 +- src/uart0/tasks_startrx.rs | 30 +- src/uart0/tasks_starttx.rs | 30 +- src/uart0/tasks_stoprx.rs | 30 +- src/uart0/tasks_stoptx.rs | 30 +- src/uart0/tasks_suspend.rs | 30 +- src/uarte0/events_cts.rs | 40 +- src/uarte0/events_endrx.rs | 40 +- src/uarte0/events_endtx.rs | 40 +- src/uarte0/events_error.rs | 40 +- src/uarte0/events_ncts.rs | 40 +- src/uarte0/events_rxdrdy.rs | 40 +- src/uarte0/events_rxstarted.rs | 40 +- src/uarte0/events_rxto.rs | 40 +- src/uarte0/events_txdrdy.rs | 40 +- src/uarte0/events_txstarted.rs | 40 +- src/uarte0/events_txstopped.rs | 40 +- src/uarte0/tasks_flushrx.rs | 30 +- src/uarte0/tasks_startrx.rs | 30 +- src/uarte0/tasks_starttx.rs | 30 +- src/uarte0/tasks_stoprx.rs | 30 +- src/uarte0/tasks_stoptx.rs | 30 +- src/wdt/events_timeout.rs | 40 +- src/wdt/tasks_start.rs | 30 +- 224 files changed, 52361 insertions(+), 343 deletions(-) create mode 100644 nrf52832_fixed.svd diff --git a/nrf52832_fixed.svd b/nrf52832_fixed.svd new file mode 100644 index 0000000..0457d58 --- /dev/null +++ b/nrf52832_fixed.svd @@ -0,0 +1,44814 @@ + + + + Nordic Semiconductor + Nordic + nrf52 + nrf52 + 1 + nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA\n +\n +All rights reserved.\n +\n +Redistribution and use in source and binary forms, with or without modification,\n +are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form, except as embedded into a Nordic\n + Semiconductor ASA integrated circuit in a product or a software update for\n + such product, must reproduce the above copyright notice, this list of\n + conditions and the following disclaimer in the documentation and/or other\n + materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +4. This software, with or without modification, must only be used with a\n + Nordic Semiconductor ASA integrated circuit.\n +\n +5. Any software provided in binary form under this license must not be reverse\n + engineered, decompiled, modified and/or disassembled.\n +\n +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 1 + 3 + 0 + + system_nrf52 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory Information Configuration Registers + FICR + 0x10000000 + 32 + + 0 + 0x1000 + registers + + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0xFFFFFFFF + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0xFFFFFFFF + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 2 + 4 + DEVICEID[%s] + Description collection[0]: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 4 + 4 + ER[%s] + Description collection[0]: Encryption Root, word 0 + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption Root, word n + 0 + 31 + + + + + 4 + 4 + IR[%s] + Description collection[0]: Identity Root, word 0 + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 2 + 4 + DEVICEADDR[%s] + Description collection[0]: Device address 0 + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052832 + + + PART + Part code + 0 + 31 + + + N52832 + nRF52832 + 0x52832 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x004 + read-only + 0x41414142 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAAB + AAAB + 0x41414142 + + + AABA + AABA + 0x41414241 + + + AABB + AABB + 0x41414242 + + + AAB0 + AAB0 + 0x41414230 + + + AAE0 + AAE0 + 0x41414530 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0x00002000 + + + PACKAGE + Package option + 0 + 31 + + + QF + QFxx - 48-pin QFN + 0x2000 + + + CH + CHxx - 7x8 WLCSP 56 balls + 0x2001 + + + CI + CIxx - 7x8 WLCSP 56 balls + 0x2002 + + + CK + CKxx - 7x8 WLCSP 56 balls with backside coating for light protection + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0x00000040 + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0x00000200 + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + 3 + 4 + UNUSED0[%s] + Description collection[0]: Unspecified + 0x014 + read-write + + + + TEMP + Registers storing factory TEMP module linearization coefficients + 0x404 + + A0 + Slope definition A0. + 0x000 + read-only + 0x00000320 + + + A + A (slope definition) register. + 0 + 11 + + + + + A1 + Slope definition A1. + 0x004 + read-only + 0x00000343 + + + A + A (slope definition) register. + 0 + 11 + + + + + A2 + Slope definition A2. + 0x008 + read-only + 0x0000035D + + + A + A (slope definition) register. + 0 + 11 + + + + + A3 + Slope definition A3. + 0x00C + read-only + 0x00000400 + + + A + A (slope definition) register. + 0 + 11 + + + + + A4 + Slope definition A4. + 0x010 + read-only + 0x00000452 + + + A + A (slope definition) register. + 0 + 11 + + + + + A5 + Slope definition A5. + 0x014 + read-only + 0x0000037B + + + A + A (slope definition) register. + 0 + 11 + + + + + B0 + y-intercept B0. + 0x018 + read-only + 0x00003FCC + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + y-intercept B1. + 0x01C + read-only + 0x00003F98 + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + y-intercept B2. + 0x020 + read-only + 0x00003F98 + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + y-intercept B3. + 0x024 + read-only + 0x00000012 + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + y-intercept B4. + 0x028 + read-only + 0x0000004D + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + y-intercept B5. + 0x02C + read-only + 0x00003E10 + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0. + 0x030 + read-only + 0x000000E2 + + + T + T (segment end)register. + 0 + 7 + + + + + T1 + Segment end T1. + 0x034 + read-only + 0x00000000 + + + T + T (segment end)register. + 0 + 7 + + + + + T2 + Segment end T2. + 0x038 + read-only + 0x00000014 + + + T + T (segment end)register. + 0 + 7 + + + + + T3 + Segment end T3. + 0x03C + read-only + 0x00000019 + + + T + T (segment end)register. + 0 + 7 + + + + + T4 + Segment end T4. + 0x040 + read-only + 0x00000050 + + + T + T (segment end)register. + 0 + 7 + + + + + + NFC + Unspecified + 0x450 + + TAGHEADER0 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + + + UICR + User Information Configuration Registers + UICR + 0x10001000 + 32 + + 0 + 0x1000 + registers + + + + UNUSED0 + Unspecified + 0x000 + read-write + + + UNUSED1 + Unspecified + 0x004 + read-write + + + UNUSED2 + Unspecified + 0x008 + read-write + + + UNUSED3 + Unspecified + 0x010 + read-write + + + 15 + 4 + NRFFW[%s] + Description collection[0]: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 12 + 4 + NRFHW[%s] + Description collection[0]: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 32 + 4 + CUSTOMER[%s] + Description collection[0]: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 2 + 4 + PSELRESET[%s] + Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO number P0.n onto which Reset is exposed + 0 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access Port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. + 0 + 7 + + + Disabled + Disable + 0xFF + + + Enabled + Enable + 0x00 + + + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x20C + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation + 1 + + + + + + + + + BPROT + Block Protect + BPROT + 0x40000000 + 32 + + 0 + 0x1000 + registers + + + + CONFIG0 + Block protect configuration register 0 + 0x600 + read-write + + + REGION0 + Enable protection for region 0. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION1 + Enable protection for region 1. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION2 + Enable protection for region 2. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION3 + Enable protection for region 3. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION4 + Enable protection for region 4. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION5 + Enable protection for region 5. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION6 + Enable protection for region 6. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION7 + Enable protection for region 7. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION8 + Enable protection for region 8. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION9 + Enable protection for region 9. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION10 + Enable protection for region 10. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION11 + Enable protection for region 11. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION12 + Enable protection for region 12. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION13 + Enable protection for region 13. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION14 + Enable protection for region 14. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION15 + Enable protection for region 15. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION16 + Enable protection for region 16. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION17 + Enable protection for region 17. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION18 + Enable protection for region 18. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION19 + Enable protection for region 19. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION20 + Enable protection for region 20. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION21 + Enable protection for region 21. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION22 + Enable protection for region 22. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION23 + Enable protection for region 23. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION24 + Enable protection for region 24. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION25 + Enable protection for region 25. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION26 + Enable protection for region 26. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION27 + Enable protection for region 27. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION28 + Enable protection for region 28. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION29 + Enable protection for region 29. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION30 + Enable protection for region 30. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION31 + Enable protection for region 31. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + + + CONFIG1 + Block protect configuration register 1 + 0x604 + read-write + + + REGION32 + Enable protection for region 32. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION33 + Enable protection for region 33. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION34 + Enable protection for region 34. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION35 + Enable protection for region 35. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION36 + Enable protection for region 36. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION37 + Enable protection for region 37. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION38 + Enable protection for region 38. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION39 + Enable protection for region 39. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION40 + Enable protection for region 40. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION41 + Enable protection for region 41. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION42 + Enable protection for region 42. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION43 + Enable protection for region 43. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION44 + Enable protection for region 44. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION45 + Enable protection for region 45. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION46 + Enable protection for region 46. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION47 + Enable protection for region 47. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION48 + Enable protection for region 48. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION49 + Enable protection for region 49. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION50 + Enable protection for region 50. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION51 + Enable protection for region 51. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION52 + Enable protection for region 52. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION53 + Enable protection for region 53. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION54 + Enable protection for region 54. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION55 + Enable protection for region 55. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION56 + Enable protection for region 56. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION57 + Enable protection for region 57. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION58 + Enable protection for region 58. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION59 + Enable protection for region 59. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION60 + Enable protection for region 60. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION61 + Enable protection for region 61. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION62 + Enable protection for region 62. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION63 + Enable protection for region 63. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + DISABLEINDEBUG + Disable protection mechanism in debug interface mode + 0x608 + read-write + 0x00000001 + + + DISABLEINDEBUG + Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. + 0 + 0 + + + Disabled + Disable in debug + 1 + + + Enabled + Enable in debug + 0 + + + + + + + UNUSED0 + Unspecified + 0x60C + read-write + + + CONFIG2 + Block protect configuration register 2 + 0x610 + read-write + + + REGION64 + Enable protection for region 64. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION65 + Enable protection for region 65. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION66 + Enable protection for region 66. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION67 + Enable protection for region 67. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION68 + Enable protection for region 68. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION69 + Enable protection for region 69. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION70 + Enable protection for region 70. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION71 + Enable protection for region 71. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION72 + Enable protection for region 72. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION73 + Enable protection for region 73. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION74 + Enable protection for region 74. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION75 + Enable protection for region 75. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION76 + Enable protection for region 76. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION77 + Enable protection for region 77. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION78 + Enable protection for region 78. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION79 + Enable protection for region 79. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION80 + Enable protection for region 80. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION81 + Enable protection for region 81. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION82 + Enable protection for region 82. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION83 + Enable protection for region 83. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION84 + Enable protection for region 84. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION85 + Enable protection for region 85. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION86 + Enable protection for region 86. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION87 + Enable protection for region 87. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION88 + Enable protection for region 88. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION89 + Enable protection for region 89. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION90 + Enable protection for region 90. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION91 + Enable protection for region 91. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION92 + Enable protection for region 92. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION93 + Enable protection for region 93. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION94 + Enable protection for region 94. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION95 + Enable protection for region 95. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + CONFIG3 + Block protect configuration register 3 + 0x614 + read-write + + + REGION96 + Enable protection for region 96. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION97 + Enable protection for region 97. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION98 + Enable protection for region 98. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION99 + Enable protection for region 99. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION100 + Enable protection for region 100. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION101 + Enable protection for region 101. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION102 + Enable protection for region 102. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION103 + Enable protection for region 103. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION104 + Enable protection for region 104. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION105 + Enable protection for region 105. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION106 + Enable protection for region 106. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION107 + Enable protection for region 107. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION108 + Enable protection for region 108. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION109 + Enable protection for region 109. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION110 + Enable protection for region 110. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION111 + Enable protection for region 111. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION112 + Enable protection for region 112. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION113 + Enable protection for region 113. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION114 + Enable protection for region 114. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION115 + Enable protection for region 115. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION116 + Enable protection for region 116. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION117 + Enable protection for region 117. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION118 + Enable protection for region 118. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION119 + Enable protection for region 119. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION120 + Enable protection for region 120. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION121 + Enable protection for region 121. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION122 + Enable protection for region 122. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION123 + Enable protection for region 123. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION124 + Enable protection for region 124. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION125 + Enable protection for region 125. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION126 + Enable protection for region 126. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION127 + Enable protection for region 127. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + + + POWER + Power control + POWER + 0x40000000 + 32 + BPROT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + + + TASKS_CONSTLAT + Enable constant latency mode + 0x078 + write-only + + + TASKS_CONSTLAT + 0 + 0 + + + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0x07C + write-only + + + TASKS_LOWPWR + 0 + 0 + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + 0 + 0 + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + 0 + 0 + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to Enable interrupt for POFWARN event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to Enable interrupt for SLEEPENTER event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to Enable interrupt for SLEEPEXIT event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to Disable interrupt for POFWARN event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to Disable interrupt for SLEEPENTER event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to Disable interrupt for SLEEPEXIT event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset due to wake up from System OFF mode by NFC field detect + 19 + 19 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + RAMSTATUS + Deprecated register - RAM status register + 0x428 + read-only + 0x00000000 + + + RAMBLOCK0 + RAM block 0 is on or off/powering up + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK1 + RAM block 1 is on or off/powering up + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK2 + RAM block 2 is on or off/powering up + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK3 + RAM block 3 is on or off/powering up + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power failure comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure comparator + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power failure comparator threshold setting + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + RAMON + Deprecated register - RAM on/off register (this register is retained) + 0x524 + read-write + 0x00000003 + + + ONRAM0 + Keep RAM block 0 on or off in system ON Mode + 0 + 0 + + + RAM0Off + Off + 0 + + + RAM0On + On + 1 + + + + + ONRAM1 + Keep RAM block 1 on or off in system ON Mode + 1 + 1 + + + RAM1Off + Off + 0 + + + RAM1On + On + 1 + + + + + OFFRAM0 + Keep retention on RAM block 0 when RAM block is switched off + 16 + 16 + + + RAM0Off + Off + 0 + + + RAM0On + On + 1 + + + + + OFFRAM1 + Keep retention on RAM block 1 when RAM block is switched off + 17 + 17 + + + RAM1Off + Off + 0 + + + RAM1On + On + 1 + + + + + + + RAMONB + Deprecated register - RAM on/off register (this register is retained) + 0x554 + read-write + 0x00000003 + + + ONRAM2 + Keep RAM block 2 on or off in system ON Mode + 0 + 0 + + + RAM2Off + Off + 0 + + + RAM2On + On + 1 + + + + + ONRAM3 + Keep RAM block 3 on or off in system ON Mode + 1 + 1 + + + RAM3Off + Off + 0 + + + RAM3On + On + 1 + + + + + OFFRAM2 + Keep retention on RAM block 2 when RAM block is switched off + 16 + 16 + + + RAM2Off + Off + 0 + + + RAM2On + On + 1 + + + + + OFFRAM3 + Keep retention on RAM block 3 when RAM block is switched off + 17 + 17 + + + RAM3Off + Off + 0 + + + RAM3On + On + 1 + + + + + + + DCDCEN + DC/DC enable register + 0x578 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + 8 + 16 + RAM[%s] + Unspecified + 0x900 + + POWER + Description cluster[0]: RAM0 power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 ON or OFF in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 ON or OFF in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is in OFF + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is in OFF + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster[0]: RAM0 power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM0 on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM0 on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster[0]: RAM0 power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM0 on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAM0 on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + + + + + + CLOCK + Clock control + CLOCK + 0x40000000 + 32 + BPROT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + 0 + 0 + + + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + 0 + 0 + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + + + TASKS_LFCLKSTART + 0 + 0 + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + 0 + 0 + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + 0 + 0 + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + 0 + 0 + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + 0 + 0 + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + 0 + 0 + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + 0 + 0 + + + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0x10C + read-write + + + EVENTS_DONE + 0 + 0 + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to Enable interrupt for HFCLKSTARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to Enable interrupt for LFCLKSTARTED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to Enable interrupt for DONE event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to Enable interrupt for CTTO event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to Disable interrupt for HFCLKSTARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to Disable interrupt for LFCLKSTARTED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to Disable interrupt for DONE event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to Disable interrupt for CTTO event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + TRACECONFIG + Clocking options for the Trace Port debug interface + 0x55C + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. + 0 + 1 + + + 32MHz + 32 MHz Trace Port clock (TRACECLK = 16 MHz) + 0 + + + 16MHz + 16 MHz Trace Port clock (TRACECLK = 8 MHz) + 1 + + + 8MHz + 8 MHz Trace Port clock (TRACECLK = 4 MHz) + 2 + + + 4MHz + 4 MHz Trace Port clock (TRACECLK = 2 MHz) + 3 + + + + + TRACEMUX + Pin multiplexing of trace signals. + 16 + 17 + + + GPIO + GPIOs multiplexed onto all trace-pins + 0 + + + Serial + SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins + 1 + + + Parallel + TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. + 2 + + + + + + + + + RADIO + 2.4 GHz Radio + RADIO + 0x40001000 + 32 + + 0 + 0x1000 + registers + + + RADIO + 1 + + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + 0 + 0 + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + 0 + 0 + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + 0 + 0 + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength. + 0x014 + write-only + + + TASKS_RSSISTART + 0 + 0 + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + 0 + 0 + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + 0 + 0 + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + 0 + 0 + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + 0 + 0 + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + 0 + 0 + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + 0 + 0 + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + 0 + 0 + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + 0 + 0 + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + 0 + 0 + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + 0 + 0 + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete. + 0x11C + read-write + + + EVENTS_RSSIEND + 0 + 0 + + + + + EVENTS_BCMATCH + Bit counter reached bit count value. + 0x128 + read-write + + + EVENTS_BCMATCH + 0 + 0 + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + 0 + 0 + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + READY_START + Shortcut between READY event and START task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between END event and DISABLE task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between DISABLED event and TXEN task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between DISABLED event and RXEN task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between ADDRESS event and RSSISTART task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between END event and START task + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between ADDRESS event and BCSTART task + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between DISABLED event and RSSISTOP task + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to Enable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to Enable interrupt for ADDRESS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to Enable interrupt for PAYLOAD event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to Enable interrupt for END event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to Enable interrupt for DISABLED event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to Enable interrupt for DEVMATCH event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to Enable interrupt for DEVMISS event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to Enable interrupt for RSSIEND event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to Enable interrupt for BCMATCH event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to Enable interrupt for CRCOK event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to Enable interrupt for CRCERROR event + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to Disable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to Disable interrupt for ADDRESS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to Disable interrupt for PAYLOAD event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to Disable interrupt for END event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to Disable interrupt for DISABLED event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to Disable interrupt for DEVMATCH event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to Disable interrupt for DEVMISS event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to Disable interrupt for RSSIEND event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to Disable interrupt for BCMATCH event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to Disable interrupt for CRCOK event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to Disable interrupt for CRCERROR event + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power. + 0 + 7 + + + Pos4dBm + +4 dBm + 0x04 + + + Pos3dBm + +3 dBm + 0x03 + + + 0dBm + 0 dBm + 0x00 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 1 + + + Nrf_250Kbit + Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode + 2 + + + Ble_1Mbit + 1 Mbit/s Bluetooth Low Energy + 3 + + + Ble_2Mbit + 2 Mbit/s Bluetooth Low Energy + 4 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 24 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least Significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 8 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + UNUSED0 + Unspecified + 0x540 + read-write + + + TIFS + Inter Frame Spacing in us + 0x544 + read-write + + + TIFS + Inter Frame Spacing in us + 0 + 7 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 8 + 4 + DAB[%s] + Description collection[0]: Device address base segment 0 + 0x600 + read-write + + + DAB + Device address base segment 0 + 0 + 31 + + + + + 8 + 4 + DAP[%s] + Description collection[0]: Device address prefix 0 + 0x620 + read-write + + + DAP + Device address prefix 0 + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST), see electrical specification for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UARTE0 + UART with EasyDMA + UARTE + 0x40002000 + 32 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + 0 + 0 + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + 0 + 0 + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + 0 + 0 + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + 0 + 0 + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + 0 + 0 + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + 0 + 0 + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + 0 + 0 + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + 0 + 0 + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + 0 + 0 + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + 0 + 0 + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + 0 + 0 + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + 0 + 0 + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + 0 + 0 + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between ENDRX event and STARTRX task + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between ENDRX event and STOPRX task + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for CTS event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for NCTS event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for RXDRDY event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for ENDRX event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for TXDRDY event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for ENDTX event + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for ERROR event + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for RXTO event + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for RXSTARTED event + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for TXSTARTED event + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for TXSTOPPED event + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to Enable interrupt for CTS event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to Enable interrupt for NCTS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to Enable interrupt for RXDRDY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to Enable interrupt for ENDRX event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to Enable interrupt for TXDRDY event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to Enable interrupt for ENDTX event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to Enable interrupt for RXTO event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to Enable interrupt for RXSTARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to Enable interrupt for TXSTARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to Enable interrupt for TXSTOPPED event + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to Disable interrupt for CTS event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to Disable interrupt for NCTS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to Disable interrupt for RXDRDY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to Disable interrupt for ENDRX event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to Disable interrupt for TXDRDY event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to Disable interrupt for ENDTX event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to Disable interrupt for RXTO event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to Disable interrupt for RXSTARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to Disable interrupt for TXSTARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to Disable interrupt for TXSTOPPED event + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + UART + 0x40002000 + 32 + UARTE0 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + 0 + 0 + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + 0 + 0 + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + 0 + 0 + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + 0 + 0 + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + 0 + 0 + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + 0 + 0 + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + 0 + 0 + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + CTS_STARTRX + Shortcut between CTS event and STARTRX task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between NCTS event and STOPRX task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to Enable interrupt for CTS event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to Enable interrupt for NCTS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to Enable interrupt for RXDRDY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to Enable interrupt for TXDRDY event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to Enable interrupt for RXTO event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to Disable interrupt for CTS event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to Disable interrupt for NCTS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to Disable interrupt for RXDRDY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to Disable interrupt for TXDRDY event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to Disable interrupt for RXTO event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSELRTS + Pin select for RTS + 0x508 + read-write + 0xFFFFFFFF + + + PSELRTS + Pin number configuration for UART RTS signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELTXD + Pin select for TXD + 0x50C + read-write + 0xFFFFFFFF + + + PSELTXD + Pin number configuration for UART TXD signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELCTS + Pin select for CTS + 0x510 + read-write + 0xFFFFFFFF + + + PSELCTS + Pin number configuration for UART CTS signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELRXD + Pin select for RXD + 0x514 + read-write + 0xFFFFFFFF + + + PSELRXD + Pin number configuration for UART RXD signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + SPIM + 0x40003000 + 32 + SPIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + 0 + 0 + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + 0 + 0 + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + 0 + 0 + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + 0 + 0 + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + END_START + Shortcut between END event and START task + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to Enable interrupt for ENDRX event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to Enable interrupt for END event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to Enable interrupt for ENDTX event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to Enable interrupt for STARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to Disable interrupt for ENDRX event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to Disable interrupt for END event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to Disable interrupt for ENDTX event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to Disable interrupt for STARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + SPIS + 0x40003000 + 32 + SPIM0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + 0 + 0 + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + 0 + 0 + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + 0 + 0 + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + 0 + 0 + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + END_ACQUIRE + Shortcut between END event and ACQUIRE task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to Enable interrupt for END event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to Enable interrupt for ENDRX event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to Enable interrupt for ACQUIRED event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to Disable interrupt for END event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to Disable interrupt for ENDRX event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to Disable interrupt for ACQUIRED event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 7 + + + + + + TXD + Unspecified + SPIS_TXD + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 7 + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + TWIM + 0x40003000 + 32 + SPIM0 + TWIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + 0 + 0 + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + 0 + 0 + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + 0 + 0 + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + 0 + 0 + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + 0 + 0 + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + 0 + 0 + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between LASTTX event and STARTRX task + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between LASTTX event and SUSPEND task + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between LASTTX event and STOP task + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between LASTRX event and STARTTX task + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between LASTRX event and STOP task + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for STOPPED event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for ERROR event + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for SUSPENDED event + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for RXSTARTED event + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for TXSTARTED event + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for LASTRX event + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for LASTTX event + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to Enable interrupt for SUSPENDED event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to Enable interrupt for RXSTARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to Enable interrupt for TXSTARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to Enable interrupt for LASTRX event + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to Enable interrupt for LASTTX event + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to Disable interrupt for SUSPENDED event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to Disable interrupt for RXSTARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to Disable interrupt for TXSTARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to Disable interrupt for LASTRX event + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to Disable interrupt for LASTTX event + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + TWIS + 0x40003000 + 32 + SPIM0 + TWIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + 0 + 0 + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + 0 + 0 + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + 0 + 0 + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + 0 + 0 + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + 0 + 0 + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + 0 + 0 + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between WRITE event and SUSPEND task + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between READ event and SUSPEND task + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for STOPPED event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for ERROR event + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for RXSTARTED event + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for TXSTARTED event + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for WRITE event + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for READ event + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to Enable interrupt for RXSTARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to Enable interrupt for TXSTARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to Enable interrupt for WRITE event + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to Enable interrupt for READ event + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to Disable interrupt for RXSTARTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to Disable interrupt for TXSTARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to Disable interrupt for WRITE event + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to Disable interrupt for READ event + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Which of the addresses in {ADDRESS} matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 7 + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 7 + + + + + + 2 + 4 + ADDRESS[%s] + Description collection[0]: TWI slave address 0 + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI0 + Serial Peripheral Interface 0 + SPI + 0x40003000 + 32 + SPIM0 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to Enable interrupt for READY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to Disable interrupt for READY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PSELSCK + Pin number configuration for SPI SCK signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + MOSI + Pin select for MOSI + 0x004 + read-write + 0xFFFFFFFF + + + PSELMOSI + Pin number configuration for SPI MOSI signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + MISO + Pin select for MISO + 0x008 + read-write + 0xFFFFFFFF + + + PSELMISO + Pin number configuration for SPI MISO signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered + 0 + 7 + + + + + FREQUENCY + SPI frequency + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + TWI0 + I2C compatible Two-Wire Interface 0 + TWI + 0x40003000 + 32 + SPIM0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + 0 + 0 + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + 0 + 0 + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + 0 + 0 + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + 0 + 0 + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + 0 + 0 + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + BB_SUSPEND + Shortcut between BB event and SUSPEND task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between BB event and STOP task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to Enable interrupt for RXDREADY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to Enable interrupt for TXDSENT event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to Enable interrupt for BB event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to Enable interrupt for SUSPENDED event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to Disable interrupt for RXDREADY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to Disable interrupt for TXDSENT event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to Disable interrupt for BB event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to Disable interrupt for SUSPENDED event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSELSCL + Pin select for SCL + 0x508 + read-write + 0xFFFFFFFF + + + PSELSCL + Pin number configuration for TWI SCL signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELSDA + Pin select for SDA + 0x50C + read-write + 0xFFFFFFFF + + + PSELSDA + Pin number configuration for TWI SDA signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + SPIM + 0x40004000 + 32 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIS1 + SPI Slave 1 + SPIS + 0x40004000 + 32 + SPIM1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + TWIM + 0x40004000 + 32 + SPIM1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + TWIS + 0x40004000 + 32 + SPIM1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPI1 + Serial Peripheral Interface 1 + SPI + 0x40004000 + 32 + SPIM1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + TWI + 0x40004000 + 32 + SPIM1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + NFCT + NFC-A compatible radio + NFCT + 0x40005000 + 32 + + 0 + 0x1000 + registers + + + NFCT + 5 + + + + TASKS_ACTIVATE + Activate NFC peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + 0 + 0 + + + + + TASKS_DISABLE + Disable NFC peripheral + 0x004 + write-only + + + TASKS_DISABLE + 0 + 0 + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + 0 + 0 + + + + + TASKS_STARTTX + Start transmission of a outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + 0 + 0 + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + 0 + 0 + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + 0 + 0 + + + + + EVENTS_READY + The NFC peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + 0 + 0 + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + 0 + 0 + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + 0 + 0 + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + 0 + 0 + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + 0 + 0 + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + 0 + 0 + + + + + EVENTS_RXFRAMEEND + Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + 0 + 0 + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + 0 + 0 + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + 0 + 0 + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + 0 + 0 + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + 0 + 0 + + + + + EVENTS_COLLISION + NFC Auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + 0 + 0 + + + + + EVENTS_SELECTED + NFC Auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + 0 + 0 + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between FIELDDETECTED event and ACTIVATE task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between FIELDLOST event and SENSE task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for READY event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for FIELDDETECTED event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for FIELDLOST event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for TXFRAMESTART event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for TXFRAMEEND event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for RXFRAMESTART event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for RXFRAMEEND event + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for ERROR event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for RXERROR event + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for ENDRX event + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for ENDTX event + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for AUTOCOLRESSTARTED event + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for COLLISION event + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for SELECTED event + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for STARTED event + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to Enable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to Enable interrupt for FIELDDETECTED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to Enable interrupt for FIELDLOST event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to Enable interrupt for TXFRAMESTART event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to Enable interrupt for TXFRAMEEND event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to Enable interrupt for RXFRAMESTART event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to Enable interrupt for RXFRAMEEND event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to Enable interrupt for RXERROR event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to Enable interrupt for ENDRX event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to Enable interrupt for ENDTX event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to Enable interrupt for COLLISION event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to Enable interrupt for SELECTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to Enable interrupt for STARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to Disable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to Disable interrupt for FIELDDETECTED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to Disable interrupt for FIELDLOST event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to Disable interrupt for TXFRAMESTART event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to Disable interrupt for TXFRAMEEND event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to Disable interrupt for RXFRAMESTART event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to Disable interrupt for RXFRAMEEND event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to Disable interrupt for RXERROR event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to Disable interrupt for ENDRX event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to Disable interrupt for ENDTX event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to Disable interrupt for COLLISION event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to Disable interrupt for SELECTED event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to Disable interrupt for STARTED event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + NFCFIELDTOOSTRONG + Field level is too high at max load resistance + 2 + 2 + + + NFCFIELDTOOWEAK + Field level is too low at min load resistance + 3 + 3 + + + + + FRAMESTATUS + Unspecified + 0x40C + + RX + Result of last incoming frames + 0x000 + read-write + oneToClear + + + CRCERROR + No valid End of Frame detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + CURRENTLOADCTRL + Current value driven to the NFC Load Control + 0x430 + read-only + 0x00000000 + + + CURRENTLOADCTRL + Current value driven to the NFC Load Control + 0 + 5 + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates the presence or not of a valid field. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of allocated for TXD and RXD data storage buffer in Data RAM + 0x514 + read-write + + + MAXLEN + Size of allocated for TXD and RXD data storage buffer in Data RAM + 0 + 8 + + + + + TXD + Unspecified + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Adding parity or not in the frame + 0 + 0 + + + NoParity + Parity is not added in TX frames + 0 + + + Parity + Parity is added TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits in start or at end of a Frame + 1 + 1 + + + DiscardEnd + Unused bits is discarded at end of frame + 0 + + + DiscardStart + Unused bits is discarded at start of frame + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + Start of Frame symbol not added + 0 + + + SoF + Start of Frame symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Parity expected or not in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + Start of Frame symbol is not expected in RX frames + 0 + + + SoF + Start of Frame symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the Auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade bit (controlled by hardware, write has no effect) + 2 + 2 + + + Complete + NFCID1 complete + 0 + + + NotComplete + NFCID1 not complete + 1 + + + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + GPIOTE + 0x40006000 + 32 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + + + 8 + 4 + TASKS_OUT[%s] + Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + 0x000 + write-only + + + 8 + 4 + TASKS_SET[%s] + Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + 8 + 4 + TASKS_CLR[%s] + Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + 8 + 4 + EVENTS_IN[%s] + Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL + 0x100 + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to Enable interrupt for IN[0] event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to Enable interrupt for IN[1] event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to Enable interrupt for IN[2] event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to Enable interrupt for IN[3] event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to Enable interrupt for IN[4] event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to Enable interrupt for IN[5] event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to Enable interrupt for IN[6] event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to Enable interrupt for IN[7] event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to Enable interrupt for PORT event + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to Disable interrupt for IN[0] event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to Disable interrupt for IN[1] event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to Disable interrupt for IN[2] event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to Disable interrupt for IN[3] event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to Disable interrupt for IN[4] event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to Disable interrupt for IN[5] event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to Disable interrupt for IN[6] event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to Disable interrupt for IN[7] event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to Disable interrupt for PORT event + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 8 + 4 + CONFIG[%s] + Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Analog to Digital Converter + SAADC + 0x40007000 + 32 + + 0 + 0x1000 + registers + + + SAADC + 7 + + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + 0 + 0 + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + 0 + 0 + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + 0 + 0 + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + 0 + 0 + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + 0 + 0 + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + + + EVENTS_RESULTDONE + 0 + 0 + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + 0 + 0 + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + 8 + 8 + EVENTS_CH[%s] + Unspecified + 0x118 + + LIMITH + Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH + 0x000 + read-write + + + LIMITL + Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW + 0x004 + read-write + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for STARTED event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for END event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for DONE event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for RESULTDONE event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for CALIBRATEDONE event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for STOPPED event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for CH[0].LIMITH event + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for CH[0].LIMITL event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for CH[1].LIMITH event + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for CH[1].LIMITL event + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for CH[2].LIMITH event + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for CH[2].LIMITL event + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for CH[3].LIMITH event + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for CH[3].LIMITL event + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for CH[4].LIMITH event + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for CH[4].LIMITL event + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for CH[5].LIMITH event + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for CH[5].LIMITL event + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for CH[6].LIMITH event + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for CH[6].LIMITL event + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for CH[7].LIMITH event + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for CH[7].LIMITL event + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to Enable interrupt for STARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to Enable interrupt for END event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to Enable interrupt for DONE event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to Enable interrupt for RESULTDONE event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to Enable interrupt for CALIBRATEDONE event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to Enable interrupt for CH[0].LIMITH event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to Enable interrupt for CH[0].LIMITL event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to Enable interrupt for CH[1].LIMITH event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to Enable interrupt for CH[1].LIMITL event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to Enable interrupt for CH[2].LIMITH event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to Enable interrupt for CH[2].LIMITL event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to Enable interrupt for CH[3].LIMITH event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to Enable interrupt for CH[3].LIMITL event + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to Enable interrupt for CH[4].LIMITH event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to Enable interrupt for CH[4].LIMITL event + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to Enable interrupt for CH[5].LIMITH event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to Enable interrupt for CH[5].LIMITL event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to Enable interrupt for CH[6].LIMITH event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to Enable interrupt for CH[6].LIMITL event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to Enable interrupt for CH[7].LIMITH event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to Enable interrupt for CH[7].LIMITL event + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to Disable interrupt for STARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to Disable interrupt for END event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to Disable interrupt for DONE event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to Disable interrupt for RESULTDONE event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to Disable interrupt for CALIBRATEDONE event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to Disable interrupt for CH[0].LIMITH event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to Disable interrupt for CH[0].LIMITL event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to Disable interrupt for CH[1].LIMITH event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to Disable interrupt for CH[1].LIMITL event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to Disable interrupt for CH[2].LIMITH event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to Disable interrupt for CH[2].LIMITL event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to Disable interrupt for CH[3].LIMITH event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to Disable interrupt for CH[3].LIMITL event + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to Disable interrupt for CH[4].LIMITH event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to Disable interrupt for CH[4].LIMITL event + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to Disable interrupt for CH[5].LIMITH event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to Disable interrupt for CH[5].LIMITL event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to Disable interrupt for CH[6].LIMITH event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to Disable interrupt for CH[6].LIMITL event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to Disable interrupt for CH[7].LIMITH event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to Disable interrupt for CH[7].LIMITL event + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0 + + + Busy + ADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 16 + CH[%s] + Unspecified + 0x510 + + PSELP + Description cluster[0]: Input positive pin selection for CH[0] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + PSELN + Description cluster[0]: Input negative pin selection for CH[0] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + CONFIG + Description cluster[0]: Input configuration for CH[0] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster[0]: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + TIMER + 0x40008000 + 32 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + 0 + 0 + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + 0 + 0 + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + 0 + 0 + + + + + 4 + 4 + TASKS_CAPTURE[%s] + Description collection[0]: Capture Timer value to CC[0] register + 0x040 + write-only + + + 4 + 4 + EVENTS_COMPARE[%s] + Description collection[0]: Compare event on CC[0] match + 0x140 + read-write + + + SHORTS + Shortcut register + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between COMPARE[0] event and CLEAR task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between COMPARE[1] event and CLEAR task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between COMPARE[2] event and CLEAR task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between COMPARE[3] event and CLEAR task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between COMPARE[0] event and STOP task + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between COMPARE[1] event and STOP task + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between COMPARE[2] event and STOP task + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between COMPARE[3] event and STOP task + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to Enable interrupt for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to Enable interrupt for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to Enable interrupt for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to Enable interrupt for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to Disable interrupt for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to Disable interrupt for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to Disable interrupt for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to Disable interrupt for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 4 + 4 + CC[%s] + Description collection[0]: Capture/Compare register 0 + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + TIMER + 0x40009000 + 32 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + TIMER + 0x4000A000 + 32 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + RTC + 0x4000B000 + 32 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + 0 + 0 + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + 0 + 0 + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + 0 + 0 + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + 0 + 0 + + + + + 4 + 4 + EVENTS_COMPARE[%s] + Description collection[0]: Compare event on CC[0] match + 0x140 + read-write + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to Enable interrupt for TICK event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to Enable interrupt for OVRFLW event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to Enable interrupt for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to Enable interrupt for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to Enable interrupt for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to Enable interrupt for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to Disable interrupt for TICK event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to Disable interrupt for OVRFLW event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to Disable interrupt for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to Disable interrupt for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to Disable interrupt for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to Disable interrupt for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for TICK event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for OVRFLW event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for COMPARE[0] event + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for COMPARE[1] event + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for COMPARE[2] event + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for COMPARE[3] event + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to Enable event routing for TICK event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to Enable event routing for OVRFLW event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to Enable event routing for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to Enable event routing for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to Enable event routing for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to Enable event routing for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to Disable event routing for TICK event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to Disable event routing for OVRFLW event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to Disable event routing for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to Disable event routing for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to Disable event routing for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to Disable event routing for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 4 + 4 + CC[%s] + Description collection[0]: Compare register 0 + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + TEMP + 0x4000C000 + 32 + + 0 + 0x1000 + registers + + + TEMP + 12 + + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to Enable interrupt for DATARDY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to Disable interrupt for DATARDY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000320 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000343 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x0000035D + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x00000400 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000047F + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x0000037B + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00003FCC + + + B0 + y-intercept of 1st piece wise linear function + 0 + 13 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00003F98 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 13 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00003F98 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 13 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 13 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x0000006A + + + B4 + y-intercept of 5th piece wise linear function + 0 + 13 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x00003DD0 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 13 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000014 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x00000019 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + RNG + 0x4000D000 + 32 + + 0 + 0x1000 + registers + + + RNG + 13 + + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + VALRDY_STOP + Shortcut between VALRDY event and STOP task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to Enable interrupt for VALRDY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to Disable interrupt for VALRDY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + ECB + 0x4000E000 + 32 + + 0 + 0x1000 + registers + + + ECB + 14 + + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + 0 + 0 + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + 0 + 0 + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + 0 + 0 + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to Enable interrupt for ENDECB event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to Enable interrupt for ERRORECB event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to Disable interrupt for ENDECB event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to Disable interrupt for ERRORECB event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + CCM + 0x4000F000 + 32 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + 0 + 0 + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + 0 + 0 + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + 0 + 0 + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + 0 + 0 + + + + + EVENTS_ERROR + CCM error event + 0x108 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between ENDKSGEN event and CRYPT task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to Enable interrupt for ENDKSGEN event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to Enable interrupt for ENDCRYPT event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to Enable interrupt for ERROR event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to Disable interrupt for ENDKSGEN event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to Disable interrupt for ENDCRYPT event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to Disable interrupt for ERROR event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Data rate that the CCM shall run in synch with + 16 + 16 + + + 1Mbit + In synch with 1 Mbit data rate + 0 + + + 2Mbit + In synch with 2 Mbit data rate + 1 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field is 5-bit + 0 + + + Extended + Extended length. Effective length of LENGTH field is 8-bit + 1 + + + + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + AAR + 0x4000F000 + 32 + CCM + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + 0 + 0 + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + 0 + 0 + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to Enable interrupt for END event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to Enable interrupt for RESOLVED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to Enable interrupt for NOTRESOLVED event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to Disable interrupt for END event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to Disable interrupt for RESOLVED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to Disable interrupt for NOTRESOLVED event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + WDT + Watchdog Timer + WDT + 0x40010000 + 32 + + 0 + 0x1000 + registers + + + WDT + 16 + + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to Enable interrupt for TIMEOUT event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to Disable interrupt for TIMEOUT event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 8 + 4 + RR[%s] + Description collection[0]: Reload request 0 + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + RTC + 0x40011000 + 32 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + QDEC + 0x40012000 + 32 + + 0 + 0x1000 + registers + + + QDEC + 18 + + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + 0 + 0 + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + 0 + 0 + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + 0 + 0 + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + 0 + 0 + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + 0 + 0 + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + 0 + 0 + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + 0 + 0 + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between REPORTRDY event and READCLRACC task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between SAMPLERDY event and STOP task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between REPORTRDY event and RDCLRACC task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between REPORTRDY event and STOP task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between DBLRDY event and RDCLRDBL task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between DBLRDY event and STOP task + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between SAMPLERDY event and READCLRACC task + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to Enable interrupt for SAMPLERDY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to Enable interrupt for REPORTRDY event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to Enable interrupt for ACCOF event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to Enable interrupt for DBLRDY event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to Disable interrupt for SAMPLERDY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to Disable interrupt for REPORTRDY event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to Disable interrupt for ACCOF event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to Disable interrupt for DBLRDY event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + 0 + 3 + + + 10Smpl + 10 samples / report + 0 + + + 40Smpl + 40 samples / report + 1 + + + 80Smpl + 80 samples / report + 2 + + + 120Smpl + 120 samples / report + 3 + + + 160Smpl + 160 samples / report + 4 + + + 200Smpl + 200 samples / report + 5 + + + 240Smpl + 240 samples / report + 6 + + + 280Smpl + 280 samples / report + 7 + + + 1Smpl + 1 sample / report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + COMP + 0x40013000 + 32 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + 0 + 0 + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + 0 + 0 + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + 0 + 0 + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + 0 + 0 + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + READY_SAMPLE + Shortcut between READY event and SAMPLE task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between READY event and STOP task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between DOWN event and STOP task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between UP event and STOP task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between CROSS event and STOP task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for READY event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for DOWN event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for UP event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for CROSS event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to Enable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to Enable interrupt for DOWN event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to Enable interrupt for UP event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to Enable interrupt for CROSS event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to Disable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to Disable interrupt for DOWN event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to Disable interrupt for UP event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to Disable interrupt for CROSS event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + 7 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + + + ISOURCE + Comparator hysteresis + 0 + 1 + + + Off + Current source disabled + 0 + + + Ien2mA5 + Current source enabled (+/- 2.5 uA) + 1 + + + Ien5mA + Current source enabled (+/- 5 uA) + 2 + + + Ien10mA + Current source enabled (+/- 10 uA) + 3 + + + + + + + + + LPCOMP + Low Power Comparator + LPCOMP + 0x40013000 + 32 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + 0 + 0 + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + 0 + 0 + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + 0 + 0 + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + 0 + 0 + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + READY_SAMPLE + Shortcut between READY event and SAMPLE task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between READY event and STOP task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between DOWN event and STOP task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between UP event and STOP task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between CROSS event and STOP task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to Enable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to Enable interrupt for DOWN event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to Enable interrupt for UP event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to Enable interrupt for CROSS event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to Disable interrupt for READY event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to Disable interrupt for DOWN event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to Disable interrupt for UP event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to Disable interrupt for CROSS event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-). + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-). + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis disabled (typ. 50 mV) + 1 + + + + + + + + + SWI0 + Software interrupt 0 + SWI + 0x40014000 + 32 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU0 + Event Generator Unit 0 + EGU + 0x40014000 + 32 + SWI0 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + + + 16 + 4 + TASKS_TRIGGER[%s] + Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event + 0x000 + write-only + + + 16 + 4 + EVENTS_TRIGGERED[%s] + Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task + 0x100 + read-write + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for TRIGGERED[0] event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for TRIGGERED[1] event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for TRIGGERED[2] event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for TRIGGERED[3] event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for TRIGGERED[4] event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for TRIGGERED[5] event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for TRIGGERED[6] event + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for TRIGGERED[7] event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for TRIGGERED[8] event + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for TRIGGERED[9] event + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for TRIGGERED[10] event + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for TRIGGERED[11] event + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for TRIGGERED[12] event + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for TRIGGERED[13] event + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for TRIGGERED[14] event + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for TRIGGERED[15] event + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to Enable interrupt for TRIGGERED[0] event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to Enable interrupt for TRIGGERED[1] event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to Enable interrupt for TRIGGERED[2] event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to Enable interrupt for TRIGGERED[3] event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to Enable interrupt for TRIGGERED[4] event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to Enable interrupt for TRIGGERED[5] event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to Enable interrupt for TRIGGERED[6] event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to Enable interrupt for TRIGGERED[7] event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to Enable interrupt for TRIGGERED[8] event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to Enable interrupt for TRIGGERED[9] event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to Enable interrupt for TRIGGERED[10] event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to Enable interrupt for TRIGGERED[11] event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to Enable interrupt for TRIGGERED[12] event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to Enable interrupt for TRIGGERED[13] event + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to Enable interrupt for TRIGGERED[14] event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to Enable interrupt for TRIGGERED[15] event + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to Disable interrupt for TRIGGERED[0] event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to Disable interrupt for TRIGGERED[1] event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to Disable interrupt for TRIGGERED[2] event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to Disable interrupt for TRIGGERED[3] event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to Disable interrupt for TRIGGERED[4] event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to Disable interrupt for TRIGGERED[5] event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to Disable interrupt for TRIGGERED[6] event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to Disable interrupt for TRIGGERED[7] event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to Disable interrupt for TRIGGERED[8] event + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to Disable interrupt for TRIGGERED[9] event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to Disable interrupt for TRIGGERED[10] event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to Disable interrupt for TRIGGERED[11] event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to Disable interrupt for TRIGGERED[12] event + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to Disable interrupt for TRIGGERED[13] event + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to Disable interrupt for TRIGGERED[14] event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to Disable interrupt for TRIGGERED[15] event + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI1 + Software interrupt 1 + SWI + 0x40015000 + 32 + + SWI1_EGU1 + 21 + + + + EGU1 + Event Generator Unit 1 + EGU + 0x40015000 + 32 + SWI1 + + SWI1_EGU1 + 21 + + + + SWI2 + Software interrupt 2 + SWI + 0x40016000 + 32 + + SWI2_EGU2 + 22 + + + + EGU2 + Event Generator Unit 2 + EGU + 0x40016000 + 32 + SWI2 + + SWI2_EGU2 + 22 + + + + SWI3 + Software interrupt 3 + SWI + 0x40017000 + 32 + + SWI3_EGU3 + 23 + + + + EGU3 + Event Generator Unit 3 + EGU + 0x40017000 + 32 + SWI3 + + SWI3_EGU3 + 23 + + + + SWI4 + Software interrupt 4 + SWI + 0x40018000 + 32 + + SWI4_EGU4 + 24 + + + + EGU4 + Event Generator Unit 4 + EGU + 0x40018000 + 32 + SWI4 + + SWI4_EGU4 + 24 + + + + SWI5 + Software interrupt 5 + SWI + 0x40019000 + 32 + + SWI5_EGU5 + 25 + + + + EGU5 + Event Generator Unit 5 + EGU + 0x40019000 + 32 + SWI5 + + SWI5_EGU5 + 25 + + + + TIMER3 + Timer/Counter 3 + TIMER + 0x4001A000 + 32 + + TIMER3 + 26 + + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + 0 + 0 + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + 0 + 0 + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + 0 + 0 + + + + + 6 + 4 + TASKS_CAPTURE[%s] + Description collection[0]: Capture Timer value to CC[0] register + 0x040 + write-only + + + 6 + 4 + EVENTS_COMPARE[%s] + Description collection[0]: Compare event on CC[0] match + 0x140 + read-write + + + SHORTS + Shortcut register + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between COMPARE[0] event and CLEAR task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between COMPARE[1] event and CLEAR task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between COMPARE[2] event and CLEAR task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between COMPARE[3] event and CLEAR task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between COMPARE[4] event and CLEAR task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between COMPARE[5] event and CLEAR task + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between COMPARE[0] event and STOP task + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between COMPARE[1] event and STOP task + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between COMPARE[2] event and STOP task + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between COMPARE[3] event and STOP task + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between COMPARE[4] event and STOP task + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between COMPARE[5] event and STOP task + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to Enable interrupt for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to Enable interrupt for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to Enable interrupt for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to Enable interrupt for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to Enable interrupt for COMPARE[4] event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to Enable interrupt for COMPARE[5] event + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to Disable interrupt for COMPARE[0] event + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to Disable interrupt for COMPARE[1] event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to Disable interrupt for COMPARE[2] event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to Disable interrupt for COMPARE[3] event + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to Disable interrupt for COMPARE[4] event + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to Disable interrupt for COMPARE[5] event + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 6 + 4 + CC[%s] + Description collection[0]: Capture/Compare register 0 + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER4 + Timer/Counter 4 + TIMER + 0x4001B000 + 32 + + TIMER4 + 27 + + + + PWM0 + Pulse Width Modulation Unit 0 + PWM + 0x4001C000 + 32 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + 2 + 4 + TASKS_SEQSTART[%s] + Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. + 0x008 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + 0 + 0 + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + 2 + 4 + EVENTS_SEQSTARTED[%s] + Description collection[0]: First PWM period started on sequence 0 + 0x108 + read-write + + + 2 + 4 + EVENTS_SEQEND[%s] + Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + 0 + 0 + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between SEQEND[0] event and STOP task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between SEQEND[1] event and STOP task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between LOOPSDONE event and SEQSTART[0] task + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between LOOPSDONE event and SEQSTART[1] task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between LOOPSDONE event and STOP task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for STOPPED event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for SEQSTARTED[0] event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for SEQSTARTED[1] event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for SEQEND[0] event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for SEQEND[1] event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for PWMPERIODEND event + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for LOOPSDONE event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to Enable interrupt for SEQSTARTED[0] event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to Enable interrupt for SEQSTARTED[1] event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to Enable interrupt for SEQEND[0] event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to Enable interrupt for SEQEND[1] event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to Enable interrupt for PWMPERIODEND event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to Enable interrupt for LOOPSDONE event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to Disable interrupt for SEQSTARTED[0] event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to Disable interrupt for SEQSTARTED[1] event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to Disable interrupt for SEQEND[0] event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to Disable interrupt for SEQEND[1] event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to Disable interrupt for PWMPERIODEND event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to Disable interrupt for LOOPSDONE event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up or up and down as wave counter mode + 0 + 0 + + + Up + Up counter - edge aligned PWM duty-cycle + 0 + + + UpAndDown + Up and down counter - center aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Pre-scaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16MHz) + 0 + + + DIV_2 + Divide by 2 ( 8MHz) + 1 + + + DIV_4 + Divide by 4 ( 4MHz) + 2 + + + DIV_8 + Divide by 8 ( 2MHz) + 3 + + + DIV_16 + Divide by 16 ( 1MHz) + 4 + + + DIV_32 + Divide by 32 ( 500kHz) + 5 + + + DIV_64 + Divide by 64 ( 250kHz) + 6 + + + DIV_128 + Divide by 128 ( 125kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Amount of playback of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Amount of playback of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 32 + SEQ[%s] + Unspecified + PWM_SEQ + 0x520 + + PTR + Description cluster[0]: Beginning address in Data RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in Data RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster[0]: Amount of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Amount of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster[0]: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + 0x560 + + 4 + 4 + OUT[%s] + Description collection[0]: Output pin select for PWM channel 0 + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + PDM + 0x4001D000 + 32 + + 0 + 0x1000 + registers + + + PDM + 29 + + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + 0 + 0 + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + 0 + 0 + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for STARTED event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for STOPPED event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for END event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to Enable interrupt for STARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to Enable interrupt for END event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to Disable interrupt for STARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to Disable interrupt for END event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge Left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 7 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + PSEL + Unspecified + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + NVMC + Non Volatile Memory Controller + NVMC + 0x4001E000 + 32 + + 0 + 0x1000 + registers + + + + READY + Ready flag + 0x400 + read-only + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write Enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in Code area + 0x508 + read-write + + + ERASEPAGE + Register for starting erase of a page in Code area + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. + 0x508 + read-write + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in Code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + read-write + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. + 0x510 + read-write + + + ERASEPCR0 + Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEUICR + Register for erasing User Information Configuration Registers + 0x514 + read-write + + + ERASEUICR + Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ICACHECNF + I-Code cache configuration register. + 0x540 + read-write + 0x00000000 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-Code cache hit counter. + 0x548 + read-write + + + HITS + Number of cache hits + 0 + 31 + + + + + IMISS + I-Code cache miss counter. + 0x54C + read-write + + + MISSES + Number of cache misses + 0 + 31 + + + + + + + PPI + Programmable Peripheral Interconnect + PPI + 0x4001F000 + 32 + + 0 + 0x1000 + registers + + + + 6 + 8 + TASKS_CHG[%s] + Channel group tasks + 0x000 + + EN + Description cluster[0]: Enable channel group 0 + 0x000 + write-only + + + DIS + Description cluster[0]: Disable channel group 0 + 0x004 + write-only + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 8 + CH[%s] + PPI Channel + 0x510 + + EEP + Description cluster[0]: Channel 0 event end-point + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster[0]: Channel 0 task end-point + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 6 + 4 + CHG[%s] + Description collection[0]: Channel group 0 + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 4 + FORK[%s] + Fork + 0x910 + + TEP + Description cluster[0]: Channel 0 task end-point + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + MWU + Memory Watch Unit + MWU + 0x40020000 + 32 + + 0 + 0x1000 + registers + + + MWU + 32 + + + + 4 + 8 + EVENTS_REGION[%s] + Unspecified + 0x100 + + WA + Description cluster[0]: Write access to region 0 detected + 0x000 + read-write + + + RA + Description cluster[0]: Read access to region 0 detected + 0x004 + read-write + + + + 2 + 8 + EVENTS_PREGION[%s] + Unspecified + 0x160 + + WA + Description cluster[0]: Write access to peripheral region 0 detected + 0x000 + read-write + + + RA + Description cluster[0]: Read access to peripheral region 0 detected + 0x004 + read-write + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + REGION0WA + Enable or disable interrupt for REGION[0].WA event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION0RA + Enable or disable interrupt for REGION[0].RA event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1WA + Enable or disable interrupt for REGION[1].WA event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1RA + Enable or disable interrupt for REGION[1].RA event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2WA + Enable or disable interrupt for REGION[2].WA event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2RA + Enable or disable interrupt for REGION[2].RA event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3WA + Enable or disable interrupt for REGION[3].WA event + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3RA + Enable or disable interrupt for REGION[3].RA event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0WA + Enable or disable interrupt for PREGION[0].WA event + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0RA + Enable or disable interrupt for PREGION[0].RA event + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1WA + Enable or disable interrupt for PREGION[1].WA event + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1RA + Enable or disable interrupt for PREGION[1].RA event + 27 + 27 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + REGION0WA + Write '1' to Enable interrupt for REGION[0].WA event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION0RA + Write '1' to Enable interrupt for REGION[0].RA event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1WA + Write '1' to Enable interrupt for REGION[1].WA event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1RA + Write '1' to Enable interrupt for REGION[1].RA event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2WA + Write '1' to Enable interrupt for REGION[2].WA event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2RA + Write '1' to Enable interrupt for REGION[2].RA event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to Enable interrupt for REGION[3].WA event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to Enable interrupt for REGION[3].RA event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to Enable interrupt for PREGION[0].WA event + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to Enable interrupt for PREGION[0].RA event + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to Enable interrupt for PREGION[1].WA event + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to Enable interrupt for PREGION[1].RA event + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + REGION0WA + Write '1' to Disable interrupt for REGION[0].WA event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to Disable interrupt for REGION[0].RA event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to Disable interrupt for REGION[1].WA event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to Disable interrupt for REGION[1].RA event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to Disable interrupt for REGION[2].WA event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to Disable interrupt for REGION[2].RA event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to Disable interrupt for REGION[3].WA event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to Disable interrupt for REGION[3].RA event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to Disable interrupt for PREGION[0].WA event + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to Disable interrupt for PREGION[0].RA event + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to Disable interrupt for PREGION[1].WA event + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to Disable interrupt for PREGION[1].RA event + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + NMIEN + Enable or disable non-maskable interrupt + 0x320 + read-write + + + REGION0WA + Enable or disable non-maskable interrupt for REGION[0].WA event + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION0RA + Enable or disable non-maskable interrupt for REGION[0].RA event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1WA + Enable or disable non-maskable interrupt for REGION[1].WA event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1RA + Enable or disable non-maskable interrupt for REGION[1].RA event + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2WA + Enable or disable non-maskable interrupt for REGION[2].WA event + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2RA + Enable or disable non-maskable interrupt for REGION[2].RA event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3WA + Enable or disable non-maskable interrupt for REGION[3].WA event + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3RA + Enable or disable non-maskable interrupt for REGION[3].RA event + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0WA + Enable or disable non-maskable interrupt for PREGION[0].WA event + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0RA + Enable or disable non-maskable interrupt for PREGION[0].RA event + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1WA + Enable or disable non-maskable interrupt for PREGION[1].WA event + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1RA + Enable or disable non-maskable interrupt for PREGION[1].RA event + 27 + 27 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + NMIENSET + Enable non-maskable interrupt + 0x324 + read-write + + + REGION0WA + Write '1' to Enable non-maskable interrupt for REGION[0].WA event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION0RA + Write '1' to Enable non-maskable interrupt for REGION[0].RA event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1WA + Write '1' to Enable non-maskable interrupt for REGION[1].WA event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1RA + Write '1' to Enable non-maskable interrupt for REGION[1].RA event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2WA + Write '1' to Enable non-maskable interrupt for REGION[2].WA event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2RA + Write '1' to Enable non-maskable interrupt for REGION[2].RA event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to Enable non-maskable interrupt for REGION[3].WA event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to Enable non-maskable interrupt for REGION[3].RA event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable non-maskable interrupt + 0x328 + read-write + + + REGION0WA + Write '1' to Disable non-maskable interrupt for REGION[0].WA event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to Disable non-maskable interrupt for REGION[0].RA event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to Disable non-maskable interrupt for REGION[1].WA event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to Disable non-maskable interrupt for REGION[1].RA event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to Disable non-maskable interrupt for REGION[2].WA event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to Disable non-maskable interrupt for REGION[2].RA event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to Disable non-maskable interrupt for REGION[3].WA event + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to Disable non-maskable interrupt for REGION[3].RA event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 2 + 8 + PERREGION[%s] + Unspecified + 0x400 + + SUBSTATWA + Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching + 0x000 + read-write + oneToClear + + + SR0 + Subregion 0 in region 0 (write '1' to clear) + 0 + 0 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region 0 (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region 0 (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region 0 (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region 0 (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region 0 (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region 0 (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region 0 (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region 0 (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region 0 (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region 0 (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region 0 (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region 0 (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region 0 (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region 0 (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region 0 (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region 0 (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region 0 (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region 0 (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region 0 (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region 0 (write '1' to clear) + 20 + 20 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region 0 (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region 0 (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region 0 (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region 0 (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region 0 (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region 0 (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region 0 (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region 0 (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region 0 (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region 0 (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region 0 (write '1' to clear) + 31 + 31 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + + + SUBSTATRA + Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching + 0x004 + read-write + oneToClear + + + SR0 + Subregion 0 in region 0 (write '1' to clear) + 0 + 0 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region 0 (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region 0 (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region 0 (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region 0 (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region 0 (write '1' to clear) + 5 + 5 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region 0 (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region 0 (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region 0 (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region 0 (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region 0 (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region 0 (write '1' to clear) + 11 + 11 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region 0 (write '1' to clear) + 12 + 12 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region 0 (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region 0 (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region 0 (write '1' to clear) + 15 + 15 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region 0 (write '1' to clear) + 16 + 16 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region 0 (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region 0 (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region 0 (write '1' to clear) + 19 + 19 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region 0 (write '1' to clear) + 20 + 20 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region 0 (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region 0 (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region 0 (write '1' to clear) + 23 + 23 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region 0 (write '1' to clear) + 24 + 24 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region 0 (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region 0 (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region 0 (write '1' to clear) + 27 + 27 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region 0 (write '1' to clear) + 28 + 28 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region 0 (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region 0 (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region 0 (write '1' to clear) + 31 + 31 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + + + + REGIONEN + Enable/disable regions watch + 0x510 + read-write + + + RGN0WA + Enable/disable write access watch in region[0] + 0 + 0 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable/disable read access watch in region[0] + 1 + 1 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable/disable write access watch in region[1] + 2 + 2 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable/disable read access watch in region[1] + 3 + 3 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable/disable write access watch in region[2] + 4 + 4 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable/disable read access watch in region[2] + 5 + 5 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable/disable write access watch in region[3] + 6 + 6 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable/disable read access watch in region[3] + 7 + 7 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENSET + Enable regions watch + 0x514 + read-write + + + RGN0WA + Enable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENCLR + Disable regions watch + 0x518 + read-write + + + RGN0WA + Disable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN0RA + Disable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN1WA + Disable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN1RA + Disable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN2WA + Disable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN2RA + Disable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN3WA + Disable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN3RA + Disable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + + + 4 + 16 + REGION[%s] + Unspecified + 0x600 + + START + Description cluster[0]: Start address for region 0 + 0x000 + read-write + 0x00000000 + + + START + Start address for region + 0 + 31 + + + + + END + Description cluster[0]: End address of region 0 + 0x004 + read-write + + + END + End address of region. + 0 + 31 + + + + + + 2 + 16 + PREGION[%s] + Unspecified + 0x6C0 + + START + Description cluster[0]: Reserved for future use + 0x000 + read-only + + + START + Reserved for future use + 0 + 31 + + + + + END + Description cluster[0]: Reserved for future use + 0x004 + read-only + + + END + Reserved for future use + 0 + 31 + + + + + SUBS + Description cluster[0]: Subregions of region 0 + 0x008 + read-write + 0x00000000 + + + SR0 + Include or exclude subregion 0 in region + 0 + 0 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 + 6 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + + + + + + PWM1 + Pulse Width Modulation Unit 1 + PWM + 0x40021000 + 32 + + PWM1 + 33 + + + + PWM2 + Pulse Width Modulation Unit 2 + PWM + 0x40022000 + 32 + + PWM2 + 34 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + SPIM + 0x40023000 + 32 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIS2 + SPI Slave 2 + SPIS + 0x40023000 + 32 + SPIM2 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPI2 + Serial Peripheral Interface 2 + SPI + 0x40023000 + 32 + SPIM2 + + SPIM2_SPIS2_SPI2 + 35 + + + + RTC2 + Real time counter 2 + RTC + 0x40024000 + 32 + + RTC2 + 36 + + + + I2S + Inter-IC Sound + I2S + 0x40025000 + 32 + + 0 + 0x1000 + registers + + + I2S + 37 + + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. + 0x004 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + 0 + 0 + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + 0 + 0 + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for RXPTRUPD event + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for STOPPED event + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for TXPTRUPD event + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to Enable interrupt for RXPTRUPD event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to Enable interrupt for STOPPED event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to Enable interrupt for TXPTRUPD event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to Disable interrupt for RXPTRUPD event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to Disable interrupt for STOPPED event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to Disable interrupt for TXPTRUPD event + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + FPU + FPU + FPU + 0x40026000 + 32 + + 0 + 0x1000 + registers + + + FPU + 38 + + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + P0 + GPIO Port 1 + GPIO + 0x50000000 + 32 + GPIO + + 0 + 0x1000 + registers + + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behaviour + 1 + + + + + + + 32 + 4 + PIN_CNF[%s] + Description collection[0]: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + diff --git a/src/aar/events_end.rs b/src/aar/events_end.rs index 90e8b57..f2020c9 100644 --- a/src/aar/events_end.rs +++ b/src/aar/events_end.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_END { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_END`"] +pub type EVENTS_END_R = crate::R; +#[doc = "Write proxy for field `EVENTS_END`"] +pub struct EVENTS_END_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_END_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W { + EVENTS_END_W { w: self } + } +} diff --git a/src/aar/events_notresolved.rs b/src/aar/events_notresolved.rs index c1091ff..ce46511 100644 --- a/src/aar/events_notresolved.rs +++ b/src/aar/events_notresolved.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_NOTRESOLVED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_NOTRESOLVED`"] +pub type EVENTS_NOTRESOLVED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_NOTRESOLVED`"] +pub struct EVENTS_NOTRESOLVED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_NOTRESOLVED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_notresolved(&self) -> EVENTS_NOTRESOLVED_R { + EVENTS_NOTRESOLVED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_notresolved(&mut self) -> EVENTS_NOTRESOLVED_W { + EVENTS_NOTRESOLVED_W { w: self } + } +} diff --git a/src/aar/events_resolved.rs b/src/aar/events_resolved.rs index d127a1a..79803a4 100644 --- a/src/aar/events_resolved.rs +++ b/src/aar/events_resolved.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RESOLVED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RESOLVED`"] +pub type EVENTS_RESOLVED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RESOLVED`"] +pub struct EVENTS_RESOLVED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RESOLVED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_resolved(&self) -> EVENTS_RESOLVED_R { + EVENTS_RESOLVED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_resolved(&mut self) -> EVENTS_RESOLVED_W { + EVENTS_RESOLVED_W { w: self } + } +} diff --git a/src/aar/tasks_start.rs b/src/aar/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/aar/tasks_start.rs +++ b/src/aar/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/aar/tasks_stop.rs b/src/aar/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/aar/tasks_stop.rs +++ b/src/aar/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/ccm/events_endcrypt.rs b/src/ccm/events_endcrypt.rs index 29bb140..f714614 100644 --- a/src/ccm/events_endcrypt.rs +++ b/src/ccm/events_endcrypt.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDCRYPT { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDCRYPT`"] +pub type EVENTS_ENDCRYPT_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDCRYPT`"] +pub struct EVENTS_ENDCRYPT_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDCRYPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endcrypt(&self) -> EVENTS_ENDCRYPT_R { + EVENTS_ENDCRYPT_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endcrypt(&mut self) -> EVENTS_ENDCRYPT_W { + EVENTS_ENDCRYPT_W { w: self } + } +} diff --git a/src/ccm/events_endksgen.rs b/src/ccm/events_endksgen.rs index 7b77d3c..727fbe5 100644 --- a/src/ccm/events_endksgen.rs +++ b/src/ccm/events_endksgen.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDKSGEN { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDKSGEN`"] +pub type EVENTS_ENDKSGEN_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDKSGEN`"] +pub struct EVENTS_ENDKSGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDKSGEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endksgen(&self) -> EVENTS_ENDKSGEN_R { + EVENTS_ENDKSGEN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endksgen(&mut self) -> EVENTS_ENDKSGEN_W { + EVENTS_ENDKSGEN_W { w: self } + } +} diff --git a/src/ccm/events_error.rs b/src/ccm/events_error.rs index 8bd6113..810699a 100644 --- a/src/ccm/events_error.rs +++ b/src/ccm/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/ccm/tasks_crypt.rs b/src/ccm/tasks_crypt.rs index f8d91d6..c5792fb 100644 --- a/src/ccm/tasks_crypt.rs +++ b/src/ccm/tasks_crypt.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CRYPT { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CRYPT`"] +pub struct TASKS_CRYPT_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CRYPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_crypt(&mut self) -> TASKS_CRYPT_W { + TASKS_CRYPT_W { w: self } + } +} diff --git a/src/ccm/tasks_ksgen.rs b/src/ccm/tasks_ksgen.rs index dedceb3..ba53f68 100644 --- a/src/ccm/tasks_ksgen.rs +++ b/src/ccm/tasks_ksgen.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_KSGEN { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_KSGEN`"] +pub struct TASKS_KSGEN_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_KSGEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_ksgen(&mut self) -> TASKS_KSGEN_W { + TASKS_KSGEN_W { w: self } + } +} diff --git a/src/ccm/tasks_stop.rs b/src/ccm/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/ccm/tasks_stop.rs +++ b/src/ccm/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/clock/events_ctto.rs b/src/clock/events_ctto.rs index 81fe85d..5e5b5e3 100644 --- a/src/clock/events_ctto.rs +++ b/src/clock/events_ctto.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CTTO { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CTTO`"] +pub type EVENTS_CTTO_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CTTO`"] +pub struct EVENTS_CTTO_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CTTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ctto(&self) -> EVENTS_CTTO_R { + EVENTS_CTTO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ctto(&mut self) -> EVENTS_CTTO_W { + EVENTS_CTTO_W { w: self } + } +} diff --git a/src/clock/events_done.rs b/src/clock/events_done.rs index debd5e5..b40b3ab 100644 --- a/src/clock/events_done.rs +++ b/src/clock/events_done.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DONE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DONE`"] +pub type EVENTS_DONE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DONE`"] +pub struct EVENTS_DONE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_done(&self) -> EVENTS_DONE_R { + EVENTS_DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_done(&mut self) -> EVENTS_DONE_W { + EVENTS_DONE_W { w: self } + } +} diff --git a/src/clock/events_hfclkstarted.rs b/src/clock/events_hfclkstarted.rs index 851e045..126eaef 100644 --- a/src/clock/events_hfclkstarted.rs +++ b/src/clock/events_hfclkstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_HFCLKSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_HFCLKSTARTED`"] +pub type EVENTS_HFCLKSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_HFCLKSTARTED`"] +pub struct EVENTS_HFCLKSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_HFCLKSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_hfclkstarted(&self) -> EVENTS_HFCLKSTARTED_R { + EVENTS_HFCLKSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W { + EVENTS_HFCLKSTARTED_W { w: self } + } +} diff --git a/src/clock/events_lfclkstarted.rs b/src/clock/events_lfclkstarted.rs index 4faa87f..ab85f3a 100644 --- a/src/clock/events_lfclkstarted.rs +++ b/src/clock/events_lfclkstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_LFCLKSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_LFCLKSTARTED`"] +pub type EVENTS_LFCLKSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_LFCLKSTARTED`"] +pub struct EVENTS_LFCLKSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_LFCLKSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_lfclkstarted(&self) -> EVENTS_LFCLKSTARTED_R { + EVENTS_LFCLKSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W { + EVENTS_LFCLKSTARTED_W { w: self } + } +} diff --git a/src/clock/tasks_cal.rs b/src/clock/tasks_cal.rs index 94e69b6..74edba0 100644 --- a/src/clock/tasks_cal.rs +++ b/src/clock/tasks_cal.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CAL { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CAL`"] +pub struct TASKS_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_cal(&mut self) -> TASKS_CAL_W { + TASKS_CAL_W { w: self } + } +} diff --git a/src/clock/tasks_ctstart.rs b/src/clock/tasks_ctstart.rs index 9ee0cc0..49e39eb 100644 --- a/src/clock/tasks_ctstart.rs +++ b/src/clock/tasks_ctstart.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CTSTART { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CTSTART`"] +pub struct TASKS_CTSTART_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CTSTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_ctstart(&mut self) -> TASKS_CTSTART_W { + TASKS_CTSTART_W { w: self } + } +} diff --git a/src/clock/tasks_ctstop.rs b/src/clock/tasks_ctstop.rs index e554ae7..28b523d 100644 --- a/src/clock/tasks_ctstop.rs +++ b/src/clock/tasks_ctstop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CTSTOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CTSTOP`"] +pub struct TASKS_CTSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CTSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_ctstop(&mut self) -> TASKS_CTSTOP_W { + TASKS_CTSTOP_W { w: self } + } +} diff --git a/src/clock/tasks_hfclkstart.rs b/src/clock/tasks_hfclkstart.rs index b720d12..663d825 100644 --- a/src/clock/tasks_hfclkstart.rs +++ b/src/clock/tasks_hfclkstart.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_HFCLKSTART { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_HFCLKSTART`"] +pub struct TASKS_HFCLKSTART_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_HFCLKSTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W { + TASKS_HFCLKSTART_W { w: self } + } +} diff --git a/src/clock/tasks_hfclkstop.rs b/src/clock/tasks_hfclkstop.rs index 53f5b65..7beac68 100644 --- a/src/clock/tasks_hfclkstop.rs +++ b/src/clock/tasks_hfclkstop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_HFCLKSTOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_HFCLKSTOP`"] +pub struct TASKS_HFCLKSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_HFCLKSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W { + TASKS_HFCLKSTOP_W { w: self } + } +} diff --git a/src/clock/tasks_lfclkstart.rs b/src/clock/tasks_lfclkstart.rs index 3e1a57a..5777cbe 100644 --- a/src/clock/tasks_lfclkstart.rs +++ b/src/clock/tasks_lfclkstart.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_LFCLKSTART { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_LFCLKSTART`"] +pub struct TASKS_LFCLKSTART_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_LFCLKSTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W { + TASKS_LFCLKSTART_W { w: self } + } +} diff --git a/src/clock/tasks_lfclkstop.rs b/src/clock/tasks_lfclkstop.rs index b4639de..a1846e2 100644 --- a/src/clock/tasks_lfclkstop.rs +++ b/src/clock/tasks_lfclkstop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_LFCLKSTOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_LFCLKSTOP`"] +pub struct TASKS_LFCLKSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_LFCLKSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W { + TASKS_LFCLKSTOP_W { w: self } + } +} diff --git a/src/comp/events_cross.rs b/src/comp/events_cross.rs index 3201f24..2725aa6 100644 --- a/src/comp/events_cross.rs +++ b/src/comp/events_cross.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CROSS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CROSS`"] +pub type EVENTS_CROSS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CROSS`"] +pub struct EVENTS_CROSS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CROSS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cross(&self) -> EVENTS_CROSS_R { + EVENTS_CROSS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cross(&mut self) -> EVENTS_CROSS_W { + EVENTS_CROSS_W { w: self } + } +} diff --git a/src/comp/events_down.rs b/src/comp/events_down.rs index 4c4f49c..41749fb 100644 --- a/src/comp/events_down.rs +++ b/src/comp/events_down.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DOWN { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DOWN`"] +pub type EVENTS_DOWN_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DOWN`"] +pub struct EVENTS_DOWN_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DOWN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_down(&self) -> EVENTS_DOWN_R { + EVENTS_DOWN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_down(&mut self) -> EVENTS_DOWN_W { + EVENTS_DOWN_W { w: self } + } +} diff --git a/src/comp/events_ready.rs b/src/comp/events_ready.rs index df0af9b..b910196 100644 --- a/src/comp/events_ready.rs +++ b/src/comp/events_ready.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_READY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_READY`"] +pub type EVENTS_READY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_READY`"] +pub struct EVENTS_READY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&self) -> EVENTS_READY_R { + EVENTS_READY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&mut self) -> EVENTS_READY_W { + EVENTS_READY_W { w: self } + } +} diff --git a/src/comp/events_up.rs b/src/comp/events_up.rs index e807edf..169d727 100644 --- a/src/comp/events_up.rs +++ b/src/comp/events_up.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_UP { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_UP`"] +pub type EVENTS_UP_R = crate::R; +#[doc = "Write proxy for field `EVENTS_UP`"] +pub struct EVENTS_UP_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_UP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_up(&self) -> EVENTS_UP_R { + EVENTS_UP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_up(&mut self) -> EVENTS_UP_W { + EVENTS_UP_W { w: self } + } +} diff --git a/src/comp/tasks_sample.rs b/src/comp/tasks_sample.rs index e28e974..b5de2b5 100644 --- a/src/comp/tasks_sample.rs +++ b/src/comp/tasks_sample.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SAMPLE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SAMPLE`"] +pub struct TASKS_SAMPLE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SAMPLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W { + TASKS_SAMPLE_W { w: self } + } +} diff --git a/src/comp/tasks_start.rs b/src/comp/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/comp/tasks_start.rs +++ b/src/comp/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/comp/tasks_stop.rs b/src/comp/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/comp/tasks_stop.rs +++ b/src/comp/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/ecb/events_endecb.rs b/src/ecb/events_endecb.rs index 5c17991..6ce983b 100644 --- a/src/ecb/events_endecb.rs +++ b/src/ecb/events_endecb.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDECB { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDECB`"] +pub type EVENTS_ENDECB_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDECB`"] +pub struct EVENTS_ENDECB_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDECB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endecb(&self) -> EVENTS_ENDECB_R { + EVENTS_ENDECB_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endecb(&mut self) -> EVENTS_ENDECB_W { + EVENTS_ENDECB_W { w: self } + } +} diff --git a/src/ecb/events_errorecb.rs b/src/ecb/events_errorecb.rs index 581b700..5f88dfd 100644 --- a/src/ecb/events_errorecb.rs +++ b/src/ecb/events_errorecb.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERRORECB { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERRORECB`"] +pub type EVENTS_ERRORECB_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERRORECB`"] +pub struct EVENTS_ERRORECB_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERRORECB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_errorecb(&self) -> EVENTS_ERRORECB_R { + EVENTS_ERRORECB_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_errorecb(&mut self) -> EVENTS_ERRORECB_W { + EVENTS_ERRORECB_W { w: self } + } +} diff --git a/src/ecb/tasks_startecb.rs b/src/ecb/tasks_startecb.rs index cf0ca8f..cca8e27 100644 --- a/src/ecb/tasks_startecb.rs +++ b/src/ecb/tasks_startecb.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTECB { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTECB`"] +pub struct TASKS_STARTECB_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTECB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_startecb(&mut self) -> TASKS_STARTECB_W { + TASKS_STARTECB_W { w: self } + } +} diff --git a/src/ecb/tasks_stopecb.rs b/src/ecb/tasks_stopecb.rs index e0828af..e4d7d74 100644 --- a/src/ecb/tasks_stopecb.rs +++ b/src/ecb/tasks_stopecb.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOPECB { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOPECB`"] +pub struct TASKS_STOPECB_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOPECB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stopecb(&mut self) -> TASKS_STOPECB_W { + TASKS_STOPECB_W { w: self } + } +} diff --git a/src/gpiote/events_port.rs b/src/gpiote/events_port.rs index d9d4beb..ca1af17 100644 --- a/src/gpiote/events_port.rs +++ b/src/gpiote/events_port.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_PORT { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_PORT`"] +pub type EVENTS_PORT_R = crate::R; +#[doc = "Write proxy for field `EVENTS_PORT`"] +pub struct EVENTS_PORT_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_PORT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_port(&self) -> EVENTS_PORT_R { + EVENTS_PORT_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_port(&mut self) -> EVENTS_PORT_W { + EVENTS_PORT_W { w: self } + } +} diff --git a/src/i2s/events_rxptrupd.rs b/src/i2s/events_rxptrupd.rs index 5ebe452..242bd4b 100644 --- a/src/i2s/events_rxptrupd.rs +++ b/src/i2s/events_rxptrupd.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXPTRUPD { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXPTRUPD`"] +pub type EVENTS_RXPTRUPD_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXPTRUPD`"] +pub struct EVENTS_RXPTRUPD_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXPTRUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxptrupd(&self) -> EVENTS_RXPTRUPD_R { + EVENTS_RXPTRUPD_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxptrupd(&mut self) -> EVENTS_RXPTRUPD_W { + EVENTS_RXPTRUPD_W { w: self } + } +} diff --git a/src/i2s/events_stopped.rs b/src/i2s/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/i2s/events_stopped.rs +++ b/src/i2s/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/i2s/events_txptrupd.rs b/src/i2s/events_txptrupd.rs index a32eada..84c8307 100644 --- a/src/i2s/events_txptrupd.rs +++ b/src/i2s/events_txptrupd.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXPTRUPD { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXPTRUPD`"] +pub type EVENTS_TXPTRUPD_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXPTRUPD`"] +pub struct EVENTS_TXPTRUPD_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXPTRUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txptrupd(&self) -> EVENTS_TXPTRUPD_R { + EVENTS_TXPTRUPD_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txptrupd(&mut self) -> EVENTS_TXPTRUPD_W { + EVENTS_TXPTRUPD_W { w: self } + } +} diff --git a/src/i2s/tasks_start.rs b/src/i2s/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/i2s/tasks_start.rs +++ b/src/i2s/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/i2s/tasks_stop.rs b/src/i2s/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/i2s/tasks_stop.rs +++ b/src/i2s/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/lpcomp/events_cross.rs b/src/lpcomp/events_cross.rs index 3201f24..2725aa6 100644 --- a/src/lpcomp/events_cross.rs +++ b/src/lpcomp/events_cross.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CROSS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CROSS`"] +pub type EVENTS_CROSS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CROSS`"] +pub struct EVENTS_CROSS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CROSS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cross(&self) -> EVENTS_CROSS_R { + EVENTS_CROSS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cross(&mut self) -> EVENTS_CROSS_W { + EVENTS_CROSS_W { w: self } + } +} diff --git a/src/lpcomp/events_down.rs b/src/lpcomp/events_down.rs index 4c4f49c..41749fb 100644 --- a/src/lpcomp/events_down.rs +++ b/src/lpcomp/events_down.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DOWN { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DOWN`"] +pub type EVENTS_DOWN_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DOWN`"] +pub struct EVENTS_DOWN_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DOWN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_down(&self) -> EVENTS_DOWN_R { + EVENTS_DOWN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_down(&mut self) -> EVENTS_DOWN_W { + EVENTS_DOWN_W { w: self } + } +} diff --git a/src/lpcomp/events_ready.rs b/src/lpcomp/events_ready.rs index df0af9b..b910196 100644 --- a/src/lpcomp/events_ready.rs +++ b/src/lpcomp/events_ready.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_READY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_READY`"] +pub type EVENTS_READY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_READY`"] +pub struct EVENTS_READY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&self) -> EVENTS_READY_R { + EVENTS_READY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&mut self) -> EVENTS_READY_W { + EVENTS_READY_W { w: self } + } +} diff --git a/src/lpcomp/events_up.rs b/src/lpcomp/events_up.rs index e807edf..169d727 100644 --- a/src/lpcomp/events_up.rs +++ b/src/lpcomp/events_up.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_UP { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_UP`"] +pub type EVENTS_UP_R = crate::R; +#[doc = "Write proxy for field `EVENTS_UP`"] +pub struct EVENTS_UP_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_UP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_up(&self) -> EVENTS_UP_R { + EVENTS_UP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_up(&mut self) -> EVENTS_UP_W { + EVENTS_UP_W { w: self } + } +} diff --git a/src/lpcomp/tasks_sample.rs b/src/lpcomp/tasks_sample.rs index e28e974..b5de2b5 100644 --- a/src/lpcomp/tasks_sample.rs +++ b/src/lpcomp/tasks_sample.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SAMPLE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SAMPLE`"] +pub struct TASKS_SAMPLE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SAMPLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W { + TASKS_SAMPLE_W { w: self } + } +} diff --git a/src/lpcomp/tasks_start.rs b/src/lpcomp/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/lpcomp/tasks_start.rs +++ b/src/lpcomp/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/lpcomp/tasks_stop.rs b/src/lpcomp/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/lpcomp/tasks_stop.rs +++ b/src/lpcomp/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/nfct/events_autocolresstarted.rs b/src/nfct/events_autocolresstarted.rs index 8fa21cd..6c8be02 100644 --- a/src/nfct/events_autocolresstarted.rs +++ b/src/nfct/events_autocolresstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_AUTOCOLRESSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_AUTOCOLRESSTARTED`"] +pub type EVENTS_AUTOCOLRESSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_AUTOCOLRESSTARTED`"] +pub struct EVENTS_AUTOCOLRESSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_AUTOCOLRESSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_autocolresstarted(&self) -> EVENTS_AUTOCOLRESSTARTED_R { + EVENTS_AUTOCOLRESSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_autocolresstarted(&mut self) -> EVENTS_AUTOCOLRESSTARTED_W { + EVENTS_AUTOCOLRESSTARTED_W { w: self } + } +} diff --git a/src/nfct/events_collision.rs b/src/nfct/events_collision.rs index b622325..a8d4e56 100644 --- a/src/nfct/events_collision.rs +++ b/src/nfct/events_collision.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_COLLISION { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_COLLISION`"] +pub type EVENTS_COLLISION_R = crate::R; +#[doc = "Write proxy for field `EVENTS_COLLISION`"] +pub struct EVENTS_COLLISION_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_COLLISION_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_collision(&self) -> EVENTS_COLLISION_R { + EVENTS_COLLISION_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_collision(&mut self) -> EVENTS_COLLISION_W { + EVENTS_COLLISION_W { w: self } + } +} diff --git a/src/nfct/events_endrx.rs b/src/nfct/events_endrx.rs index 81b6d83..53f61a6 100644 --- a/src/nfct/events_endrx.rs +++ b/src/nfct/events_endrx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDRX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDRX`"] +pub type EVENTS_ENDRX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDRX`"] +pub struct EVENTS_ENDRX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W { + EVENTS_ENDRX_W { w: self } + } +} diff --git a/src/nfct/events_endtx.rs b/src/nfct/events_endtx.rs index 8207be1..0547b10 100644 --- a/src/nfct/events_endtx.rs +++ b/src/nfct/events_endtx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDTX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDTX`"] +pub type EVENTS_ENDTX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDTX`"] +pub struct EVENTS_ENDTX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endtx(&self) -> EVENTS_ENDTX_R { + EVENTS_ENDTX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W { + EVENTS_ENDTX_W { w: self } + } +} diff --git a/src/nfct/events_error.rs b/src/nfct/events_error.rs index 8bd6113..810699a 100644 --- a/src/nfct/events_error.rs +++ b/src/nfct/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/nfct/events_fielddetected.rs b/src/nfct/events_fielddetected.rs index 032d011..d3f42a5 100644 --- a/src/nfct/events_fielddetected.rs +++ b/src/nfct/events_fielddetected.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_FIELDDETECTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_FIELDDETECTED`"] +pub type EVENTS_FIELDDETECTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_FIELDDETECTED`"] +pub struct EVENTS_FIELDDETECTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_FIELDDETECTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_fielddetected(&self) -> EVENTS_FIELDDETECTED_R { + EVENTS_FIELDDETECTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_fielddetected(&mut self) -> EVENTS_FIELDDETECTED_W { + EVENTS_FIELDDETECTED_W { w: self } + } +} diff --git a/src/nfct/events_fieldlost.rs b/src/nfct/events_fieldlost.rs index 40c19df..9450a7f 100644 --- a/src/nfct/events_fieldlost.rs +++ b/src/nfct/events_fieldlost.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_FIELDLOST { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_FIELDLOST`"] +pub type EVENTS_FIELDLOST_R = crate::R; +#[doc = "Write proxy for field `EVENTS_FIELDLOST`"] +pub struct EVENTS_FIELDLOST_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_FIELDLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_fieldlost(&self) -> EVENTS_FIELDLOST_R { + EVENTS_FIELDLOST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_fieldlost(&mut self) -> EVENTS_FIELDLOST_W { + EVENTS_FIELDLOST_W { w: self } + } +} diff --git a/src/nfct/events_ready.rs b/src/nfct/events_ready.rs index df0af9b..b910196 100644 --- a/src/nfct/events_ready.rs +++ b/src/nfct/events_ready.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_READY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_READY`"] +pub type EVENTS_READY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_READY`"] +pub struct EVENTS_READY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&self) -> EVENTS_READY_R { + EVENTS_READY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&mut self) -> EVENTS_READY_W { + EVENTS_READY_W { w: self } + } +} diff --git a/src/nfct/events_rxerror.rs b/src/nfct/events_rxerror.rs index 8caa909..e4236a6 100644 --- a/src/nfct/events_rxerror.rs +++ b/src/nfct/events_rxerror.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXERROR`"] +pub type EVENTS_RXERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXERROR`"] +pub struct EVENTS_RXERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxerror(&self) -> EVENTS_RXERROR_R { + EVENTS_RXERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxerror(&mut self) -> EVENTS_RXERROR_W { + EVENTS_RXERROR_W { w: self } + } +} diff --git a/src/nfct/events_rxframeend.rs b/src/nfct/events_rxframeend.rs index 22e7567..13acbbd 100644 --- a/src/nfct/events_rxframeend.rs +++ b/src/nfct/events_rxframeend.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXFRAMEEND { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXFRAMEEND`"] +pub type EVENTS_RXFRAMEEND_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXFRAMEEND`"] +pub struct EVENTS_RXFRAMEEND_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXFRAMEEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxframeend(&self) -> EVENTS_RXFRAMEEND_R { + EVENTS_RXFRAMEEND_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxframeend(&mut self) -> EVENTS_RXFRAMEEND_W { + EVENTS_RXFRAMEEND_W { w: self } + } +} diff --git a/src/nfct/events_rxframestart.rs b/src/nfct/events_rxframestart.rs index bcb734f..fca9ab6 100644 --- a/src/nfct/events_rxframestart.rs +++ b/src/nfct/events_rxframestart.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXFRAMESTART { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXFRAMESTART`"] +pub type EVENTS_RXFRAMESTART_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXFRAMESTART`"] +pub struct EVENTS_RXFRAMESTART_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXFRAMESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxframestart(&self) -> EVENTS_RXFRAMESTART_R { + EVENTS_RXFRAMESTART_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxframestart(&mut self) -> EVENTS_RXFRAMESTART_W { + EVENTS_RXFRAMESTART_W { w: self } + } +} diff --git a/src/nfct/events_selected.rs b/src/nfct/events_selected.rs index ec40d93..a699739 100644 --- a/src/nfct/events_selected.rs +++ b/src/nfct/events_selected.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_SELECTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SELECTED`"] +pub type EVENTS_SELECTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SELECTED`"] +pub struct EVENTS_SELECTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SELECTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_selected(&self) -> EVENTS_SELECTED_R { + EVENTS_SELECTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_selected(&mut self) -> EVENTS_SELECTED_W { + EVENTS_SELECTED_W { w: self } + } +} diff --git a/src/nfct/events_started.rs b/src/nfct/events_started.rs index 4395b31..5a2f10d 100644 --- a/src/nfct/events_started.rs +++ b/src/nfct/events_started.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STARTED`"] +pub type EVENTS_STARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STARTED`"] +pub struct EVENTS_STARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W { + EVENTS_STARTED_W { w: self } + } +} diff --git a/src/nfct/events_txframeend.rs b/src/nfct/events_txframeend.rs index a81de8a..4658521 100644 --- a/src/nfct/events_txframeend.rs +++ b/src/nfct/events_txframeend.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXFRAMEEND { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXFRAMEEND`"] +pub type EVENTS_TXFRAMEEND_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXFRAMEEND`"] +pub struct EVENTS_TXFRAMEEND_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXFRAMEEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txframeend(&self) -> EVENTS_TXFRAMEEND_R { + EVENTS_TXFRAMEEND_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txframeend(&mut self) -> EVENTS_TXFRAMEEND_W { + EVENTS_TXFRAMEEND_W { w: self } + } +} diff --git a/src/nfct/events_txframestart.rs b/src/nfct/events_txframestart.rs index 5ad4d48..1f82185 100644 --- a/src/nfct/events_txframestart.rs +++ b/src/nfct/events_txframestart.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXFRAMESTART { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXFRAMESTART`"] +pub type EVENTS_TXFRAMESTART_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXFRAMESTART`"] +pub struct EVENTS_TXFRAMESTART_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXFRAMESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txframestart(&self) -> EVENTS_TXFRAMESTART_R { + EVENTS_TXFRAMESTART_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txframestart(&mut self) -> EVENTS_TXFRAMESTART_W { + EVENTS_TXFRAMESTART_W { w: self } + } +} diff --git a/src/nfct/tasks_activate.rs b/src/nfct/tasks_activate.rs index c4896e2..04434b7 100644 --- a/src/nfct/tasks_activate.rs +++ b/src/nfct/tasks_activate.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_ACTIVATE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_ACTIVATE`"] +pub struct TASKS_ACTIVATE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_ACTIVATE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_activate(&mut self) -> TASKS_ACTIVATE_W { + TASKS_ACTIVATE_W { w: self } + } +} diff --git a/src/nfct/tasks_disable.rs b/src/nfct/tasks_disable.rs index e3b7962..3abcca5 100644 --- a/src/nfct/tasks_disable.rs +++ b/src/nfct/tasks_disable.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_DISABLE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_DISABLE`"] +pub struct TASKS_DISABLE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_DISABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W { + TASKS_DISABLE_W { w: self } + } +} diff --git a/src/nfct/tasks_enablerxdata.rs b/src/nfct/tasks_enablerxdata.rs index df37062..43749e1 100644 --- a/src/nfct/tasks_enablerxdata.rs +++ b/src/nfct/tasks_enablerxdata.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_ENABLERXDATA { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_ENABLERXDATA`"] +pub struct TASKS_ENABLERXDATA_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_ENABLERXDATA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_enablerxdata(&mut self) -> TASKS_ENABLERXDATA_W { + TASKS_ENABLERXDATA_W { w: self } + } +} diff --git a/src/nfct/tasks_goidle.rs b/src/nfct/tasks_goidle.rs index 580ba47..903ea8e 100644 --- a/src/nfct/tasks_goidle.rs +++ b/src/nfct/tasks_goidle.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_GOIDLE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_GOIDLE`"] +pub struct TASKS_GOIDLE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_GOIDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_goidle(&mut self) -> TASKS_GOIDLE_W { + TASKS_GOIDLE_W { w: self } + } +} diff --git a/src/nfct/tasks_gosleep.rs b/src/nfct/tasks_gosleep.rs index a8eb5db..cc512ea 100644 --- a/src/nfct/tasks_gosleep.rs +++ b/src/nfct/tasks_gosleep.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_GOSLEEP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_GOSLEEP`"] +pub struct TASKS_GOSLEEP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_GOSLEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_gosleep(&mut self) -> TASKS_GOSLEEP_W { + TASKS_GOSLEEP_W { w: self } + } +} diff --git a/src/nfct/tasks_sense.rs b/src/nfct/tasks_sense.rs index 615085a..a9deb49 100644 --- a/src/nfct/tasks_sense.rs +++ b/src/nfct/tasks_sense.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SENSE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SENSE`"] +pub struct TASKS_SENSE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SENSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_sense(&mut self) -> TASKS_SENSE_W { + TASKS_SENSE_W { w: self } + } +} diff --git a/src/nfct/tasks_starttx.rs b/src/nfct/tasks_starttx.rs index 7db7b10..b48bc8c 100644 --- a/src/nfct/tasks_starttx.rs +++ b/src/nfct/tasks_starttx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTTX`"] +pub struct TASKS_STARTTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W { + TASKS_STARTTX_W { w: self } + } +} diff --git a/src/pdm/events_end.rs b/src/pdm/events_end.rs index 90e8b57..f2020c9 100644 --- a/src/pdm/events_end.rs +++ b/src/pdm/events_end.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_END { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_END`"] +pub type EVENTS_END_R = crate::R; +#[doc = "Write proxy for field `EVENTS_END`"] +pub struct EVENTS_END_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_END_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W { + EVENTS_END_W { w: self } + } +} diff --git a/src/pdm/events_started.rs b/src/pdm/events_started.rs index 4395b31..5a2f10d 100644 --- a/src/pdm/events_started.rs +++ b/src/pdm/events_started.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STARTED`"] +pub type EVENTS_STARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STARTED`"] +pub struct EVENTS_STARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W { + EVENTS_STARTED_W { w: self } + } +} diff --git a/src/pdm/events_stopped.rs b/src/pdm/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/pdm/events_stopped.rs +++ b/src/pdm/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/pdm/tasks_start.rs b/src/pdm/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/pdm/tasks_start.rs +++ b/src/pdm/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/pdm/tasks_stop.rs b/src/pdm/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/pdm/tasks_stop.rs +++ b/src/pdm/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/power/events_pofwarn.rs b/src/power/events_pofwarn.rs index 0bb793d..e1bb5f0 100644 --- a/src/power/events_pofwarn.rs +++ b/src/power/events_pofwarn.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_POFWARN { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_POFWARN`"] +pub type EVENTS_POFWARN_R = crate::R; +#[doc = "Write proxy for field `EVENTS_POFWARN`"] +pub struct EVENTS_POFWARN_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_POFWARN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_pofwarn(&self) -> EVENTS_POFWARN_R { + EVENTS_POFWARN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_pofwarn(&mut self) -> EVENTS_POFWARN_W { + EVENTS_POFWARN_W { w: self } + } +} diff --git a/src/power/events_sleepenter.rs b/src/power/events_sleepenter.rs index c3e8807..94a45b8 100644 --- a/src/power/events_sleepenter.rs +++ b/src/power/events_sleepenter.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_SLEEPENTER { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SLEEPENTER`"] +pub type EVENTS_SLEEPENTER_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SLEEPENTER`"] +pub struct EVENTS_SLEEPENTER_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SLEEPENTER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_sleepenter(&self) -> EVENTS_SLEEPENTER_R { + EVENTS_SLEEPENTER_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_sleepenter(&mut self) -> EVENTS_SLEEPENTER_W { + EVENTS_SLEEPENTER_W { w: self } + } +} diff --git a/src/power/events_sleepexit.rs b/src/power/events_sleepexit.rs index ba831ef..631fca0 100644 --- a/src/power/events_sleepexit.rs +++ b/src/power/events_sleepexit.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_SLEEPEXIT { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SLEEPEXIT`"] +pub type EVENTS_SLEEPEXIT_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SLEEPEXIT`"] +pub struct EVENTS_SLEEPEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SLEEPEXIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_sleepexit(&self) -> EVENTS_SLEEPEXIT_R { + EVENTS_SLEEPEXIT_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_sleepexit(&mut self) -> EVENTS_SLEEPEXIT_W { + EVENTS_SLEEPEXIT_W { w: self } + } +} diff --git a/src/power/tasks_constlat.rs b/src/power/tasks_constlat.rs index 5462eef..d7fe7c4 100644 --- a/src/power/tasks_constlat.rs +++ b/src/power/tasks_constlat.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CONSTLAT { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CONSTLAT`"] +pub struct TASKS_CONSTLAT_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CONSTLAT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_constlat(&mut self) -> TASKS_CONSTLAT_W { + TASKS_CONSTLAT_W { w: self } + } +} diff --git a/src/power/tasks_lowpwr.rs b/src/power/tasks_lowpwr.rs index 9ede2b2..134d236 100644 --- a/src/power/tasks_lowpwr.rs +++ b/src/power/tasks_lowpwr.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_LOWPWR { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_LOWPWR`"] +pub struct TASKS_LOWPWR_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_LOWPWR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_lowpwr(&mut self) -> TASKS_LOWPWR_W { + TASKS_LOWPWR_W { w: self } + } +} diff --git a/src/pwm0/events_loopsdone.rs b/src/pwm0/events_loopsdone.rs index 4e98f47..258b429 100644 --- a/src/pwm0/events_loopsdone.rs +++ b/src/pwm0/events_loopsdone.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_LOOPSDONE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_LOOPSDONE`"] +pub type EVENTS_LOOPSDONE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_LOOPSDONE`"] +pub struct EVENTS_LOOPSDONE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_LOOPSDONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_loopsdone(&self) -> EVENTS_LOOPSDONE_R { + EVENTS_LOOPSDONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_loopsdone(&mut self) -> EVENTS_LOOPSDONE_W { + EVENTS_LOOPSDONE_W { w: self } + } +} diff --git a/src/pwm0/events_pwmperiodend.rs b/src/pwm0/events_pwmperiodend.rs index f14721b..3f4beb6 100644 --- a/src/pwm0/events_pwmperiodend.rs +++ b/src/pwm0/events_pwmperiodend.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_PWMPERIODEND { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_PWMPERIODEND`"] +pub type EVENTS_PWMPERIODEND_R = crate::R; +#[doc = "Write proxy for field `EVENTS_PWMPERIODEND`"] +pub struct EVENTS_PWMPERIODEND_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_PWMPERIODEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_pwmperiodend(&self) -> EVENTS_PWMPERIODEND_R { + EVENTS_PWMPERIODEND_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_pwmperiodend(&mut self) -> EVENTS_PWMPERIODEND_W { + EVENTS_PWMPERIODEND_W { w: self } + } +} diff --git a/src/pwm0/events_stopped.rs b/src/pwm0/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/pwm0/events_stopped.rs +++ b/src/pwm0/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/pwm0/tasks_nextstep.rs b/src/pwm0/tasks_nextstep.rs index baae389..257a0ae 100644 --- a/src/pwm0/tasks_nextstep.rs +++ b/src/pwm0/tasks_nextstep.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_NEXTSTEP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_NEXTSTEP`"] +pub struct TASKS_NEXTSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_NEXTSTEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_nextstep(&mut self) -> TASKS_NEXTSTEP_W { + TASKS_NEXTSTEP_W { w: self } + } +} diff --git a/src/pwm0/tasks_stop.rs b/src/pwm0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/pwm0/tasks_stop.rs +++ b/src/pwm0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/qdec/events_accof.rs b/src/qdec/events_accof.rs index 46fd14d..b46a7a1 100644 --- a/src/qdec/events_accof.rs +++ b/src/qdec/events_accof.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ACCOF { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ACCOF`"] +pub type EVENTS_ACCOF_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ACCOF`"] +pub struct EVENTS_ACCOF_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ACCOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_accof(&self) -> EVENTS_ACCOF_R { + EVENTS_ACCOF_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_accof(&mut self) -> EVENTS_ACCOF_W { + EVENTS_ACCOF_W { w: self } + } +} diff --git a/src/qdec/events_dblrdy.rs b/src/qdec/events_dblrdy.rs index 5c6c2fc..afdeb20 100644 --- a/src/qdec/events_dblrdy.rs +++ b/src/qdec/events_dblrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DBLRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DBLRDY`"] +pub type EVENTS_DBLRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DBLRDY`"] +pub struct EVENTS_DBLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DBLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_dblrdy(&self) -> EVENTS_DBLRDY_R { + EVENTS_DBLRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_dblrdy(&mut self) -> EVENTS_DBLRDY_W { + EVENTS_DBLRDY_W { w: self } + } +} diff --git a/src/qdec/events_reportrdy.rs b/src/qdec/events_reportrdy.rs index 449084e..e6f020e 100644 --- a/src/qdec/events_reportrdy.rs +++ b/src/qdec/events_reportrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_REPORTRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_REPORTRDY`"] +pub type EVENTS_REPORTRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_REPORTRDY`"] +pub struct EVENTS_REPORTRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_REPORTRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_reportrdy(&self) -> EVENTS_REPORTRDY_R { + EVENTS_REPORTRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_reportrdy(&mut self) -> EVENTS_REPORTRDY_W { + EVENTS_REPORTRDY_W { w: self } + } +} diff --git a/src/qdec/events_samplerdy.rs b/src/qdec/events_samplerdy.rs index b390fd7..753420e 100644 --- a/src/qdec/events_samplerdy.rs +++ b/src/qdec/events_samplerdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_SAMPLERDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SAMPLERDY`"] +pub type EVENTS_SAMPLERDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SAMPLERDY`"] +pub struct EVENTS_SAMPLERDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SAMPLERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_samplerdy(&self) -> EVENTS_SAMPLERDY_R { + EVENTS_SAMPLERDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_samplerdy(&mut self) -> EVENTS_SAMPLERDY_W { + EVENTS_SAMPLERDY_W { w: self } + } +} diff --git a/src/qdec/events_stopped.rs b/src/qdec/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/qdec/events_stopped.rs +++ b/src/qdec/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/qdec/tasks_rdclracc.rs b/src/qdec/tasks_rdclracc.rs index 67760d1..9a23eed 100644 --- a/src/qdec/tasks_rdclracc.rs +++ b/src/qdec/tasks_rdclracc.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RDCLRACC { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RDCLRACC`"] +pub struct TASKS_RDCLRACC_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RDCLRACC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_rdclracc(&mut self) -> TASKS_RDCLRACC_W { + TASKS_RDCLRACC_W { w: self } + } +} diff --git a/src/qdec/tasks_rdclrdbl.rs b/src/qdec/tasks_rdclrdbl.rs index 81ae767..0035d73 100644 --- a/src/qdec/tasks_rdclrdbl.rs +++ b/src/qdec/tasks_rdclrdbl.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RDCLRDBL { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RDCLRDBL`"] +pub struct TASKS_RDCLRDBL_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RDCLRDBL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_rdclrdbl(&mut self) -> TASKS_RDCLRDBL_W { + TASKS_RDCLRDBL_W { w: self } + } +} diff --git a/src/qdec/tasks_readclracc.rs b/src/qdec/tasks_readclracc.rs index a008fc5..30c2432 100644 --- a/src/qdec/tasks_readclracc.rs +++ b/src/qdec/tasks_readclracc.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_READCLRACC { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_READCLRACC`"] +pub struct TASKS_READCLRACC_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_READCLRACC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_readclracc(&mut self) -> TASKS_READCLRACC_W { + TASKS_READCLRACC_W { w: self } + } +} diff --git a/src/qdec/tasks_start.rs b/src/qdec/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/qdec/tasks_start.rs +++ b/src/qdec/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/qdec/tasks_stop.rs b/src/qdec/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/qdec/tasks_stop.rs +++ b/src/qdec/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/radio/events_address.rs b/src/radio/events_address.rs index 6f2253f..c3dc782 100644 --- a/src/radio/events_address.rs +++ b/src/radio/events_address.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ADDRESS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ADDRESS`"] +pub type EVENTS_ADDRESS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ADDRESS`"] +pub struct EVENTS_ADDRESS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ADDRESS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_address(&self) -> EVENTS_ADDRESS_R { + EVENTS_ADDRESS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_address(&mut self) -> EVENTS_ADDRESS_W { + EVENTS_ADDRESS_W { w: self } + } +} diff --git a/src/radio/events_bcmatch.rs b/src/radio/events_bcmatch.rs index 30b6711..939ab0a 100644 --- a/src/radio/events_bcmatch.rs +++ b/src/radio/events_bcmatch.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_BCMATCH { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_BCMATCH`"] +pub type EVENTS_BCMATCH_R = crate::R; +#[doc = "Write proxy for field `EVENTS_BCMATCH`"] +pub struct EVENTS_BCMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_BCMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_bcmatch(&self) -> EVENTS_BCMATCH_R { + EVENTS_BCMATCH_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_bcmatch(&mut self) -> EVENTS_BCMATCH_W { + EVENTS_BCMATCH_W { w: self } + } +} diff --git a/src/radio/events_crcerror.rs b/src/radio/events_crcerror.rs index 3172cd3..694c34c 100644 --- a/src/radio/events_crcerror.rs +++ b/src/radio/events_crcerror.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CRCERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CRCERROR`"] +pub type EVENTS_CRCERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CRCERROR`"] +pub struct EVENTS_CRCERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CRCERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_crcerror(&self) -> EVENTS_CRCERROR_R { + EVENTS_CRCERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_crcerror(&mut self) -> EVENTS_CRCERROR_W { + EVENTS_CRCERROR_W { w: self } + } +} diff --git a/src/radio/events_crcok.rs b/src/radio/events_crcok.rs index 553d865..bada622 100644 --- a/src/radio/events_crcok.rs +++ b/src/radio/events_crcok.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CRCOK { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CRCOK`"] +pub type EVENTS_CRCOK_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CRCOK`"] +pub struct EVENTS_CRCOK_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CRCOK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_crcok(&self) -> EVENTS_CRCOK_R { + EVENTS_CRCOK_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_crcok(&mut self) -> EVENTS_CRCOK_W { + EVENTS_CRCOK_W { w: self } + } +} diff --git a/src/radio/events_devmatch.rs b/src/radio/events_devmatch.rs index 104559d..62642af 100644 --- a/src/radio/events_devmatch.rs +++ b/src/radio/events_devmatch.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DEVMATCH { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DEVMATCH`"] +pub type EVENTS_DEVMATCH_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DEVMATCH`"] +pub struct EVENTS_DEVMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DEVMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_devmatch(&self) -> EVENTS_DEVMATCH_R { + EVENTS_DEVMATCH_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_devmatch(&mut self) -> EVENTS_DEVMATCH_W { + EVENTS_DEVMATCH_W { w: self } + } +} diff --git a/src/radio/events_devmiss.rs b/src/radio/events_devmiss.rs index f083c9d..6aad4b7 100644 --- a/src/radio/events_devmiss.rs +++ b/src/radio/events_devmiss.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DEVMISS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DEVMISS`"] +pub type EVENTS_DEVMISS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DEVMISS`"] +pub struct EVENTS_DEVMISS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DEVMISS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_devmiss(&self) -> EVENTS_DEVMISS_R { + EVENTS_DEVMISS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_devmiss(&mut self) -> EVENTS_DEVMISS_W { + EVENTS_DEVMISS_W { w: self } + } +} diff --git a/src/radio/events_disabled.rs b/src/radio/events_disabled.rs index d488a0a..37d18de 100644 --- a/src/radio/events_disabled.rs +++ b/src/radio/events_disabled.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DISABLED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DISABLED`"] +pub type EVENTS_DISABLED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DISABLED`"] +pub struct EVENTS_DISABLED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DISABLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_disabled(&self) -> EVENTS_DISABLED_R { + EVENTS_DISABLED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_disabled(&mut self) -> EVENTS_DISABLED_W { + EVENTS_DISABLED_W { w: self } + } +} diff --git a/src/radio/events_end.rs b/src/radio/events_end.rs index 90e8b57..f2020c9 100644 --- a/src/radio/events_end.rs +++ b/src/radio/events_end.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_END { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_END`"] +pub type EVENTS_END_R = crate::R; +#[doc = "Write proxy for field `EVENTS_END`"] +pub struct EVENTS_END_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_END_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W { + EVENTS_END_W { w: self } + } +} diff --git a/src/radio/events_payload.rs b/src/radio/events_payload.rs index 5a62e5a..ac942b4 100644 --- a/src/radio/events_payload.rs +++ b/src/radio/events_payload.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_PAYLOAD { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_PAYLOAD`"] +pub type EVENTS_PAYLOAD_R = crate::R; +#[doc = "Write proxy for field `EVENTS_PAYLOAD`"] +pub struct EVENTS_PAYLOAD_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_PAYLOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_payload(&self) -> EVENTS_PAYLOAD_R { + EVENTS_PAYLOAD_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_payload(&mut self) -> EVENTS_PAYLOAD_W { + EVENTS_PAYLOAD_W { w: self } + } +} diff --git a/src/radio/events_ready.rs b/src/radio/events_ready.rs index df0af9b..b910196 100644 --- a/src/radio/events_ready.rs +++ b/src/radio/events_ready.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_READY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_READY`"] +pub type EVENTS_READY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_READY`"] +pub struct EVENTS_READY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&self) -> EVENTS_READY_R { + EVENTS_READY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&mut self) -> EVENTS_READY_W { + EVENTS_READY_W { w: self } + } +} diff --git a/src/radio/events_rssiend.rs b/src/radio/events_rssiend.rs index ea643f4..0a81d96 100644 --- a/src/radio/events_rssiend.rs +++ b/src/radio/events_rssiend.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RSSIEND { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RSSIEND`"] +pub type EVENTS_RSSIEND_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RSSIEND`"] +pub struct EVENTS_RSSIEND_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RSSIEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rssiend(&self) -> EVENTS_RSSIEND_R { + EVENTS_RSSIEND_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rssiend(&mut self) -> EVENTS_RSSIEND_W { + EVENTS_RSSIEND_W { w: self } + } +} diff --git a/src/radio/tasks_bcstart.rs b/src/radio/tasks_bcstart.rs index 3908c55..7cf2f9d 100644 --- a/src/radio/tasks_bcstart.rs +++ b/src/radio/tasks_bcstart.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_BCSTART { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_BCSTART`"] +pub struct TASKS_BCSTART_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_BCSTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_bcstart(&mut self) -> TASKS_BCSTART_W { + TASKS_BCSTART_W { w: self } + } +} diff --git a/src/radio/tasks_bcstop.rs b/src/radio/tasks_bcstop.rs index 6481a10..3d5cf44 100644 --- a/src/radio/tasks_bcstop.rs +++ b/src/radio/tasks_bcstop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_BCSTOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_BCSTOP`"] +pub struct TASKS_BCSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_BCSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_bcstop(&mut self) -> TASKS_BCSTOP_W { + TASKS_BCSTOP_W { w: self } + } +} diff --git a/src/radio/tasks_disable.rs b/src/radio/tasks_disable.rs index e3b7962..3abcca5 100644 --- a/src/radio/tasks_disable.rs +++ b/src/radio/tasks_disable.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_DISABLE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_DISABLE`"] +pub struct TASKS_DISABLE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_DISABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W { + TASKS_DISABLE_W { w: self } + } +} diff --git a/src/radio/tasks_rssistart.rs b/src/radio/tasks_rssistart.rs index a85002f..3f9ef70 100644 --- a/src/radio/tasks_rssistart.rs +++ b/src/radio/tasks_rssistart.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RSSISTART { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RSSISTART`"] +pub struct TASKS_RSSISTART_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RSSISTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_rssistart(&mut self) -> TASKS_RSSISTART_W { + TASKS_RSSISTART_W { w: self } + } +} diff --git a/src/radio/tasks_rssistop.rs b/src/radio/tasks_rssistop.rs index bf44453..f624079 100644 --- a/src/radio/tasks_rssistop.rs +++ b/src/radio/tasks_rssistop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RSSISTOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RSSISTOP`"] +pub struct TASKS_RSSISTOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RSSISTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_rssistop(&mut self) -> TASKS_RSSISTOP_W { + TASKS_RSSISTOP_W { w: self } + } +} diff --git a/src/radio/tasks_rxen.rs b/src/radio/tasks_rxen.rs index ba8adc8..c048ee5 100644 --- a/src/radio/tasks_rxen.rs +++ b/src/radio/tasks_rxen.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RXEN { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RXEN`"] +pub struct TASKS_RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_rxen(&mut self) -> TASKS_RXEN_W { + TASKS_RXEN_W { w: self } + } +} diff --git a/src/radio/tasks_start.rs b/src/radio/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/radio/tasks_start.rs +++ b/src/radio/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/radio/tasks_stop.rs b/src/radio/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/radio/tasks_stop.rs +++ b/src/radio/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/radio/tasks_txen.rs b/src/radio/tasks_txen.rs index ace7d13..a052672 100644 --- a/src/radio/tasks_txen.rs +++ b/src/radio/tasks_txen.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_TXEN { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_TXEN`"] +pub struct TASKS_TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_txen(&mut self) -> TASKS_TXEN_W { + TASKS_TXEN_W { w: self } + } +} diff --git a/src/rng/events_valrdy.rs b/src/rng/events_valrdy.rs index d05ac96..0c2980f 100644 --- a/src/rng/events_valrdy.rs +++ b/src/rng/events_valrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_VALRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_VALRDY`"] +pub type EVENTS_VALRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_VALRDY`"] +pub struct EVENTS_VALRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_VALRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_valrdy(&self) -> EVENTS_VALRDY_R { + EVENTS_VALRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_valrdy(&mut self) -> EVENTS_VALRDY_W { + EVENTS_VALRDY_W { w: self } + } +} diff --git a/src/rng/tasks_start.rs b/src/rng/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/rng/tasks_start.rs +++ b/src/rng/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/rng/tasks_stop.rs b/src/rng/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/rng/tasks_stop.rs +++ b/src/rng/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/rtc0/events_ovrflw.rs b/src/rtc0/events_ovrflw.rs index d567458..ac93607 100644 --- a/src/rtc0/events_ovrflw.rs +++ b/src/rtc0/events_ovrflw.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_OVRFLW { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_OVRFLW`"] +pub type EVENTS_OVRFLW_R = crate::R; +#[doc = "Write proxy for field `EVENTS_OVRFLW`"] +pub struct EVENTS_OVRFLW_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_OVRFLW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ovrflw(&self) -> EVENTS_OVRFLW_R { + EVENTS_OVRFLW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ovrflw(&mut self) -> EVENTS_OVRFLW_W { + EVENTS_OVRFLW_W { w: self } + } +} diff --git a/src/rtc0/events_tick.rs b/src/rtc0/events_tick.rs index 5eb2ecf..3f270d7 100644 --- a/src/rtc0/events_tick.rs +++ b/src/rtc0/events_tick.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TICK { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TICK`"] +pub type EVENTS_TICK_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TICK`"] +pub struct EVENTS_TICK_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TICK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_tick(&self) -> EVENTS_TICK_R { + EVENTS_TICK_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_tick(&mut self) -> EVENTS_TICK_W { + EVENTS_TICK_W { w: self } + } +} diff --git a/src/rtc0/tasks_clear.rs b/src/rtc0/tasks_clear.rs index c2b61e5..f452e06 100644 --- a/src/rtc0/tasks_clear.rs +++ b/src/rtc0/tasks_clear.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CLEAR { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CLEAR`"] +pub struct TASKS_CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CLEAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W { + TASKS_CLEAR_W { w: self } + } +} diff --git a/src/rtc0/tasks_start.rs b/src/rtc0/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/rtc0/tasks_start.rs +++ b/src/rtc0/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/rtc0/tasks_stop.rs b/src/rtc0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/rtc0/tasks_stop.rs +++ b/src/rtc0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/rtc0/tasks_trigovrflw.rs b/src/rtc0/tasks_trigovrflw.rs index e5bba4b..61e62df 100644 --- a/src/rtc0/tasks_trigovrflw.rs +++ b/src/rtc0/tasks_trigovrflw.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_TRIGOVRFLW { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_TRIGOVRFLW`"] +pub struct TASKS_TRIGOVRFLW_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_TRIGOVRFLW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_trigovrflw(&mut self) -> TASKS_TRIGOVRFLW_W { + TASKS_TRIGOVRFLW_W { w: self } + } +} diff --git a/src/saadc/events_calibratedone.rs b/src/saadc/events_calibratedone.rs index ae725f5..42038e0 100644 --- a/src/saadc/events_calibratedone.rs +++ b/src/saadc/events_calibratedone.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CALIBRATEDONE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CALIBRATEDONE`"] +pub type EVENTS_CALIBRATEDONE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CALIBRATEDONE`"] +pub struct EVENTS_CALIBRATEDONE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CALIBRATEDONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_calibratedone(&self) -> EVENTS_CALIBRATEDONE_R { + EVENTS_CALIBRATEDONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_calibratedone(&mut self) -> EVENTS_CALIBRATEDONE_W { + EVENTS_CALIBRATEDONE_W { w: self } + } +} diff --git a/src/saadc/events_done.rs b/src/saadc/events_done.rs index debd5e5..b40b3ab 100644 --- a/src/saadc/events_done.rs +++ b/src/saadc/events_done.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DONE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DONE`"] +pub type EVENTS_DONE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DONE`"] +pub struct EVENTS_DONE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_done(&self) -> EVENTS_DONE_R { + EVENTS_DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_done(&mut self) -> EVENTS_DONE_W { + EVENTS_DONE_W { w: self } + } +} diff --git a/src/saadc/events_end.rs b/src/saadc/events_end.rs index 90e8b57..f2020c9 100644 --- a/src/saadc/events_end.rs +++ b/src/saadc/events_end.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_END { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_END`"] +pub type EVENTS_END_R = crate::R; +#[doc = "Write proxy for field `EVENTS_END`"] +pub struct EVENTS_END_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_END_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W { + EVENTS_END_W { w: self } + } +} diff --git a/src/saadc/events_resultdone.rs b/src/saadc/events_resultdone.rs index 9248c17..4bf31fe 100644 --- a/src/saadc/events_resultdone.rs +++ b/src/saadc/events_resultdone.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RESULTDONE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RESULTDONE`"] +pub type EVENTS_RESULTDONE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RESULTDONE`"] +pub struct EVENTS_RESULTDONE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RESULTDONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_resultdone(&self) -> EVENTS_RESULTDONE_R { + EVENTS_RESULTDONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_resultdone(&mut self) -> EVENTS_RESULTDONE_W { + EVENTS_RESULTDONE_W { w: self } + } +} diff --git a/src/saadc/events_started.rs b/src/saadc/events_started.rs index 4395b31..5a2f10d 100644 --- a/src/saadc/events_started.rs +++ b/src/saadc/events_started.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STARTED`"] +pub type EVENTS_STARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STARTED`"] +pub struct EVENTS_STARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W { + EVENTS_STARTED_W { w: self } + } +} diff --git a/src/saadc/events_stopped.rs b/src/saadc/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/saadc/events_stopped.rs +++ b/src/saadc/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/saadc/tasks_calibrateoffset.rs b/src/saadc/tasks_calibrateoffset.rs index 8326969..52e1db8 100644 --- a/src/saadc/tasks_calibrateoffset.rs +++ b/src/saadc/tasks_calibrateoffset.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CALIBRATEOFFSET { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CALIBRATEOFFSET`"] +pub struct TASKS_CALIBRATEOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CALIBRATEOFFSET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_calibrateoffset(&mut self) -> TASKS_CALIBRATEOFFSET_W { + TASKS_CALIBRATEOFFSET_W { w: self } + } +} diff --git a/src/saadc/tasks_sample.rs b/src/saadc/tasks_sample.rs index e28e974..b5de2b5 100644 --- a/src/saadc/tasks_sample.rs +++ b/src/saadc/tasks_sample.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SAMPLE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SAMPLE`"] +pub struct TASKS_SAMPLE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SAMPLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W { + TASKS_SAMPLE_W { w: self } + } +} diff --git a/src/saadc/tasks_start.rs b/src/saadc/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/saadc/tasks_start.rs +++ b/src/saadc/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/saadc/tasks_stop.rs b/src/saadc/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/saadc/tasks_stop.rs +++ b/src/saadc/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/spi0/events_ready.rs b/src/spi0/events_ready.rs index df0af9b..b910196 100644 --- a/src/spi0/events_ready.rs +++ b/src/spi0/events_ready.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_READY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_READY`"] +pub type EVENTS_READY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_READY`"] +pub struct EVENTS_READY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&self) -> EVENTS_READY_R { + EVENTS_READY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ready(&mut self) -> EVENTS_READY_W { + EVENTS_READY_W { w: self } + } +} diff --git a/src/spim0/events_end.rs b/src/spim0/events_end.rs index 90e8b57..f2020c9 100644 --- a/src/spim0/events_end.rs +++ b/src/spim0/events_end.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_END { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_END`"] +pub type EVENTS_END_R = crate::R; +#[doc = "Write proxy for field `EVENTS_END`"] +pub struct EVENTS_END_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_END_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W { + EVENTS_END_W { w: self } + } +} diff --git a/src/spim0/events_endrx.rs b/src/spim0/events_endrx.rs index 81b6d83..53f61a6 100644 --- a/src/spim0/events_endrx.rs +++ b/src/spim0/events_endrx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDRX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDRX`"] +pub type EVENTS_ENDRX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDRX`"] +pub struct EVENTS_ENDRX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W { + EVENTS_ENDRX_W { w: self } + } +} diff --git a/src/spim0/events_endtx.rs b/src/spim0/events_endtx.rs index 8207be1..0547b10 100644 --- a/src/spim0/events_endtx.rs +++ b/src/spim0/events_endtx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDTX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDTX`"] +pub type EVENTS_ENDTX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDTX`"] +pub struct EVENTS_ENDTX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endtx(&self) -> EVENTS_ENDTX_R { + EVENTS_ENDTX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W { + EVENTS_ENDTX_W { w: self } + } +} diff --git a/src/spim0/events_started.rs b/src/spim0/events_started.rs index 4395b31..5a2f10d 100644 --- a/src/spim0/events_started.rs +++ b/src/spim0/events_started.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STARTED`"] +pub type EVENTS_STARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STARTED`"] +pub struct EVENTS_STARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&self) -> EVENTS_STARTED_R { + EVENTS_STARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_started(&mut self) -> EVENTS_STARTED_W { + EVENTS_STARTED_W { w: self } + } +} diff --git a/src/spim0/events_stopped.rs b/src/spim0/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/spim0/events_stopped.rs +++ b/src/spim0/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/spim0/tasks_resume.rs b/src/spim0/tasks_resume.rs index 1ce7bdb..4d908e0 100644 --- a/src/spim0/tasks_resume.rs +++ b/src/spim0/tasks_resume.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RESUME { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RESUME`"] +pub struct TASKS_RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W { + TASKS_RESUME_W { w: self } + } +} diff --git a/src/spim0/tasks_start.rs b/src/spim0/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/spim0/tasks_start.rs +++ b/src/spim0/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/spim0/tasks_stop.rs b/src/spim0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/spim0/tasks_stop.rs +++ b/src/spim0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/spim0/tasks_suspend.rs b/src/spim0/tasks_suspend.rs index 6d6e95f..d0ac7a7 100644 --- a/src/spim0/tasks_suspend.rs +++ b/src/spim0/tasks_suspend.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SUSPEND { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SUSPEND`"] +pub struct TASKS_SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W { + TASKS_SUSPEND_W { w: self } + } +} diff --git a/src/spis0/events_acquired.rs b/src/spis0/events_acquired.rs index a120429..8571d5c 100644 --- a/src/spis0/events_acquired.rs +++ b/src/spis0/events_acquired.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ACQUIRED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ACQUIRED`"] +pub type EVENTS_ACQUIRED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ACQUIRED`"] +pub struct EVENTS_ACQUIRED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ACQUIRED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_acquired(&self) -> EVENTS_ACQUIRED_R { + EVENTS_ACQUIRED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_acquired(&mut self) -> EVENTS_ACQUIRED_W { + EVENTS_ACQUIRED_W { w: self } + } +} diff --git a/src/spis0/events_end.rs b/src/spis0/events_end.rs index 90e8b57..f2020c9 100644 --- a/src/spis0/events_end.rs +++ b/src/spis0/events_end.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_END { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_END`"] +pub type EVENTS_END_R = crate::R; +#[doc = "Write proxy for field `EVENTS_END`"] +pub struct EVENTS_END_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_END_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&self) -> EVENTS_END_R { + EVENTS_END_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_end(&mut self) -> EVENTS_END_W { + EVENTS_END_W { w: self } + } +} diff --git a/src/spis0/events_endrx.rs b/src/spis0/events_endrx.rs index 81b6d83..53f61a6 100644 --- a/src/spis0/events_endrx.rs +++ b/src/spis0/events_endrx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDRX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDRX`"] +pub type EVENTS_ENDRX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDRX`"] +pub struct EVENTS_ENDRX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W { + EVENTS_ENDRX_W { w: self } + } +} diff --git a/src/spis0/tasks_acquire.rs b/src/spis0/tasks_acquire.rs index 83ff592..f57868a 100644 --- a/src/spis0/tasks_acquire.rs +++ b/src/spis0/tasks_acquire.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_ACQUIRE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_ACQUIRE`"] +pub struct TASKS_ACQUIRE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_ACQUIRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_acquire(&mut self) -> TASKS_ACQUIRE_W { + TASKS_ACQUIRE_W { w: self } + } +} diff --git a/src/spis0/tasks_release.rs b/src/spis0/tasks_release.rs index bb6d08c..c78192d 100644 --- a/src/spis0/tasks_release.rs +++ b/src/spis0/tasks_release.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RELEASE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RELEASE`"] +pub struct TASKS_RELEASE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RELEASE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_release(&mut self) -> TASKS_RELEASE_W { + TASKS_RELEASE_W { w: self } + } +} diff --git a/src/temp/events_datardy.rs b/src/temp/events_datardy.rs index ed74d57..b7bd47a 100644 --- a/src/temp/events_datardy.rs +++ b/src/temp/events_datardy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_DATARDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_DATARDY`"] +pub type EVENTS_DATARDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_DATARDY`"] +pub struct EVENTS_DATARDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_DATARDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_datardy(&self) -> EVENTS_DATARDY_R { + EVENTS_DATARDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_datardy(&mut self) -> EVENTS_DATARDY_W { + EVENTS_DATARDY_W { w: self } + } +} diff --git a/src/temp/tasks_start.rs b/src/temp/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/temp/tasks_start.rs +++ b/src/temp/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/temp/tasks_stop.rs b/src/temp/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/temp/tasks_stop.rs +++ b/src/temp/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/timer0/tasks_clear.rs b/src/timer0/tasks_clear.rs index c2b61e5..f452e06 100644 --- a/src/timer0/tasks_clear.rs +++ b/src/timer0/tasks_clear.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CLEAR { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CLEAR`"] +pub struct TASKS_CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CLEAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W { + TASKS_CLEAR_W { w: self } + } +} diff --git a/src/timer0/tasks_count.rs b/src/timer0/tasks_count.rs index 2fb7fe8..9cbcae9 100644 --- a/src/timer0/tasks_count.rs +++ b/src/timer0/tasks_count.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_COUNT { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_COUNT`"] +pub struct TASKS_COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_COUNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_count(&mut self) -> TASKS_COUNT_W { + TASKS_COUNT_W { w: self } + } +} diff --git a/src/timer0/tasks_shutdown.rs b/src/timer0/tasks_shutdown.rs index 024587a..51fe75d 100644 --- a/src/timer0/tasks_shutdown.rs +++ b/src/timer0/tasks_shutdown.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SHUTDOWN { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SHUTDOWN`"] +pub struct TASKS_SHUTDOWN_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SHUTDOWN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_shutdown(&mut self) -> TASKS_SHUTDOWN_W { + TASKS_SHUTDOWN_W { w: self } + } +} diff --git a/src/timer0/tasks_start.rs b/src/timer0/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/timer0/tasks_start.rs +++ b/src/timer0/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/timer0/tasks_stop.rs b/src/timer0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/timer0/tasks_stop.rs +++ b/src/timer0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/timer3/tasks_clear.rs b/src/timer3/tasks_clear.rs index c2b61e5..f452e06 100644 --- a/src/timer3/tasks_clear.rs +++ b/src/timer3/tasks_clear.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_CLEAR { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CLEAR`"] +pub struct TASKS_CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CLEAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W { + TASKS_CLEAR_W { w: self } + } +} diff --git a/src/timer3/tasks_count.rs b/src/timer3/tasks_count.rs index 2fb7fe8..9cbcae9 100644 --- a/src/timer3/tasks_count.rs +++ b/src/timer3/tasks_count.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_COUNT { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_COUNT`"] +pub struct TASKS_COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_COUNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_count(&mut self) -> TASKS_COUNT_W { + TASKS_COUNT_W { w: self } + } +} diff --git a/src/timer3/tasks_shutdown.rs b/src/timer3/tasks_shutdown.rs index 024587a..51fe75d 100644 --- a/src/timer3/tasks_shutdown.rs +++ b/src/timer3/tasks_shutdown.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SHUTDOWN { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SHUTDOWN`"] +pub struct TASKS_SHUTDOWN_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SHUTDOWN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_shutdown(&mut self) -> TASKS_SHUTDOWN_W { + TASKS_SHUTDOWN_W { w: self } + } +} diff --git a/src/timer3/tasks_start.rs b/src/timer3/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/timer3/tasks_start.rs +++ b/src/timer3/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} diff --git a/src/timer3/tasks_stop.rs b/src/timer3/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/timer3/tasks_stop.rs +++ b/src/timer3/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/twi0/events_bb.rs b/src/twi0/events_bb.rs index c2da574..5c99ea3 100644 --- a/src/twi0/events_bb.rs +++ b/src/twi0/events_bb.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_BB { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_BB`"] +pub type EVENTS_BB_R = crate::R; +#[doc = "Write proxy for field `EVENTS_BB`"] +pub struct EVENTS_BB_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_BB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_bb(&self) -> EVENTS_BB_R { + EVENTS_BB_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_bb(&mut self) -> EVENTS_BB_W { + EVENTS_BB_W { w: self } + } +} diff --git a/src/twi0/events_error.rs b/src/twi0/events_error.rs index 8bd6113..810699a 100644 --- a/src/twi0/events_error.rs +++ b/src/twi0/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/twi0/events_rxdready.rs b/src/twi0/events_rxdready.rs index d650460..ca3060d 100644 --- a/src/twi0/events_rxdready.rs +++ b/src/twi0/events_rxdready.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXDREADY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXDREADY`"] +pub type EVENTS_RXDREADY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXDREADY`"] +pub struct EVENTS_RXDREADY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXDREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxdready(&self) -> EVENTS_RXDREADY_R { + EVENTS_RXDREADY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxdready(&mut self) -> EVENTS_RXDREADY_W { + EVENTS_RXDREADY_W { w: self } + } +} diff --git a/src/twi0/events_stopped.rs b/src/twi0/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/twi0/events_stopped.rs +++ b/src/twi0/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/twi0/events_suspended.rs b/src/twi0/events_suspended.rs index f6f29e2..11d1f78 100644 --- a/src/twi0/events_suspended.rs +++ b/src/twi0/events_suspended.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_SUSPENDED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SUSPENDED`"] +pub type EVENTS_SUSPENDED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SUSPENDED`"] +pub struct EVENTS_SUSPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SUSPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_suspended(&self) -> EVENTS_SUSPENDED_R { + EVENTS_SUSPENDED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W { + EVENTS_SUSPENDED_W { w: self } + } +} diff --git a/src/twi0/events_txdsent.rs b/src/twi0/events_txdsent.rs index d80d56f..3867b17 100644 --- a/src/twi0/events_txdsent.rs +++ b/src/twi0/events_txdsent.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXDSENT { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXDSENT`"] +pub type EVENTS_TXDSENT_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXDSENT`"] +pub struct EVENTS_TXDSENT_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXDSENT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txdsent(&self) -> EVENTS_TXDSENT_R { + EVENTS_TXDSENT_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txdsent(&mut self) -> EVENTS_TXDSENT_W { + EVENTS_TXDSENT_W { w: self } + } +} diff --git a/src/twi0/tasks_resume.rs b/src/twi0/tasks_resume.rs index 1ce7bdb..4d908e0 100644 --- a/src/twi0/tasks_resume.rs +++ b/src/twi0/tasks_resume.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RESUME { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RESUME`"] +pub struct TASKS_RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W { + TASKS_RESUME_W { w: self } + } +} diff --git a/src/twi0/tasks_startrx.rs b/src/twi0/tasks_startrx.rs index 06cff49..6b1e442 100644 --- a/src/twi0/tasks_startrx.rs +++ b/src/twi0/tasks_startrx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTRX`"] +pub struct TASKS_STARTRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W { + TASKS_STARTRX_W { w: self } + } +} diff --git a/src/twi0/tasks_starttx.rs b/src/twi0/tasks_starttx.rs index 7db7b10..b48bc8c 100644 --- a/src/twi0/tasks_starttx.rs +++ b/src/twi0/tasks_starttx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTTX`"] +pub struct TASKS_STARTTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W { + TASKS_STARTTX_W { w: self } + } +} diff --git a/src/twi0/tasks_stop.rs b/src/twi0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/twi0/tasks_stop.rs +++ b/src/twi0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/twi0/tasks_suspend.rs b/src/twi0/tasks_suspend.rs index 6d6e95f..d0ac7a7 100644 --- a/src/twi0/tasks_suspend.rs +++ b/src/twi0/tasks_suspend.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SUSPEND { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SUSPEND`"] +pub struct TASKS_SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W { + TASKS_SUSPEND_W { w: self } + } +} diff --git a/src/twim0/events_error.rs b/src/twim0/events_error.rs index 8bd6113..810699a 100644 --- a/src/twim0/events_error.rs +++ b/src/twim0/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/twim0/events_lastrx.rs b/src/twim0/events_lastrx.rs index 019a7bc..f1daaef 100644 --- a/src/twim0/events_lastrx.rs +++ b/src/twim0/events_lastrx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_LASTRX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_LASTRX`"] +pub type EVENTS_LASTRX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_LASTRX`"] +pub struct EVENTS_LASTRX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_LASTRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_lastrx(&self) -> EVENTS_LASTRX_R { + EVENTS_LASTRX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_lastrx(&mut self) -> EVENTS_LASTRX_W { + EVENTS_LASTRX_W { w: self } + } +} diff --git a/src/twim0/events_lasttx.rs b/src/twim0/events_lasttx.rs index feaf120..b465185 100644 --- a/src/twim0/events_lasttx.rs +++ b/src/twim0/events_lasttx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_LASTTX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_LASTTX`"] +pub type EVENTS_LASTTX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_LASTTX`"] +pub struct EVENTS_LASTTX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_LASTTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_lasttx(&self) -> EVENTS_LASTTX_R { + EVENTS_LASTTX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_lasttx(&mut self) -> EVENTS_LASTTX_W { + EVENTS_LASTTX_W { w: self } + } +} diff --git a/src/twim0/events_rxstarted.rs b/src/twim0/events_rxstarted.rs index 7458dea..0d3c646 100644 --- a/src/twim0/events_rxstarted.rs +++ b/src/twim0/events_rxstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXSTARTED`"] +pub type EVENTS_RXSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXSTARTED`"] +pub struct EVENTS_RXSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxstarted(&self) -> EVENTS_RXSTARTED_R { + EVENTS_RXSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W { + EVENTS_RXSTARTED_W { w: self } + } +} diff --git a/src/twim0/events_stopped.rs b/src/twim0/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/twim0/events_stopped.rs +++ b/src/twim0/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/twim0/events_suspended.rs b/src/twim0/events_suspended.rs index f6f29e2..11d1f78 100644 --- a/src/twim0/events_suspended.rs +++ b/src/twim0/events_suspended.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_SUSPENDED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SUSPENDED`"] +pub type EVENTS_SUSPENDED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SUSPENDED`"] +pub struct EVENTS_SUSPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SUSPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_suspended(&self) -> EVENTS_SUSPENDED_R { + EVENTS_SUSPENDED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W { + EVENTS_SUSPENDED_W { w: self } + } +} diff --git a/src/twim0/events_txstarted.rs b/src/twim0/events_txstarted.rs index 0cc71c4..c58b54f 100644 --- a/src/twim0/events_txstarted.rs +++ b/src/twim0/events_txstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXSTARTED`"] +pub type EVENTS_TXSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXSTARTED`"] +pub struct EVENTS_TXSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstarted(&self) -> EVENTS_TXSTARTED_R { + EVENTS_TXSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W { + EVENTS_TXSTARTED_W { w: self } + } +} diff --git a/src/twim0/tasks_resume.rs b/src/twim0/tasks_resume.rs index 1ce7bdb..4d908e0 100644 --- a/src/twim0/tasks_resume.rs +++ b/src/twim0/tasks_resume.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RESUME { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RESUME`"] +pub struct TASKS_RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W { + TASKS_RESUME_W { w: self } + } +} diff --git a/src/twim0/tasks_startrx.rs b/src/twim0/tasks_startrx.rs index 06cff49..6b1e442 100644 --- a/src/twim0/tasks_startrx.rs +++ b/src/twim0/tasks_startrx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTRX`"] +pub struct TASKS_STARTRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W { + TASKS_STARTRX_W { w: self } + } +} diff --git a/src/twim0/tasks_starttx.rs b/src/twim0/tasks_starttx.rs index 7db7b10..b48bc8c 100644 --- a/src/twim0/tasks_starttx.rs +++ b/src/twim0/tasks_starttx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTTX`"] +pub struct TASKS_STARTTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W { + TASKS_STARTTX_W { w: self } + } +} diff --git a/src/twim0/tasks_stop.rs b/src/twim0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/twim0/tasks_stop.rs +++ b/src/twim0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/twim0/tasks_suspend.rs b/src/twim0/tasks_suspend.rs index 6d6e95f..d0ac7a7 100644 --- a/src/twim0/tasks_suspend.rs +++ b/src/twim0/tasks_suspend.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SUSPEND { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SUSPEND`"] +pub struct TASKS_SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W { + TASKS_SUSPEND_W { w: self } + } +} diff --git a/src/twis0/events_error.rs b/src/twis0/events_error.rs index 8bd6113..810699a 100644 --- a/src/twis0/events_error.rs +++ b/src/twis0/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/twis0/events_read.rs b/src/twis0/events_read.rs index 38f0f14..8b6254a 100644 --- a/src/twis0/events_read.rs +++ b/src/twis0/events_read.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_READ { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_READ`"] +pub type EVENTS_READ_R = crate::R; +#[doc = "Write proxy for field `EVENTS_READ`"] +pub struct EVENTS_READ_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_READ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_read(&self) -> EVENTS_READ_R { + EVENTS_READ_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_read(&mut self) -> EVENTS_READ_W { + EVENTS_READ_W { w: self } + } +} diff --git a/src/twis0/events_rxstarted.rs b/src/twis0/events_rxstarted.rs index 7458dea..0d3c646 100644 --- a/src/twis0/events_rxstarted.rs +++ b/src/twis0/events_rxstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXSTARTED`"] +pub type EVENTS_RXSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXSTARTED`"] +pub struct EVENTS_RXSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxstarted(&self) -> EVENTS_RXSTARTED_R { + EVENTS_RXSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W { + EVENTS_RXSTARTED_W { w: self } + } +} diff --git a/src/twis0/events_stopped.rs b/src/twis0/events_stopped.rs index 4794a84..2d83a06 100644 --- a/src/twis0/events_stopped.rs +++ b/src/twis0/events_stopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_STOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_STOPPED`"] +pub type EVENTS_STOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_STOPPED`"] +pub struct EVENTS_STOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_STOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&self) -> EVENTS_STOPPED_R { + EVENTS_STOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W { + EVENTS_STOPPED_W { w: self } + } +} diff --git a/src/twis0/events_txstarted.rs b/src/twis0/events_txstarted.rs index 0cc71c4..c58b54f 100644 --- a/src/twis0/events_txstarted.rs +++ b/src/twis0/events_txstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXSTARTED`"] +pub type EVENTS_TXSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXSTARTED`"] +pub struct EVENTS_TXSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstarted(&self) -> EVENTS_TXSTARTED_R { + EVENTS_TXSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W { + EVENTS_TXSTARTED_W { w: self } + } +} diff --git a/src/twis0/events_write.rs b/src/twis0/events_write.rs index b345fcb..bcc79d3 100644 --- a/src/twis0/events_write.rs +++ b/src/twis0/events_write.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_WRITE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_WRITE`"] +pub type EVENTS_WRITE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_WRITE`"] +pub struct EVENTS_WRITE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_WRITE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_write(&self) -> EVENTS_WRITE_R { + EVENTS_WRITE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_write(&mut self) -> EVENTS_WRITE_W { + EVENTS_WRITE_W { w: self } + } +} diff --git a/src/twis0/tasks_preparerx.rs b/src/twis0/tasks_preparerx.rs index 3a45fae..10bf54e 100644 --- a/src/twis0/tasks_preparerx.rs +++ b/src/twis0/tasks_preparerx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_PREPARERX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_PREPARERX`"] +pub struct TASKS_PREPARERX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_PREPARERX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_preparerx(&mut self) -> TASKS_PREPARERX_W { + TASKS_PREPARERX_W { w: self } + } +} diff --git a/src/twis0/tasks_preparetx.rs b/src/twis0/tasks_preparetx.rs index 4cd0d13..3a85c50 100644 --- a/src/twis0/tasks_preparetx.rs +++ b/src/twis0/tasks_preparetx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_PREPARETX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_PREPARETX`"] +pub struct TASKS_PREPARETX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_PREPARETX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_preparetx(&mut self) -> TASKS_PREPARETX_W { + TASKS_PREPARETX_W { w: self } + } +} diff --git a/src/twis0/tasks_resume.rs b/src/twis0/tasks_resume.rs index 1ce7bdb..4d908e0 100644 --- a/src/twis0/tasks_resume.rs +++ b/src/twis0/tasks_resume.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_RESUME { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_RESUME`"] +pub struct TASKS_RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_resume(&mut self) -> TASKS_RESUME_W { + TASKS_RESUME_W { w: self } + } +} diff --git a/src/twis0/tasks_stop.rs b/src/twis0/tasks_stop.rs index 01cd790..5ea6ca1 100644 --- a/src/twis0/tasks_stop.rs +++ b/src/twis0/tasks_stop.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOP { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOP`"] +pub struct TASKS_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stop(&mut self) -> TASKS_STOP_W { + TASKS_STOP_W { w: self } + } +} diff --git a/src/twis0/tasks_suspend.rs b/src/twis0/tasks_suspend.rs index 6d6e95f..d0ac7a7 100644 --- a/src/twis0/tasks_suspend.rs +++ b/src/twis0/tasks_suspend.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SUSPEND { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SUSPEND`"] +pub struct TASKS_SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W { + TASKS_SUSPEND_W { w: self } + } +} diff --git a/src/uart0/events_cts.rs b/src/uart0/events_cts.rs index 9fcbd04..56814fc 100644 --- a/src/uart0/events_cts.rs +++ b/src/uart0/events_cts.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CTS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CTS`"] +pub type EVENTS_CTS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CTS`"] +pub struct EVENTS_CTS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cts(&self) -> EVENTS_CTS_R { + EVENTS_CTS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cts(&mut self) -> EVENTS_CTS_W { + EVENTS_CTS_W { w: self } + } +} diff --git a/src/uart0/events_error.rs b/src/uart0/events_error.rs index 8bd6113..810699a 100644 --- a/src/uart0/events_error.rs +++ b/src/uart0/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/uart0/events_ncts.rs b/src/uart0/events_ncts.rs index a1105c4..ffd1cf5 100644 --- a/src/uart0/events_ncts.rs +++ b/src/uart0/events_ncts.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_NCTS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_NCTS`"] +pub type EVENTS_NCTS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_NCTS`"] +pub struct EVENTS_NCTS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_NCTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ncts(&self) -> EVENTS_NCTS_R { + EVENTS_NCTS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ncts(&mut self) -> EVENTS_NCTS_W { + EVENTS_NCTS_W { w: self } + } +} diff --git a/src/uart0/events_rxdrdy.rs b/src/uart0/events_rxdrdy.rs index f7be619..72d694e 100644 --- a/src/uart0/events_rxdrdy.rs +++ b/src/uart0/events_rxdrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXDRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXDRDY`"] +pub type EVENTS_RXDRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXDRDY`"] +pub struct EVENTS_RXDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxdrdy(&self) -> EVENTS_RXDRDY_R { + EVENTS_RXDRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W { + EVENTS_RXDRDY_W { w: self } + } +} diff --git a/src/uart0/events_rxto.rs b/src/uart0/events_rxto.rs index afc2059..cbb6c20 100644 --- a/src/uart0/events_rxto.rs +++ b/src/uart0/events_rxto.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXTO { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXTO`"] +pub type EVENTS_RXTO_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXTO`"] +pub struct EVENTS_RXTO_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxto(&self) -> EVENTS_RXTO_R { + EVENTS_RXTO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxto(&mut self) -> EVENTS_RXTO_W { + EVENTS_RXTO_W { w: self } + } +} diff --git a/src/uart0/events_txdrdy.rs b/src/uart0/events_txdrdy.rs index 044946c..f209b50 100644 --- a/src/uart0/events_txdrdy.rs +++ b/src/uart0/events_txdrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXDRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXDRDY`"] +pub type EVENTS_TXDRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXDRDY`"] +pub struct EVENTS_TXDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txdrdy(&self) -> EVENTS_TXDRDY_R { + EVENTS_TXDRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W { + EVENTS_TXDRDY_W { w: self } + } +} diff --git a/src/uart0/tasks_startrx.rs b/src/uart0/tasks_startrx.rs index 06cff49..6b1e442 100644 --- a/src/uart0/tasks_startrx.rs +++ b/src/uart0/tasks_startrx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTRX`"] +pub struct TASKS_STARTRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W { + TASKS_STARTRX_W { w: self } + } +} diff --git a/src/uart0/tasks_starttx.rs b/src/uart0/tasks_starttx.rs index 7db7b10..b48bc8c 100644 --- a/src/uart0/tasks_starttx.rs +++ b/src/uart0/tasks_starttx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTTX`"] +pub struct TASKS_STARTTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W { + TASKS_STARTTX_W { w: self } + } +} diff --git a/src/uart0/tasks_stoprx.rs b/src/uart0/tasks_stoprx.rs index 90f1618..0f6c773 100644 --- a/src/uart0/tasks_stoprx.rs +++ b/src/uart0/tasks_stoprx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOPRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOPRX`"] +pub struct TASKS_STOPRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOPRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W { + TASKS_STOPRX_W { w: self } + } +} diff --git a/src/uart0/tasks_stoptx.rs b/src/uart0/tasks_stoptx.rs index ea527ff..06e33bb 100644 --- a/src/uart0/tasks_stoptx.rs +++ b/src/uart0/tasks_stoptx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOPTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOPTX`"] +pub struct TASKS_STOPTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOPTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W { + TASKS_STOPTX_W { w: self } + } +} diff --git a/src/uart0/tasks_suspend.rs b/src/uart0/tasks_suspend.rs index 6d6e95f..d0ac7a7 100644 --- a/src/uart0/tasks_suspend.rs +++ b/src/uart0/tasks_suspend.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_SUSPEND { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SUSPEND`"] +pub struct TASKS_SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W { + TASKS_SUSPEND_W { w: self } + } +} diff --git a/src/uarte0/events_cts.rs b/src/uarte0/events_cts.rs index 9fcbd04..56814fc 100644 --- a/src/uarte0/events_cts.rs +++ b/src/uarte0/events_cts.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_CTS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_CTS`"] +pub type EVENTS_CTS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_CTS`"] +pub struct EVENTS_CTS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cts(&self) -> EVENTS_CTS_R { + EVENTS_CTS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_cts(&mut self) -> EVENTS_CTS_W { + EVENTS_CTS_W { w: self } + } +} diff --git a/src/uarte0/events_endrx.rs b/src/uarte0/events_endrx.rs index 81b6d83..53f61a6 100644 --- a/src/uarte0/events_endrx.rs +++ b/src/uarte0/events_endrx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDRX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDRX`"] +pub type EVENTS_ENDRX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDRX`"] +pub struct EVENTS_ENDRX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&self) -> EVENTS_ENDRX_R { + EVENTS_ENDRX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W { + EVENTS_ENDRX_W { w: self } + } +} diff --git a/src/uarte0/events_endtx.rs b/src/uarte0/events_endtx.rs index 8207be1..0547b10 100644 --- a/src/uarte0/events_endtx.rs +++ b/src/uarte0/events_endtx.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ENDTX { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ENDTX`"] +pub type EVENTS_ENDTX_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ENDTX`"] +pub struct EVENTS_ENDTX_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ENDTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endtx(&self) -> EVENTS_ENDTX_R { + EVENTS_ENDTX_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W { + EVENTS_ENDTX_W { w: self } + } +} diff --git a/src/uarte0/events_error.rs b/src/uarte0/events_error.rs index 8bd6113..810699a 100644 --- a/src/uarte0/events_error.rs +++ b/src/uarte0/events_error.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_ERROR { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_ERROR`"] +pub type EVENTS_ERROR_R = crate::R; +#[doc = "Write proxy for field `EVENTS_ERROR`"] +pub struct EVENTS_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&self) -> EVENTS_ERROR_R { + EVENTS_ERROR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_error(&mut self) -> EVENTS_ERROR_W { + EVENTS_ERROR_W { w: self } + } +} diff --git a/src/uarte0/events_ncts.rs b/src/uarte0/events_ncts.rs index a1105c4..ffd1cf5 100644 --- a/src/uarte0/events_ncts.rs +++ b/src/uarte0/events_ncts.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_NCTS { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_NCTS`"] +pub type EVENTS_NCTS_R = crate::R; +#[doc = "Write proxy for field `EVENTS_NCTS`"] +pub struct EVENTS_NCTS_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_NCTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ncts(&self) -> EVENTS_NCTS_R { + EVENTS_NCTS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_ncts(&mut self) -> EVENTS_NCTS_W { + EVENTS_NCTS_W { w: self } + } +} diff --git a/src/uarte0/events_rxdrdy.rs b/src/uarte0/events_rxdrdy.rs index f7be619..72d694e 100644 --- a/src/uarte0/events_rxdrdy.rs +++ b/src/uarte0/events_rxdrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXDRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXDRDY`"] +pub type EVENTS_RXDRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXDRDY`"] +pub struct EVENTS_RXDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxdrdy(&self) -> EVENTS_RXDRDY_R { + EVENTS_RXDRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W { + EVENTS_RXDRDY_W { w: self } + } +} diff --git a/src/uarte0/events_rxstarted.rs b/src/uarte0/events_rxstarted.rs index 7458dea..0d3c646 100644 --- a/src/uarte0/events_rxstarted.rs +++ b/src/uarte0/events_rxstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXSTARTED`"] +pub type EVENTS_RXSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXSTARTED`"] +pub struct EVENTS_RXSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxstarted(&self) -> EVENTS_RXSTARTED_R { + EVENTS_RXSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W { + EVENTS_RXSTARTED_W { w: self } + } +} diff --git a/src/uarte0/events_rxto.rs b/src/uarte0/events_rxto.rs index afc2059..cbb6c20 100644 --- a/src/uarte0/events_rxto.rs +++ b/src/uarte0/events_rxto.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_RXTO { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_RXTO`"] +pub type EVENTS_RXTO_R = crate::R; +#[doc = "Write proxy for field `EVENTS_RXTO`"] +pub struct EVENTS_RXTO_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_RXTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxto(&self) -> EVENTS_RXTO_R { + EVENTS_RXTO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_rxto(&mut self) -> EVENTS_RXTO_W { + EVENTS_RXTO_W { w: self } + } +} diff --git a/src/uarte0/events_txdrdy.rs b/src/uarte0/events_txdrdy.rs index 044946c..f209b50 100644 --- a/src/uarte0/events_txdrdy.rs +++ b/src/uarte0/events_txdrdy.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXDRDY { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXDRDY`"] +pub type EVENTS_TXDRDY_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXDRDY`"] +pub struct EVENTS_TXDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txdrdy(&self) -> EVENTS_TXDRDY_R { + EVENTS_TXDRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W { + EVENTS_TXDRDY_W { w: self } + } +} diff --git a/src/uarte0/events_txstarted.rs b/src/uarte0/events_txstarted.rs index 0cc71c4..c58b54f 100644 --- a/src/uarte0/events_txstarted.rs +++ b/src/uarte0/events_txstarted.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXSTARTED`"] +pub type EVENTS_TXSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXSTARTED`"] +pub struct EVENTS_TXSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstarted(&self) -> EVENTS_TXSTARTED_R { + EVENTS_TXSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W { + EVENTS_TXSTARTED_W { w: self } + } +} diff --git a/src/uarte0/events_txstopped.rs b/src/uarte0/events_txstopped.rs index e859805..66d7283 100644 --- a/src/uarte0/events_txstopped.rs +++ b/src/uarte0/events_txstopped.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TXSTOPPED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TXSTOPPED`"] +pub type EVENTS_TXSTOPPED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TXSTOPPED`"] +pub struct EVENTS_TXSTOPPED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TXSTOPPED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstopped(&self) -> EVENTS_TXSTOPPED_R { + EVENTS_TXSTOPPED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_txstopped(&mut self) -> EVENTS_TXSTOPPED_W { + EVENTS_TXSTOPPED_W { w: self } + } +} diff --git a/src/uarte0/tasks_flushrx.rs b/src/uarte0/tasks_flushrx.rs index 5258434..ba5e468 100644 --- a/src/uarte0/tasks_flushrx.rs +++ b/src/uarte0/tasks_flushrx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_FLUSHRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_FLUSHRX`"] +pub struct TASKS_FLUSHRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_FLUSHRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_flushrx(&mut self) -> TASKS_FLUSHRX_W { + TASKS_FLUSHRX_W { w: self } + } +} diff --git a/src/uarte0/tasks_startrx.rs b/src/uarte0/tasks_startrx.rs index 06cff49..6b1e442 100644 --- a/src/uarte0/tasks_startrx.rs +++ b/src/uarte0/tasks_startrx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTRX`"] +pub struct TASKS_STARTRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W { + TASKS_STARTRX_W { w: self } + } +} diff --git a/src/uarte0/tasks_starttx.rs b/src/uarte0/tasks_starttx.rs index 7db7b10..b48bc8c 100644 --- a/src/uarte0/tasks_starttx.rs +++ b/src/uarte0/tasks_starttx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STARTTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STARTTX`"] +pub struct TASKS_STARTTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STARTTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W { + TASKS_STARTTX_W { w: self } + } +} diff --git a/src/uarte0/tasks_stoprx.rs b/src/uarte0/tasks_stoprx.rs index 90f1618..0f6c773 100644 --- a/src/uarte0/tasks_stoprx.rs +++ b/src/uarte0/tasks_stoprx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOPRX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOPRX`"] +pub struct TASKS_STOPRX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOPRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W { + TASKS_STOPRX_W { w: self } + } +} diff --git a/src/uarte0/tasks_stoptx.rs b/src/uarte0/tasks_stoptx.rs index ea527ff..06e33bb 100644 --- a/src/uarte0/tasks_stoptx.rs +++ b/src/uarte0/tasks_stoptx.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_STOPTX { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_STOPTX`"] +pub struct TASKS_STOPTX_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_STOPTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W { + TASKS_STOPTX_W { w: self } + } +} diff --git a/src/wdt/events_timeout.rs b/src/wdt/events_timeout.rs index 936db5d..898b942 100644 --- a/src/wdt/events_timeout.rs +++ b/src/wdt/events_timeout.rs @@ -10,5 +10,41 @@ impl crate::ResetValue for super::EVENTS_TIMEOUT { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TIMEOUT`"] +pub type EVENTS_TIMEOUT_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TIMEOUT`"] +pub struct EVENTS_TIMEOUT_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TIMEOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_timeout(&self) -> EVENTS_TIMEOUT_R { + EVENTS_TIMEOUT_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_timeout(&mut self) -> EVENTS_TIMEOUT_W { + EVENTS_TIMEOUT_W { w: self } + } +} diff --git a/src/wdt/tasks_start.rs b/src/wdt/tasks_start.rs index 1bff5b5..31df6cc 100644 --- a/src/wdt/tasks_start.rs +++ b/src/wdt/tasks_start.rs @@ -8,4 +8,32 @@ impl crate::ResetValue for super::TASKS_START { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_START`"] +pub struct TASKS_START_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_start(&mut self) -> TASKS_START_W { + TASKS_START_W { w: self } + } +} From 114d1b9540871856ab3391479fbcdf7345d6340b Mon Sep 17 00:00:00 2001 From: dskleingeld <11743287+dskleingeld@users.noreply.github.com> Date: Fri, 23 Apr 2021 16:57:30 +0200 Subject: [PATCH 6/6] fixes EVENTS followed by [%s] being ignored --- fix_svd.py | 75 +++++++++++++++++++-------- nrf52832_fixed.svd | 98 +++++++++++++++++++++++++++++++++++ src/egu0/events_triggered.rs | 40 +++++++++++++- src/egu0/tasks_trigger.rs | 30 ++++++++++- src/gpiote/events_in.rs | 40 +++++++++++++- src/gpiote/tasks_clr.rs | 30 ++++++++++- src/gpiote/tasks_out.rs | 30 ++++++++++- src/gpiote/tasks_set.rs | 30 ++++++++++- src/pwm0/events_seqend.rs | 40 +++++++++++++- src/pwm0/events_seqstarted.rs | 40 +++++++++++++- src/pwm0/tasks_seqstart.rs | 30 ++++++++++- src/rtc0/events_compare.rs | 40 +++++++++++++- src/timer0/events_compare.rs | 40 +++++++++++++- src/timer0/tasks_capture.rs | 30 ++++++++++- src/timer3/events_compare.rs | 40 +++++++++++++- src/timer3/tasks_capture.rs | 30 ++++++++++- 16 files changed, 619 insertions(+), 44 deletions(-) diff --git a/fix_svd.py b/fix_svd.py index 8e677c7..1e5b2e5 100644 --- a/fix_svd.py +++ b/fix_svd.py @@ -6,7 +6,11 @@ lsb_re = re.compile(r"^\s+(\d)\s+$") msb_re = re.compile(r"^\s+(\d)\s+$") -name_re = re.compile(r"^\s+(\w+)\s+$") +name_re = re.compile(r"^\s+([\w|\[%\]]+)\s+$") + + +def indent(line: str) -> int: + return len(line) - len(line.lstrip(" ")) @dataclass @@ -28,51 +32,74 @@ def from_lines(lines: List[str]): @dataclass class Register: name: str + field_name: str reg_range: Tuple[int, int] field: Optional[TaskField] @staticmethod - def from_lines(i: int, lines: List[str]): + def from_lines(reg_pos: int, name_pos: int, lines: List[str]): # extract register name - name_match = name_re.match(lines[i]) + name_match = name_re.match(lines[name_pos]) if name_match is None: - raise ValueError(f"register at line {i} has no name") - name = name_match.group(1) + raise ValueError(f"register at line {reg_pos} has no name") + reg_name = name_match.group(1) + if reg_name is None: + raise ValueError(f"register at line {reg_pos} has no name") # find end of register reg_range = None - for j, line in enumerate(lines[i:]): + for j, line in enumerate(lines[reg_pos:]): if "" in line: - reg_range = (i, i+j+1) + reg_range = (reg_pos, reg_pos+j+1) break if reg_range is None: - raise ValueError(f"register at line {i} has no end") + raise ValueError(f"register at line {reg_pos} has no end") # has field? + field_name = reg_name + if reg_name.endswith("[%s]"): # field name is then without "[%s]" + field_name = reg_name[:-len("[%s]")] + field = None lines = lines[reg_range[0]:reg_range[1]] for j, line in enumerate(lines): if "" not in line: continue - if ""+name not in lines[j+1]: + if ""+field_name not in lines[j+1]: continue field = TaskField.from_lines(lines[j:]) break - return Register(name, reg_range, field) + + return Register(reg_name, field_name, reg_range, field) + + +def register_start(lines: List[str], name_pos: int) -> Optional[int]: + name_indent = indent(lines[name_pos]) + lines = lines[max(name_pos-10, 0):name_pos] + for j, line in enumerate(reversed(lines)): + if indent(line) == name_indent: + continue + if "" in line: + return name_pos - j - 1 + break + + return None def extract_registers(name_prompt: str, lines: List[str]) -> List[Register]: tasks = [] for i, line in enumerate(lines): - # if "TASKS_" not in line: if name_prompt not in line: continue - if "" not in lines[i-1]: + + name_pos = i + reg_pos = register_start(lines, name_pos) + if reg_pos is None: continue - task = Register.from_lines(i, lines) + task = Register.from_lines(reg_pos, name_pos, lines) tasks.append(task) return tasks @@ -84,25 +111,28 @@ def check_assumptions(name_prompt: str): """ file = open("nrf52840.svd", "r") lines = file.readlines() + # lines = lines[4873:4888] + # lines = lines[40832:40846] + tasks = extract_registers(name_prompt, lines) for task in tasks: if task.field is None: - print("some registers have no field") + print(f"register {task.name} at {task.reg_range[0]} have no field") continue if task.field.lsb != 0: - print("not all registers have lsb = 0") + print(f"register {task.name} at {task.reg_range[0]} has lsb != 0") if task.field.msb != 0: - print("not all registers have msb = 0") + print(f"register {task.name} at {task.reg_range[0]} has msb != 0") -def to_insert(taskname: str, num_spaces: int) -> List[str]: +def to_insert(field_name: str, num_spaces: int) -> List[str]: indent = "".ljust(num_spaces) return ([ indent + " \n", indent + " \n", - indent + f" {taskname}\n", + indent + f" {field_name}\n", indent + " 0\n", indent + " 0\n", indent + " \n", @@ -122,11 +152,10 @@ def to_insert(taskname: str, num_spaces: int) -> List[str]: registers = sorted(registers, key=lambda r: r.reg_range[0]) # this assumes the fields key is not present - for task in reversed(registers): - pos = task.reg_range[1] - 1 - reg_line = lines[task.reg_range[1]] - indent = len(reg_line) - len(reg_line.lstrip(" ")) - lines[pos:pos] = to_insert(task.name, indent) + for reg in reversed(registers): + pos = reg.reg_range[1] - 1 + reg_line = lines[reg.reg_range[1]] + lines[pos:pos] = to_insert(reg.field_name, indent(reg_line)) file = open("nrf52832_fixed.svd", "w") file.writelines(lines) diff --git a/nrf52832_fixed.svd b/nrf52832_fixed.svd index 0457d58..29b8953 100644 --- a/nrf52832_fixed.svd +++ b/nrf52832_fixed.svd @@ -16885,6 +16885,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. 0x000 write-only + + + TASKS_OUT + 0 + 0 + + 8 @@ -16893,6 +16900,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. 0x030 write-only + + + TASKS_SET + 0 + 0 + + 8 @@ -16901,6 +16915,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. 0x060 write-only + + + TASKS_CLR + 0 + 0 + + 8 @@ -16909,6 +16930,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL 0x100 read-write + + + EVENTS_IN + 0 + 0 + + EVENTS_PORT @@ -19972,6 +20000,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Capture Timer value to CC[0] register 0x040 write-only + + + TASKS_CAPTURE + 0 + 0 + + 4 @@ -19980,6 +20015,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Compare event on CC[0] match 0x140 read-write + + + EVENTS_COMPARE + 0 + 0 + + SHORTS @@ -20589,6 +20631,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Compare event on CC[0] match 0x140 read-write + + + EVENTS_COMPARE + 0 + 0 + + INTENSET @@ -26206,6 +26255,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event 0x000 write-only + + + TASKS_TRIGGER + 0 + 0 + + 16 @@ -26214,6 +26270,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task 0x100 read-write + + + EVENTS_TRIGGERED + 0 + 0 + + INTEN @@ -27591,6 +27654,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Capture Timer value to CC[0] register 0x040 write-only + + + TASKS_CAPTURE + 0 + 0 + + 6 @@ -27599,6 +27669,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Compare event on CC[0] match 0x140 read-write + + + EVENTS_COMPARE + 0 + 0 + + SHORTS @@ -28312,6 +28389,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. 0x008 write-only + + + TASKS_SEQSTART + 0 + 0 + + TASKS_NEXTSTEP @@ -28346,6 +28430,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: First PWM period started on sequence 0 0x108 read-write + + + EVENTS_SEQSTARTED + 0 + 0 + + 2 @@ -28354,6 +28445,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter 0x110 read-write + + + EVENTS_SEQEND + 0 + 0 + + EVENTS_PWMPERIODEND diff --git a/src/egu0/events_triggered.rs b/src/egu0/events_triggered.rs index 81cd386..de70c26 100644 --- a/src/egu0/events_triggered.rs +++ b/src/egu0/events_triggered.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_TRIGGERED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_TRIGGERED`"] +pub type EVENTS_TRIGGERED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_TRIGGERED`"] +pub struct EVENTS_TRIGGERED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_TRIGGERED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_triggered(&self) -> EVENTS_TRIGGERED_R { + EVENTS_TRIGGERED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W { + EVENTS_TRIGGERED_W { w: self } + } +} diff --git a/src/egu0/tasks_trigger.rs b/src/egu0/tasks_trigger.rs index 8f03986..d30ec18 100644 --- a/src/egu0/tasks_trigger.rs +++ b/src/egu0/tasks_trigger.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_TRIGGER { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_TRIGGER`"] +pub struct TASKS_TRIGGER_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_TRIGGER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W { + TASKS_TRIGGER_W { w: self } + } +} diff --git a/src/gpiote/events_in.rs b/src/gpiote/events_in.rs index ae7639f..683d860 100644 --- a/src/gpiote/events_in.rs +++ b/src/gpiote/events_in.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_IN { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_IN`"] +pub type EVENTS_IN_R = crate::R; +#[doc = "Write proxy for field `EVENTS_IN`"] +pub struct EVENTS_IN_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_in(&self) -> EVENTS_IN_R { + EVENTS_IN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_in(&mut self) -> EVENTS_IN_W { + EVENTS_IN_W { w: self } + } +} diff --git a/src/gpiote/tasks_clr.rs b/src/gpiote/tasks_clr.rs index f565fcb..60b175e 100644 --- a/src/gpiote/tasks_clr.rs +++ b/src/gpiote/tasks_clr.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_CLR { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CLR`"] +pub struct TASKS_CLR_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_clr(&mut self) -> TASKS_CLR_W { + TASKS_CLR_W { w: self } + } +} diff --git a/src/gpiote/tasks_out.rs b/src/gpiote/tasks_out.rs index 475feb3..151cfba 100644 --- a/src/gpiote/tasks_out.rs +++ b/src/gpiote/tasks_out.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_OUT { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_OUT`"] +pub struct TASKS_OUT_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_OUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_out(&mut self) -> TASKS_OUT_W { + TASKS_OUT_W { w: self } + } +} diff --git a/src/gpiote/tasks_set.rs b/src/gpiote/tasks_set.rs index 348dc82..4a9baad 100644 --- a/src/gpiote/tasks_set.rs +++ b/src/gpiote/tasks_set.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_SET { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SET`"] +pub struct TASKS_SET_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_set(&mut self) -> TASKS_SET_W { + TASKS_SET_W { w: self } + } +} diff --git a/src/pwm0/events_seqend.rs b/src/pwm0/events_seqend.rs index b728454..c3fd432 100644 --- a/src/pwm0/events_seqend.rs +++ b/src/pwm0/events_seqend.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_SEQEND { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SEQEND`"] +pub type EVENTS_SEQEND_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SEQEND`"] +pub struct EVENTS_SEQEND_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SEQEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_seqend(&self) -> EVENTS_SEQEND_R { + EVENTS_SEQEND_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_seqend(&mut self) -> EVENTS_SEQEND_W { + EVENTS_SEQEND_W { w: self } + } +} diff --git a/src/pwm0/events_seqstarted.rs b/src/pwm0/events_seqstarted.rs index 102601f..b61805c 100644 --- a/src/pwm0/events_seqstarted.rs +++ b/src/pwm0/events_seqstarted.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_SEQSTARTED { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_SEQSTARTED`"] +pub type EVENTS_SEQSTARTED_R = crate::R; +#[doc = "Write proxy for field `EVENTS_SEQSTARTED`"] +pub struct EVENTS_SEQSTARTED_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_SEQSTARTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_seqstarted(&self) -> EVENTS_SEQSTARTED_R { + EVENTS_SEQSTARTED_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_seqstarted(&mut self) -> EVENTS_SEQSTARTED_W { + EVENTS_SEQSTARTED_W { w: self } + } +} diff --git a/src/pwm0/tasks_seqstart.rs b/src/pwm0/tasks_seqstart.rs index 1a0c00b..805850f 100644 --- a/src/pwm0/tasks_seqstart.rs +++ b/src/pwm0/tasks_seqstart.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_SEQSTART { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_SEQSTART`"] +pub struct TASKS_SEQSTART_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_SEQSTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_seqstart(&mut self) -> TASKS_SEQSTART_W { + TASKS_SEQSTART_W { w: self } + } +} diff --git a/src/rtc0/events_compare.rs b/src/rtc0/events_compare.rs index 2dfd8b1..b59db01 100644 --- a/src/rtc0/events_compare.rs +++ b/src/rtc0/events_compare.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_COMPARE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_COMPARE`"] +pub type EVENTS_COMPARE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_COMPARE`"] +pub struct EVENTS_COMPARE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_COMPARE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_compare(&self) -> EVENTS_COMPARE_R { + EVENTS_COMPARE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_compare(&mut self) -> EVENTS_COMPARE_W { + EVENTS_COMPARE_W { w: self } + } +} diff --git a/src/timer0/events_compare.rs b/src/timer0/events_compare.rs index 2dfd8b1..b59db01 100644 --- a/src/timer0/events_compare.rs +++ b/src/timer0/events_compare.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_COMPARE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_COMPARE`"] +pub type EVENTS_COMPARE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_COMPARE`"] +pub struct EVENTS_COMPARE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_COMPARE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_compare(&self) -> EVENTS_COMPARE_R { + EVENTS_COMPARE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_compare(&mut self) -> EVENTS_COMPARE_W { + EVENTS_COMPARE_W { w: self } + } +} diff --git a/src/timer0/tasks_capture.rs b/src/timer0/tasks_capture.rs index a48b3bb..7a00885 100644 --- a/src/timer0/tasks_capture.rs +++ b/src/timer0/tasks_capture.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_CAPTURE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CAPTURE`"] +pub struct TASKS_CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CAPTURE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_capture(&mut self) -> TASKS_CAPTURE_W { + TASKS_CAPTURE_W { w: self } + } +} diff --git a/src/timer3/events_compare.rs b/src/timer3/events_compare.rs index 2dfd8b1..b59db01 100644 --- a/src/timer3/events_compare.rs +++ b/src/timer3/events_compare.rs @@ -11,5 +11,41 @@ impl crate::ResetValue for super::EVENTS_COMPARE { 0 } } -impl R {} -impl W {} +#[doc = "Reader of field `EVENTS_COMPARE`"] +pub type EVENTS_COMPARE_R = crate::R; +#[doc = "Write proxy for field `EVENTS_COMPARE`"] +pub struct EVENTS_COMPARE_W<'a> { + w: &'a mut W, +} +impl<'a> EVENTS_COMPARE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_compare(&self) -> EVENTS_COMPARE_R { + EVENTS_COMPARE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn events_compare(&mut self) -> EVENTS_COMPARE_W { + EVENTS_COMPARE_W { w: self } + } +} diff --git a/src/timer3/tasks_capture.rs b/src/timer3/tasks_capture.rs index a48b3bb..7a00885 100644 --- a/src/timer3/tasks_capture.rs +++ b/src/timer3/tasks_capture.rs @@ -9,4 +9,32 @@ impl crate::ResetValue for super::TASKS_CAPTURE { 0 } } -impl W {} +#[doc = "Write proxy for field `TASKS_CAPTURE`"] +pub struct TASKS_CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> TASKS_CAPTURE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + pub fn tasks_capture(&mut self) -> TASKS_CAPTURE_W { + TASKS_CAPTURE_W { w: self } + } +}