From cb60496545b72b01d56fbb25d0f2d77a4e647bb1 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 7 Aug 2023 10:09:41 -0400 Subject: [PATCH 01/23] Adding Ara RTL to FPGA Protosyn flow --- piton/tools/src/proto/common/rtl_setup.tcl | 142 ++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 7bcf1d82d..ab99f7f41 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,8 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include" + # RTL include files set GLOBAL_INCLUDE_FILES [list \ @@ -541,6 +542,144 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axilite.sv " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/strb2mask.v" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/axilite_noc_bridge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axi.sv " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/axi_noc_bridge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ara_verilog_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/accel_dispatcher_ideal.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_dispatcher.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_sequencer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_soc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_system.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_inval_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_to_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ctrl_registers.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/cva6_accel_first_pass_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/fixed_p_rounding.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queues_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_alu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/valu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vmfpu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/lane_sequencer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_div.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_fus_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/lane.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_requester.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_mul.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/masku/masku.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/addrgen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vldu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vlsu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vstu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_detect.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/fifo_v3.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator_tx.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_omega_net.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/delta_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_to_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/clock_divider_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/fifo_v2.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/prioarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/pulp_sync.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/rrarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/clock_divider.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_fifo.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/fifo_v1.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/find_first_one.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/pulp_sync_wedge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_fifo_adv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/isochronous_spill_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sub_per_hash.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fifo.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/fall_through_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/exp_backoff.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rstgen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_decode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lzc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_fifo_gray.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/id_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cb_filter_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/serial_deglitch.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_arbiter_flushable.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/onehot_to_bin.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/clk_div.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fork.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_delay.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rr_arb_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/max_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_arbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/addr_decode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator_rx.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/binary_to_gray.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/spill_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cb_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/spill_register_flushable.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_fifo_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_encode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/plru_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/shift_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr_16bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fork_dynamic.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/unread.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/popcount.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sync.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rstgen_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sync_wedge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/gray_to_binary.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/mv_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_to_axi.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_src.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_modify_address.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_downsizer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_err_slv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_to_axi_lite.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_serializer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_converter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cut.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_upsizer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_atop_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_burst_splitter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_delayer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_regs.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_to_apb.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_isolate.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_multicut.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_sim_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_id_prepend.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mailbox.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_dst.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mux.sv" \ ] set CHIP_INCLUDE_FILES [list \ @@ -655,6 +794,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ From b466c8347caa217e2e473920c2a2b86f517134a7 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 7 Aug 2023 10:12:10 -0400 Subject: [PATCH 02/23] Adding Alveo U280 board to FPGA Protosyn flow --- piton/design/chipset/mc/rtl/u280_polara_top.v | 247 ++++++++++++ .../chipset/xilinx/alveou280/.gitignore | 2 + piton/design/xilinx/alveou280/constraints.xdc | 269 +++++++++++++ piton/design/xilinx/alveou280/devices.xml | 57 +++ .../xilinx/alveou280/devices_ariane.xml | 77 ++++ piton/tools/src/proto/alveou280/board.tcl | 45 +++ piton/tools/src/proto/alveou280/polara.tcl | 364 ++++++++++++++++++ piton/tools/src/proto/block.list | 2 +- piton/tools/src/proto/board.list | 1 + piton/tools/src/proto/protosyn,2.5 | 18 +- 10 files changed, 1079 insertions(+), 3 deletions(-) create mode 100644 piton/design/chipset/mc/rtl/u280_polara_top.v create mode 100644 piton/design/chipset/xilinx/alveou280/.gitignore create mode 100644 piton/design/xilinx/alveou280/constraints.xdc create mode 100644 piton/design/xilinx/alveou280/devices.xml create mode 100644 piton/design/xilinx/alveou280/devices_ariane.xml create mode 100644 piton/tools/src/proto/alveou280/board.tcl create mode 100644 piton/tools/src/proto/alveou280/polara.tcl diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v new file mode 100644 index 000000000..f0dc03286 --- /dev/null +++ b/piton/design/chipset/mc/rtl/u280_polara_top.v @@ -0,0 +1,247 @@ + +`include "mc_define.h" + +module u280_polara_top ( + + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + + output c0_ddr4_act_n, + output [16:0] c0_ddr4_adr, + output [1:0] c0_ddr4_ba, + output [1:0] c0_ddr4_bg, + output [0:0] c0_ddr4_ck_c, + output [0:0] c0_ddr4_ck_t, + output [0:0] c0_ddr4_cke, + output [0:0] c0_ddr4_cs_n, + inout [71:0] c0_ddr4_dq, + inout [17:0] c0_ddr4_dqs_c, + inout [17:0] c0_ddr4_dqs_t, + output [0:0] c0_ddr4_odt, + output c0_ddr4_par, + output c0_ddr4_reset_n, + output c0_ddr4_ui_clk_sync_rst, + // Reference clock + input c0_sysclk_clk_n, + input c0_sysclk_clk_p, + // input mc_clk , + // input mc_rstn , + output chip_rstn , + input chipset_clk , + output chipset_rstn , + output c0_init_calib_complete, + + input [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input mem_flit_in_val , + output mem_flit_in_rdy , + + output [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output mem_flit_out_val , + input mem_flit_out_rdy +); + + + wire trans_fifo_val; + wire [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + wire trans_fifo_rdy; + + wire fifo_trans_val; + wire [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + wire fifo_trans_rdy; + + + noc_bidir_afifo mig_afifo ( + .clk_1 ( chipset_clk ), + .rst_1 ( ~chipset_rstn ), + + .clk_2 ( mc_clk ), + .rst_2 ( mc_rst ), + + // CPU --> MIG + .flit_in_val_1 ( mem_flit_in_val ), + .flit_in_data_1 ( mem_flit_in_data ), + .flit_in_rdy_1 ( mem_flit_in_rdy ), + + .flit_out_val_2 ( fifo_trans_val ), + .flit_out_data_2 ( fifo_trans_data ), + .flit_out_rdy_2 ( fifo_trans_rdy ), + + // MIG --> CPU + .flit_in_val_2 ( trans_fifo_val ), + .flit_in_data_2 ( trans_fifo_data ), + .flit_in_rdy_2 ( trans_fifo_rdy ), + + .flit_out_val_1 ( mem_flit_out_val ), + .flit_out_data_1 ( mem_flit_out_data ), + .flit_out_rdy_1 ( mem_flit_out_rdy ) + ); + + + noc_axi4_bridge noc_axi4_bridge ( + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( init_calib_complete ), + + .src_bridge_vr_noc2_val ( fifo_trans_val ), + .src_bridge_vr_noc2_dat ( fifo_trans_data ), + .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), + + .bridge_dst_vr_noc3_val ( trans_fifo_val ), + .bridge_dst_vr_noc3_dat ( trans_fifo_data ), + .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + + .m_axi_wid ( m_axi_wid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_buser ( m_axi_buser ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + + .m_axi_rid ( m_axi_rid), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + + ); + + polara polara_i ( + + .c0_sysclk_clk_p ( c0_sysclk_clk_p ), + .c0_sysclk_clk_n ( c0_sysclk_clk_n ), + .c0_ddr4_ui_clk ( mc_clk ), + .c0_ddr4_ui_clk_sync_rst ( mc_rst ), + .c0_init_calib_complete ( init_calib_complete ), + + + // DDR4 physicall interface + .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_par ( c0_ddr4_par ), // output wire c0_ddr4_parity + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + + // DDR4 control interface, not used, grounded + .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_awvalid + .c0_ddr4_s_axi_ctrl_awready( ), // output wire c0_ddr4_s_axi_ctrl_awready + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output wire c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output wire c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_arvalid + .c0_ddr4_s_axi_ctrl_arready( ), // output wire c0_ddr4_s_axi_ctrl_arready + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output wire c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output wire [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_rresp + + .chip_rstn ( chip_rstn ), + + // AXI4 Memory Interface + .c0_ddr4_s_axi_awid ( m_axi_awid), // input wire [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input wire [34 : 0] c0_ddr4_s_axi_awaddr + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input wire [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input wire [2 : 0] c0_ddr4_s_axi_awsize + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input wire [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input wire [0 : 0] c0_ddr4_s_axi_awlock + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input wire [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input wire [2 : 0] c0_ddr4_s_axi_awprot + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input wire [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input wire c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output wire c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input wire [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input wire [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input wire c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input wire c0_ddr4_s_axi_wvalid + .c0_ddr4_s_axi_wready ( m_axi_wready), // output wire c0_ddr4_s_axi_wready + .c0_ddr4_s_axi_bready ( m_axi_bready), // input wire c0_ddr4_s_axi_bready + .c0_ddr4_s_axi_bid ( m_axi_bid), // output wire [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output wire [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output wire c0_ddr4_s_axi_bvalid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input wire [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input wire [34 : 0] c0_ddr4_s_axi_araddr + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input wire [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input wire [2 : 0] c0_ddr4_s_axi_arsize + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input wire [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input wire [0 : 0] c0_ddr4_s_axi_arlock + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input wire [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input wire [2 : 0] c0_ddr4_s_axi_arprot + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input wire [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input wire c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output wire c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_rready ( m_axi_rready), // input wire c0_ddr4_s_axi_rready + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output wire c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output wire c0_ddr4_s_axi_rvalid + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output wire [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output wire [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output wire [511 : 0] c0_ddr4_s_axi_rdata + + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn) + ); + +endmodule diff --git a/piton/design/chipset/xilinx/alveou280/.gitignore b/piton/design/chipset/xilinx/alveou280/.gitignore new file mode 100644 index 000000000..9f9934c3f --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/.gitignore @@ -0,0 +1,2 @@ +!ip_cores +polara_fpga \ No newline at end of file diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc new file mode 100644 index 000000000..02f6d81e5 --- /dev/null +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -0,0 +1,269 @@ +# Bitstream generation +# --------------------------------------------------------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] ;# Choices are pullnone, pulldown, and pullup. +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# --------------------------------------------------------------------- + + +# 156.25MHz General purpose system clock +set_property PACKAGE_PIN F30 [get_ports {chipset_clk_osc_n}] +set_property PACKAGE_PIN G30 [get_ports {chipset_clk_osc_p}] +set_property IOSTANDARD LVDS [get_ports {chipset_clk*}] + +# Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller +set_property PACKAGE_PIN L30 [get_ports resetn] +set_property IOSTANDARD LVCMOS18 [get_ports resetn] + +# UART +set_property PACKAGE_PIN A28 [get_ports uart_rx] +set_property PACKAGE_PIN B33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_*] + +# PCIe MGTY Interface +set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 + +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]} ] ;# Bank 224 - MGTYRXN0_224 +set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]} ] ;# Bank 224 - MGTYRXN1_224 +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]} ] ;# Bank 224 - MGTYRXN2_224 +set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]} ] ;# Bank 224 - MGTYRXN3_224 +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]} ] ;# Bank 224 - MGTYRXP0_224 +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]} ] ;# Bank 224 - MGTYRXP1_224 +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]} ] ;# Bank 224 - MGTYRXP2_224 +set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]} ] ;# Bank 224 - MGTYRXP3_224 +set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]} ] ;# Bank 224 - MGTYTXN0_224 +set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]} ] ;# Bank 224 - MGTYTXN1_224 +set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]} ] ;# Bank 224 - MGTYTXN2_224 +set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]} ] ;# Bank 224 - MGTYTXN3_224 +set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]} ] ;# Bank 224 - MGTYTXP0_224 +set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]} ] ;# Bank 224 - MGTYTXP1_224 +set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]} ] ;# Bank 224 - MGTYTXP2_224 +set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]} ] ;# Bank 224 - MGTYTXP3_224 +# Clock +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n ] ;# Bank 225 - MGTREFCLK0N_225 +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p ] ;# Bank 225 - MGTREFCLK0P_225 + +set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]} ] ;# Bank 225 - MGTYRXN0_225 +set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]} ] ;# Bank 225 - MGTYRXN1_225 +set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]} ] ;# Bank 225 - MGTYRXN2_225 +set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]} ] ;# Bank 225 - MGTYRXN3_225 +set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]} ] ;# Bank 225 - MGTYRXP0_225 +set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]} ] ;# Bank 225 - MGTYRXP1_225 +set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]} ] ;# Bank 225 - MGTYRXP2_225 +set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]} ] ;# Bank 225 - MGTYRXP3_225 +set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]} ] ;# Bank 225 - MGTYTXN0_225 +set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]} ] ;# Bank 225 - MGTYTXN1_225 +set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]} ] ;# Bank 225 - MGTYTXN2_225 +set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 +set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 +set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP2_225 +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP3_225 +set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]} ] ;# Bank 226 - MGTYRXN0_226 +set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]} ] ;# Bank 226 - MGTYRXN1_226 +set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]} ] ;# Bank 226 - MGTYRXN2_226 +set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]} ] ;# Bank 226 - MGTYRXN3_226 +set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]} ] ;# Bank 226 - MGTYRXP0_226 +set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]} ] ;# Bank 226 - MGTYRXP1_226 +set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]} ] ;# Bank 226 - MGTYRXP2_226 +set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]} ] ;# Bank 226 - MGTYRXP3_226 +set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]} ] ;# Bank 226 - MGTYTXN0_226 +set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]} ] ;# Bank 226 - MGTYTXN1_226 +set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]} ] ;# Bank 226 - MGTYTXN2_226 +set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]} ] ;# Bank 226 - MGTYTXN3_226 +set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]} ] ;# Bank 226 - MGTYTXP0_226 +set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]} ] ;# Bank 226 - MGTYTXP1_226 +set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]} ] ;# Bank 226 - MGTYTXP2_226 +set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]} ] ;# Bank 226 - MGTYTXP3_226 +#set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 +set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]} ] ;# Bank 227 - MGTYRXN0_227 +set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]} ] ;# Bank 227 - MGTYRXN1_227 +set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]} ] ;# Bank 227 - MGTYRXN2_227 +set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]} ] ;# Bank 227 - MGTYRXN3_227 +set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]} ] ;# Bank 227 - MGTYRXP0_227 +set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]} ] ;# Bank 227 - MGTYRXP1_227 +set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]} ] ;# Bank 227 - MGTYRXP2_227 +set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]} ] ;# Bank 227 - MGTYRXP3_227 +set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]} ] ;# Bank 227 - MGTYTXN0_227 +set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]} ] ;# Bank 227 - MGTYTXN1_227 +set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]} ] ;# Bank 227 - MGTYTXN2_227 +set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]} ] ;# Bank 227 - MGTYTXN3_227 +set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]} ] ;# Bank 227 - MGTYTXP0_227 +set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]} ] ;# Bank 227 - MGTYTXP1_227 +set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]} ] ;# Bank 227 - MGTYTXP2_227 +set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]} ] ;# Bank 227 - MGTYTXP3_227 + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] + +# 100MHz DDR0 System clock +set_property PACKAGE_PIN BJ44 [get_ports {mc_clk_n}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property PACKAGE_PIN BJ43 [get_ports {mc_clk_p}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 + + +# DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank +# <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# +set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[16]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 +set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +#set_property -dict {PACKAGE_PIN BE46 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property -dict {PACKAGE_PIN BK44 IOSTANDARD SSTL12_DCI} [ get_ports {#NA} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cs_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[13]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +#set_property -dict {PACKAGE_PIN BL47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 +set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_odt[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +#set_property -dict {PACKAGE_PIN BE45 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property -dict {PACKAGE_PIN BD42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[10]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property -dict {PACKAGE_PIN BK41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property -dict {PACKAGE_PIN BJ41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_parity} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 +set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[4]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[3]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[8]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[7]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[11]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[9]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[5]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 +set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[6]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +#set_property -dict {PACKAGE_PIN BJ42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[12]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_act_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 +set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cke[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 +set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[66]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[67]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[64]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[65]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[71]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[70]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[68]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 +set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[69]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 +set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[34]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[35]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property -dict {PACKAGE_PIN BK29 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[33]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[32]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[38]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 +set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[39]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 +set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[37]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 +set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[36]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 +set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[25]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 +set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[24]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 +set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 +set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 +set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [ get_ports {ddr_reset_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 +set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[27]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[26]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 +set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[29]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 +set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[28]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 +set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[30]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 +set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[31]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 +set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 +set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 +set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[17]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 +set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[16]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 +set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 +set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 +set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[19]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 +set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[18]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 +set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[21]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 +set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[20]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 +set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[23]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 +set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[22]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 +set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 +set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 +set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[58]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[57]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[59]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[56]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[61]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[60]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[63]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[62]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 +set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 +set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[40]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[41]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 +set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[42]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[43]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[47]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[46]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[44]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[45]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - L21_T3L_N4_AD8 P_66 +set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[49]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[50]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 +set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[48]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[51]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[52]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[55]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[53]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[54]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 +set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 +set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 +set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 +set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 +set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 +set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 +set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 +set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 +set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 +set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 +set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 +set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[9]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 +set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[8]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 +set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 +set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[10]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[11]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 +set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[12]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 +set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[13]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 +set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[14]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 +set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[15]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 +set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 +set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 + +set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] +set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] \ No newline at end of file diff --git a/piton/design/xilinx/alveou280/devices.xml b/piton/design/xilinx/alveou280/devices.xml new file mode 100644 index 000000000..8162e9c91 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices.xml @@ -0,0 +1,57 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + net + 0xfff0d00000 + 0x100000 + + diff --git a/piton/design/xilinx/alveou280/devices_ariane.xml b/piton/design/xilinx/alveou280/devices_ariane.xml new file mode 100644 index 000000000..e3f99d675 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices_ariane.xml @@ -0,0 +1,77 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x200000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + diff --git a/piton/tools/src/proto/alveou280/board.tcl b/piton/tools/src/proto/alveou280/board.tcl new file mode 100644 index 000000000..e479b8b76 --- /dev/null +++ b/piton/tools/src/proto/alveou280/board.tcl @@ -0,0 +1,45 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "" +set FPGA_PART "xcu280-fsvh2892-2l-e" +set VIVADO_FLOW_PERF_OPT 0 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" + + +# Create a block design containing PCIe and GPIO using the FPGA_PART variable +# It will produce the "meep_shell.bd" file + +source $DV_ROOT/tools/src/proto/${BOARD}/polara.tcl + +# Grab the file from where the above tcl script has placed it +set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/alveou280/polara_fpga/polara_fpga] + + diff --git a/piton/tools/src/proto/alveou280/polara.tcl b/piton/tools/src/proto/alveou280/polara.tcl new file mode 100644 index 000000000..274132d03 --- /dev/null +++ b/piton/tools/src/proto/alveou280/polara.tcl @@ -0,0 +1,364 @@ + +################################################################ +# This is a generated script based on design: polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./tmp_proj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT)1 + +set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2l-e + set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] +} + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 +current_bd_design $design_name + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create interface ports + set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {156250000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $c0_sysclk + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi_ctrl} \ + ] $c0_ddr4_ui_clk + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $resetn + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: axi_xbar_pcie, and set properties + set axi_xbar_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar_pcie ] + set_property -dict [ list \ + CONFIG.M00_HAS_REGSLICE {4} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.S00_HAS_REGSLICE {4} \ + CONFIG.S01_HAS_REGSLICE {4} \ + ] $axi_xbar_pcie + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0.CKE_WIDTH {2} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {11} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {7} \ + CONFIG.C0.DDR4_CasLatency {10} \ + CONFIG.C0.DDR4_CasWriteLatency {9} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod {10044} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PDZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_Specify_MandD {false} \ + CONFIG.C0.DDR4_TimePeriod {1598} \ + CONFIG.C0.ODT_WIDTH {2} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.MAILBOX_ENABLE {true} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.coreclk_freq {250} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.flr_enable {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf0_device_id {902F} \ + CONFIG.pf1_bar0_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar0_prefetchable_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_device_id {922F} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar0_prefetchable_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_device_id {932F} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.testname {mm} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_xbar_pcie/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net c0_ddr4_s_axi_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins axi_xbar_pcie/S01_AXI] + connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins axi_xbar_pcie/S00_AXI] [get_bd_intf_pins qdma_0/M_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net ARESETN_1 [get_bd_pins axi_xbar_pcie/ARESETN] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] + connect_bd_net -net M00_ARESETN_1 [get_bd_pins axi_xbar_pcie/M00_ARESETN] [get_bd_pins axi_xbar_pcie/S01_ARESETN] [get_bd_pins rst_ea_CLK0/peripheral_aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins axi_xbar_pcie/ACLK] [get_bd_pins axi_xbar_pcie/M00_ACLK] [get_bd_pins axi_xbar_pcie/S01_ACLK] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net proc_sys_rst_pcie_peripheral_aresetn [get_bd_pins axi_xbar_pcie/S00_ARESETN] [get_bd_pins proc_sys_rst_pcie/peripheral_aresetn] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_xbar_pcie/S00_ACLK] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + + + + # ########################################################### + # Final changes. Use this block to customize the bd + + # Decrease the PCIe speed for better timing results + + # ########################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 04a332390..3387c9e73 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,100,16384 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/board.list b/piton/tools/src/proto/board.list index 6149781e9..d51b4ffed 100644 --- a/piton/tools/src/proto/board.list +++ b/piton/tools/src/proto/board.list @@ -30,3 +30,4 @@ nexysVideo vivado f1 vivado vcu118 vivado xupp3r vivado +alveou280 vivado diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 376e7143f..d0326f536 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -64,6 +64,7 @@ def usage(): print(" genesys2", file=sys.stderr) print(" nexysVideo", file=sys.stderr) print(" f1", file=sys.stderr) + print(" alveou280", file=sys.stderr) print("\n -d, --design ", file=sys.stderr) print(" Name of design module to synthesize. The default is 'system', which", file=sys.stderr) print(" synthesizes a full system with chip and chipset. See", file=sys.stderr) @@ -74,6 +75,7 @@ def usage(): print(" pico (32bit RISCV core)", file=sys.stderr) print(" pico_het (heterogeneous pico+sparc arrangement)", file=sys.stderr) print(" ariane (64bit RISCV core)", file=sys.stderr) + print(" ara (64bit RISCV vec core)", file=sys.stderr) print("\n --network_config ", file=sys.stderr) print(" Name of the network type to be used:", file=sys.stderr) print(" 2dmesh_config (default)", file=sys.stderr) @@ -490,7 +492,7 @@ def makeDefList(options): #defines.append(df) # disable CSM in this case - if options.core == 'ariane': + if (options.core == 'ariane') or (options.core == 'ara'): defines.append("NO_RTL_CSM") if (options.board == "f1"): @@ -514,7 +516,7 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1"}): + if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1", "alveou280"}): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") @@ -772,6 +774,15 @@ def main(): os.environ['RTL_SPARC' + str(i)] = "1" print_info('setenv RTL_SPARC' + str(i)) + elif options.core == 'ara': + os.environ['PITON_ARA'] = "1" + os.environ['PITON_RV64_PLATFORM'] = "1" + os.environ['WT_DCACHE'] = "1" + + for i in range(int(options.num_tiles)): + os.environ['RTL_ARA' + str(i)] = "1" + print_info('setenv RTL_ARA' + str(i)) + else: print_error("invalid core configuration " + str(options.core)) sys.exit(1) @@ -845,6 +856,9 @@ def main(): if options.core == 'ariane': config += ' -ariane' + + if options.core == 'ara': + config += ' -ara' print_info("Synthesizing a test: %s" % options.test_name) print_info("Compilation started") From affa658bc0259849e7b309289579f0e66942d78f Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:04:09 -0400 Subject: [PATCH 03/23] Include BD in Protosyn flow --- piton/tools/src/proto/common/setup.tcl | 7 ++++++- piton/tools/src/proto/vivado/setup.tcl | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 3a2f15efa..3d101e877 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -62,6 +62,11 @@ foreach ip_file ${ALL_IP_FILE_PREFIXES} { lappend ALL_XCO_IP_FILES "${ip_file}.xco" } +set ALL_BD_FILES [list ] +foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" +} + set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] set ALL_PRJ_IP_FILES [concat ${DESIGN_PRJ_IP_FILES}] @@ -94,7 +99,7 @@ if {[info exists ::env(PITON_PICO_HET)]} { } if {[info exists ::env(PITON_ARIANE)]} { - append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE" + append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT" } for {set k 0} {$k < $::env(PITON_NUM_TILES)} {incr k} { diff --git a/piton/tools/src/proto/vivado/setup.tcl b/piton/tools/src/proto/vivado/setup.tcl index b63e811ae..c5a724e40 100644 --- a/piton/tools/src/proto/vivado/setup.tcl +++ b/piton/tools/src/proto/vivado/setup.tcl @@ -34,4 +34,5 @@ set ALL_FILES [concat \ $ALL_COE_FILES \ $ALL_PRJ_IP_FILES \ $ALL_XCI_IP_FILES \ + $ALL_BD_FILES \ ] From 5c006aacf08cb072a5e861147eddd65a13944197 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:08:21 -0400 Subject: [PATCH 04/23] Update Polara BD for Protosyn --- piton/design/chipset/mc/rtl/u280_polara_top.v | 2 +- piton/tools/src/proto/alveou280/board.tcl | 4 +- .../tools/src/proto/alveou280/polara_fpga.tcl | 364 ++++++++++++++++++ piton/tools/src/proto/common/rtl_setup.tcl | 2 + 4 files changed, 369 insertions(+), 3 deletions(-) create mode 100644 piton/tools/src/proto/alveou280/polara_fpga.tcl diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v index f0dc03286..c5e3bc0b0 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.v +++ b/piton/design/chipset/mc/rtl/u280_polara_top.v @@ -149,7 +149,7 @@ module u280_polara_top ( ); - polara polara_i ( + polara_fpga polara_i ( .c0_sysclk_clk_p ( c0_sysclk_clk_p ), .c0_sysclk_clk_n ( c0_sysclk_clk_n ), diff --git a/piton/tools/src/proto/alveou280/board.tcl b/piton/tools/src/proto/alveou280/board.tcl index e479b8b76..ca739787f 100644 --- a/piton/tools/src/proto/alveou280/board.tcl +++ b/piton/tools/src/proto/alveou280/board.tcl @@ -35,9 +35,9 @@ set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" # Create a block design containing PCIe and GPIO using the FPGA_PART variable -# It will produce the "meep_shell.bd" file +# It will produce the "polara_fpga.bd" file -source $DV_ROOT/tools/src/proto/${BOARD}/polara.tcl +source $DV_ROOT/tools/src/proto/${BOARD}/polara_fpga.tcl # Grab the file from where the above tcl script has placed it set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/alveou280/polara_fpga/polara_fpga] diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl new file mode 100644 index 000000000..f5debf750 --- /dev/null +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -0,0 +1,364 @@ + +################################################################ +# This is a generated script based on design: polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./tmp_proj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT)1 + +set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2L-e + set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] +} + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 +current_bd_design $design_name + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create interface ports + set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $c0_sysclk + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi:c0_ddr4_s_axi_ctrl} \ + ] $c0_ddr4_ui_clk + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $resetn + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.CKE_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {1} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiNarrowBurst.VALUE_SRC {USER} \ + CONFIG.C0.DDR4_AxiIDWidth.VALUE_SRC {USER} \ + CONFIG.C0.DDR4_AxiIDWidth {7} \ + CONFIG.C0.DDR4_AxiNarrowBurst {true} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {15} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataMask {NONE} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_Specify_MandD {false} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.ODT_WIDTH {1} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.MAILBOX_ENABLE {true} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.coreclk_freq {250} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.flr_enable {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf0_device_id {902F} \ + CONFIG.pf1_bar0_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar0_prefetchable_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_device_id {922F} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar0_prefetchable_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_device_id {932F} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.testname {mm} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + ] $smartconnect_0 + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins qdma_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + + # Create port connections + connect_bd_net -net ARESETN_1 [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] [get_bd_pins smartconnect_0/aclk1] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + + + + # ########################################################### + # Final changes. Use this block to customize the bd + + # Decrease the PCIe speed for better timing results + + # ########################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index ab99f7f41..58676a147 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -70,6 +70,8 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/common/rtl/bram_1rw_wrapper.v" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ "${DV_ROOT}/design/common/rtl/synchronizer.v" \ + "${DV_ROOT}/design/common/rtl/noc_simple_splitter.v" \ + "${DV_ROOT}/design/common/rtl/noc_simple_merger.v" \ "${DV_ROOT}/design/chip/rtl/OCI.v" \ "${DV_ROOT}/design/chip/rtl/chip.v" \ "${DV_ROOT}/design/chip/pll/rtl/pll_top.v" \ From aa2f730cfd0c4b80823e32d6e967c1dcc6ba1e68 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:13:35 -0400 Subject: [PATCH 05/23] Add Alveo U280 config options and IPs --- piton/design/chipset/include/mc_define.h | 19 + .../ip_cores/uart_16550/uart_16550.xci | 142 +++ piton/design/chipset/rtl/chipset.v | 44 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 69 +- .../afifo_w64_d128_std/afifo_w64_d128_std.xci | 582 +++++++++++++ .../alveou280/ip_cores/clk_mmcm/clk_mmcm.xci | 823 ++++++++++++++++++ piton/design/include/piton_system.vh | 15 + piton/design/rtl/system.v | 49 +- piton/tools/src/proto/fpga_lib.py | 15 +- piton/tools/src/proto/protosyn,2.5 | 5 +- 10 files changed, 1745 insertions(+), 18 deletions(-) create mode 100644 piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci create mode 100644 piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci create mode 100644 piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci diff --git a/piton/design/chipset/include/mc_define.h b/piton/design/chipset/include/mc_define.h index 133877099..15edf8ef5 100644 --- a/piton/design/chipset/include/mc_define.h +++ b/piton/design/chipset/include/mc_define.h @@ -105,6 +105,25 @@ `define DDR3_CS_WIDTH 2 `define DDR3_BG_WIDTH 2 `define DDR3_ODT_WIDTH 2 +`elsif ALVEO_BOARD + `define BOARD_MEM_SIZE_MB 8192 + `define WORDS_PER_BURST 8 + `define WORD_SIZE 8 // in bytes + `define MIG_APP_ADDR_WIDTH 32 + `define MIG_APP_CMD_WIDTH 3 + `define MIG_APP_DATA_WIDTH 512 + `define MIG_APP_MASK_WIDTH 64 + + `define DDR3_DQ_WIDTH 72 + `define DDR3_DQS_WIDTH 18 + `define DDR3_ADDR_WIDTH 17 + `define DDR3_BA_WIDTH 2 + `define DDR3_DM_WIDTH 0 + `define DDR3_CK_WIDTH 1 + `define DDR3_CKE_WIDTH 1 + `define DDR3_CS_WIDTH 1 + `define DDR3_BG_WIDTH 2 + `define DDR3_ODT_WIDTH 1 `elsif NEXYS4DDR_BOARD `define BOARD_MEM_SIZE_MB 256 `define WORDS_PER_BURST 8 diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci new file mode 100644 index 000000000..8c27abbec --- /dev/null +++ b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci @@ -0,0 +1,142 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_16550 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 25000000 + virtexuplushbm + 0 + 0 + 1 + VERSAL_AI_CORE_ES1 + 100000000 + 1 + 25000000 + 25 + 0 + 0 + 16550 + 100000000 + 100 + 1 + 1 + uart_16550 + Custom + false + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 26 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 840b49d23..5da36d0ef 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -93,7 +93,16 @@ module chipset( `endif `ifdef F1_BOARD input sys_clk, -`else +`elsif ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , // Oscillator clock `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK @@ -249,11 +258,11 @@ module chipset( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -467,13 +476,13 @@ module chipset( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, - `elsif XUPP3R_BOARD + `elsif XUPP3R_OR_ALVEO // no switches :( `else input [7:0] sw, `endif - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO output [3:0] leds `else output [7:0] leds @@ -731,7 +740,7 @@ end `ifdef VCU118_BOARD assign uart_boot_en = sw[0]; assign uart_timeout_en = sw[1]; - `elsif XUPP3R_BOARD + `elsif XUPP3R_OR_ALVEO assign uart_boot_en = 1'b1; assign uart_timeout_en = 1'b0; `else @@ -789,6 +798,11 @@ end assign leds[1] = init_calib_complete; assign leds[2] = processor_offchip_noc2_valid; assign leds[3] = offchip_processor_noc3_valid; +`elsif ALVEO_BOARD + assign leds[0] = 1'b1; + assign leds[1] = init_calib_complete; + assign leds[2] = processor_offchip_noc2_valid; + assign leds[3] = offchip_processor_noc3_valid; `else // PITON_BOARD assign leds[0] = clk_locked; assign leds[1] = ~piton_ready_n; @@ -1288,11 +1302,11 @@ chipset_impl_noc_power_test chipset_impl ( .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), - `endif // XUPP3R_BOARD + `endif // XUPP3R_OR_ALVEO .ddr_odt(ddr_odt) `else // ifndef F1_BOARD .mc_clk(mc_clk), @@ -1402,6 +1416,20 @@ chipset_impl_noc_power_test chipset_impl ( `endif // PITON_FPGA_ETHERNETLITE `endif // endif PITONSYS_IOCTRL + `ifdef ALVEO_BOARD + , // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + .chip_rstn (chip_rstn) + + `endif + ); diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 1fd900c79..1bf1af2dc 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -92,6 +92,17 @@ module chipset_impl( output wire bad_end, input wire test_ena, `endif +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , +`endif `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 @@ -158,11 +169,11 @@ module chipset_impl( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -799,6 +810,54 @@ credit_to_valrdy noc3_xbar_to_%s( .m_axi_bready(m_axi_bready), .ddr_ready(ddr_ready) ); + `elsif ALVEO_BOARD + u280_polara_top u280_polara_i ( + + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + + // DDR4 physicall interface + .c0_ddr4_act_n ( ddr_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( ddr_addr ), + .c0_ddr4_ba ( ddr_ba ), + .c0_ddr4_bg ( ddr_bg ), // bank group address + .c0_ddr4_ck_t ( ddr_ck_p ), + .c0_ddr4_ck_c ( ddr_ck_n ), + .c0_ddr4_cke ( ddr_cke ), + .c0_ddr4_cs_n ( ddr_cs_n ), + .c0_ddr4_dq ( ddr_dq ), + .c0_ddr4_dqs_c ( ddr_dqs_n ), + .c0_ddr4_dqs_t ( ddr_dqs_p ), + .c0_ddr4_odt ( ddr_odt ), + .c0_ddr4_par ( ddr_parity ), // output wire c0_ddr4_parity + .c0_ddr4_reset_n ( ddr_reset_n ), + + // DDR4 clock & reset + .c0_sysclk_clk_p ( mc_clk_p ), + .c0_sysclk_clk_n ( mc_clk_n ), + + .c0_init_calib_complete ( init_calib_complete ), + + .chip_rstn (chip_rstn ), + .chipset_clk (chipset_clk ), + .chipset_rstn (chipset_rst_n ), + + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_rdy(buf_mem_noc3_ready) + + ); `else mc_top mc_top( .mc_ui_clk_sync_rst(mc_ui_clk_sync_rst), @@ -1171,7 +1230,11 @@ fake_uart fake_uart ( // this is for selecting the right bootrom (1: baremetal, 0: linux) wire ariane_boot_sel; `ifdef PITON_FPGA_SYNTH - assign ariane_boot_sel = uart_boot_en; + `ifdef ALVEO_BOARD + assign ariane_boot_sel = 1'b1; + `else + assign ariane_boot_sel = uart_boot_en; + `endif `else `ifdef ARIANE_SIM_LINUX_BOOT assign ariane_boot_sel = 1'b0; diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci new file mode 100644 index 000000000..e3bdaecc8 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w64_d128_std + + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 7 + BlankString + 64 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 64 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplusHBM + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x72 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1 + 7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 7 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + afifo_w64_d128_std + 64 + false + 7 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 64 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 64 + 128 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 7 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 7 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci new file mode 100644 index 000000000..02843e9a1 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci @@ -0,0 +1,823 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 100.000 + 0000 + 0000 + 100.00000 + 0000 + 0000 + 250.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100 + 0.000 + 1 + 0000 + 0000 + 50.00000 + BUFG + 50.0 + false + 250.00000 + 0.000 + 50.000 + 250.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 50.00000 + 0.000 + 50.000 + 50 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 25.00000 + BUFG + 50.0 + false + 100.00000 + 180.000 + 50.000 + 100.000 + 180.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 25.00000 + 0.000 + 50.000 + 25.000 + 0.000 + 1 + 1 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + VCO + clk_in_sel + chipset_clk + mc_sys_clk + sd_sys_clk + chipset_passthru_clk + chipset_passthru_clk_n + net_phy_clk + net_axi_clk + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.4 + 2.0 + 1.0 + 1.0 + 4.0 + 1.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________100_______________35 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 10.000 + 0.000 + FALSE + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 20 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + 10 + 0.500 + 180.000 + FALSE + 40 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.004 + 0.010 + FALSE + 128.000 + 2.000 + 7 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + chipset_clk__100.00000______0.000______50.0______129.254_____98.575 + mc_sys_clk__250.00000______0.000______50.0______108.624_____98.575 + sd_sys_clk__50.00000______0.000______50.0______147.729_____98.575 + chipset_passthru_clk__100.00000______0.000______50.0______129.254_____98.575 + chipset_passthru_clk_n__100.00000____180.000______50.0______129.254_____98.575 + net_phy_clk__25.00000______0.000______50.0______168.830_____98.575 + net_axi_clk__100.00000______0.000______50.0______129.254_____98.575 + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1600.000 + 800.000 + clk_mmcm + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 35 + 100.000 + 100.000 + BUFG + 129.254 + false + 98.575 + 50.000 + 100 + 0.000 + 1 + true + BUFG + 108.624 + false + 98.575 + 50.000 + 250.000 + 0.000 + 1 + true + BUFG + 147.729 + false + 98.575 + 50.000 + 50 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 180.000 + 1 + true + BUFG + 168.830 + false + 98.575 + 50.000 + 25.000 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + 600.000 + Custom + Custom + clk_in_sel + chipset_clk + false + mc_sys_clk + false + sd_sys_clk + false + chipset_passthru_clk + false + chipset_passthru_clk_n + false + net_phy_clk + false + net_axi_clk + false + CLK_VALID + auto + clk_mmcm + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + PS + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 20 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + 10 + 0.500 + 180.000 + false + 40 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.004 + 0.010 + false + 7 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/include/piton_system.vh b/piton/design/include/piton_system.vh index 5b6618fd8..0c25e8f71 100644 --- a/piton/design/include/piton_system.vh +++ b/piton/design/include/piton_system.vh @@ -122,6 +122,8 @@ `define PITON_CHIPSET_DIFF_CLK `elsif GENESYS2_BOARD `define PITON_CHIPSET_DIFF_CLK +`elsif ALVEO_BOARD + `define PITON_CHIPSET_DIFF_CLK `elsif PITON_BOARD `define PITON_CHIPSET_DIFF_CLK `define PITON_CHIPSET_DIFF_CLK_POLARITY_CAPS @@ -134,6 +136,8 @@ `define PITON_FPGA_RST_ACT_HIGH `elsif VCU118_BOARD `define PITON_FPGA_RST_ACT_HIGH +`elsif ALVEO_BOARD + `define PITON_FPGA_RST_ACT_HIGH `endif `ifdef XUPP3R_BOARD @@ -143,6 +147,9 @@ `undef PITON_FPGA_SD_BOOT `undef PITONSYS_SPI `define PITONSYS_AXI4_MEM +`elsif ALVEO_BOARD + `undef PITON_FPGA_SD_BOOT + `undef PITONSYS_SPI `endif // If PITON_FPGA_SD_BOOT is set we should always include SPI @@ -159,4 +166,12 @@ `define PITONSYS_DDR4 `elsif XUPP3R_BOARD `define PITONSYS_DDR4 +`elsif ALVEO_BOARD + `define PITONSYS_DDR4 `endif + +`ifdef XUPP3R_BOARD + `define XUPP3R_OR_ALVEO +`elsif ALVEO_BOARD + `define XUPP3R_OR_ALVEO +`endif \ No newline at end of file diff --git a/piton/design/rtl/system.v b/piton/design/rtl/system.v index 48362dfdf..732d4448d 100644 --- a/piton/design/rtl/system.v +++ b/piton/design/rtl/system.v @@ -112,6 +112,17 @@ module system( input passthru_chipset_clk_n, `endif // endif PITON_PASSTHRU_CLKS_GEN `endif // endif PITON_SYS_INC_PASSTHRU + +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , +`endif `ifndef F1_BOARD `ifdef PITON_CHIPSET_CLKS_GEN @@ -147,7 +158,9 @@ module system( input sys_clk, `endif +`ifndef ALVEO_BOARD input sys_rst_n, +`endif `ifndef PITON_FPGA_SYNTH input fll_rst_n, @@ -188,6 +201,7 @@ module system( `ifndef VCU118_BOARD `ifndef NEXYSVIDEO_BOARD `ifndef XUPP3R_BOARD +`ifndef ALVEO_BOARD `ifndef F1_BOARD input tck_i, input tms_i, @@ -195,6 +209,7 @@ module system( input td_i, output td_o, `endif//F1_BOARD +`endif //ALVEO_BOARD `endif//XUPP3R_BOARD `endif //NEXYSVIDEO_BOARD `endif //VCU118_BOARD @@ -238,11 +253,11 @@ module system( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, - `endif // XUPP3R_BOARD + `endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -392,7 +407,7 @@ module system( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, -`elsif XUPP3R_BOARD +`elsif XUPP3R_OR_ALVEO // no switches :( `else input [7:0] sw, @@ -400,6 +415,8 @@ module system( `ifdef XUPP3R_BOARD output [3:0] leds +`elsif ALVEO_BOARD + output hbm_cattrip `else output [7:0] leds `endif @@ -528,6 +545,13 @@ wire uart_rst_out_n; assign uart_rts = 1'b0; `endif // VCU118_BOARD +`ifdef ALVEO_BOARD + + wire sys_rst_n; + assign hbm_cattrip = 1'b0; + +`endif + // Different reset active levels for different boards always @ * begin @@ -991,6 +1015,17 @@ chipset chipset( .mc_clk_n(mc_clk_n), `endif // PITONSYS_DDR4 +`ifdef ALVEO_BOARD + .pcie_refclk_clk_n (pcie_refclk_clk_n) , + .pcie_refclk_clk_p (pcie_refclk_clk_p) , + .pcie_perstn (pcie_perstn) , + .pci_express_x16_rxn (pci_express_x16_rxn) , + .pci_express_x16_rxp (pci_express_x16_rxp) , + .pci_express_x16_txn (pci_express_x16_txn ) , + .pci_express_x16_txp (pci_express_x16_txp) , + .resetn (resetn), +`endif + `else // ifndef PITON_CHIPSET_CLKS_GEN .chipset_clk(chipset_clk), `ifndef PITONSYS_NO_MC @@ -1112,7 +1147,7 @@ chipset chipset( `ifndef NEXYSVIDEO_BOARD .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), @@ -1180,6 +1215,10 @@ chipset chipset( `endif // PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC +`ifdef ALVEO_BOARD + .chip_rstn (sys_rst_n), +`endif + `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART .uart_tx(uart_tx), @@ -1249,7 +1288,7 @@ chipset chipset( .btnc(btnc), `endif -`ifndef XUPP3R_BOARD +`ifndef XUPP3R_OR_ALVEO .sw(sw), `endif .leds(leds) diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index 46f0870ea..a223f1536 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -48,6 +48,7 @@ NOC_PAYLOAD_WIDTH = 512 STORAGE_BLOCK_BIT_WIDTH = { "ddr": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":128, "genesys2":256, @@ -56,6 +57,7 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -65,6 +67,7 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -76,6 +79,7 @@ STORAGE_ADDRESSABLE_BIT_WIDTH = { "ddr": { "vc707":64, "vcu118":64, + "alveou280":72, "xupp3r":64, "nexys4ddr":16, "genesys2":32, @@ -84,6 +88,7 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -93,17 +98,21 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, "nexysVideo":512, "piton_board":512, "f1":512 + }, + "hbm": { "alveou280":33 } } STORAGE_BIT_SIZE = { "ddr": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, @@ -112,6 +121,7 @@ }, "bram": { "vc707":16384*512, "vcu118":16384*512, + "alveou280":116384*512, "xupp3r":16384*512, "nexys4ddr":16384*512, "genesys2":16384*512, @@ -121,11 +131,14 @@ }, "dmw": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, "nexysVideo":8*512*2**20, "f1":8*4*2**30 + }, + "hbm": { "alveou280":8*4*2*33 } } DW_BIT_SIZE = 64 @@ -345,7 +358,7 @@ def buildProjectSuccess(log_dir): dbg.print_error("Check: %s" % fpath) return False - dbg.print_info("Project was build successfully!") + dbg.print_info("Project was built successfully!") return True diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index d0326f536..2fd0e35b2 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -498,6 +498,9 @@ def makeDefList(options): if (options.board == "f1"): print_info("design option is ignored for f1") + if (options.board == "alveou280"): + defines.append("PITON_ALVEO") + # --no-ddr option if (options.no_ddr == True) or (options.board == "piton_board"): defines.append("PITONSYS_NO_MC") @@ -516,7 +519,7 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1", "alveou280"}): + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") From 6e5090bff33429767ea33ac35153c8cb9fd0e561 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:15:11 -0400 Subject: [PATCH 06/23] Replaced Polara BD creation file --- piton/tools/src/proto/alveou280/polara.tcl | 364 --------------------- 1 file changed, 364 deletions(-) delete mode 100644 piton/tools/src/proto/alveou280/polara.tcl diff --git a/piton/tools/src/proto/alveou280/polara.tcl b/piton/tools/src/proto/alveou280/polara.tcl deleted file mode 100644 index 274132d03..000000000 --- a/piton/tools/src/proto/alveou280/polara.tcl +++ /dev/null @@ -1,364 +0,0 @@ - -################################################################ -# This is a generated script based on design: polara_fpga -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source design_1_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./tmp_proj/project_1.xpr> in the current working folder. - -set DV_ROOT $::env(DV_ROOT) -set PITON_ROOT $::env(PITON_ROOT)1 - -set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo -set tmp_prj "create_bd" - -file delete -force ${tmp_build_dir}/${tmp_prj} - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2l-e - set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] -} - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name polara_fpga - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 -current_bd_design $design_name - - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - - -################################################################## -# DESIGN PROCs -################################################################## - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - # Create interface ports - set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] - - set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {64} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {512} \ - CONFIG.FREQ_HZ {156250000} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {1} \ - CONFIG.HAS_CACHE {1} \ - CONFIG.HAS_LOCK {1} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {1} \ - CONFIG.HAS_REGION {1} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.MAX_BURST_LENGTH {256} \ - CONFIG.NUM_READ_OUTSTANDING {1} \ - CONFIG.NUM_READ_THREADS {1} \ - CONFIG.NUM_WRITE_OUTSTANDING {1} \ - CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {1} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $c0_ddr4_s_axi - - set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {32} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {0} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {0} \ - CONFIG.ID_WIDTH {0} \ - CONFIG.MAX_BURST_LENGTH {1} \ - CONFIG.NUM_READ_OUTSTANDING {1} \ - CONFIG.NUM_READ_THREADS {1} \ - CONFIG.NUM_WRITE_OUTSTANDING {1} \ - CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PROTOCOL {AXI4LITE} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {0} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $c0_ddr4_s_axi_ctrl - - set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {100000000} \ - ] $c0_sysclk - - set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] - - set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] - - - # Create ports - set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] - set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi_ctrl} \ - ] $c0_ddr4_ui_clk - set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] - set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] - set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] - set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] - set resetn [ create_bd_port -dir I -type rst resetn ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $resetn - - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] - set_property -dict [ list \ - CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_GPIO_WIDTH {2} \ - ] $axi_gpio_0 - - # Create instance: axi_xbar_pcie, and set properties - set axi_xbar_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar_pcie ] - set_property -dict [ list \ - CONFIG.M00_HAS_REGSLICE {4} \ - CONFIG.NUM_MI {1} \ - CONFIG.NUM_SI {2} \ - CONFIG.S00_HAS_REGSLICE {4} \ - CONFIG.S01_HAS_REGSLICE {4} \ - ] $axi_xbar_pcie - - # Create instance: chip_rstn, and set properties - set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] - set_property -dict [ list \ - CONFIG.DIN_FROM {1} \ - CONFIG.DIN_TO {1} \ - CONFIG.DIN_WIDTH {2} \ - CONFIG.DOUT_WIDTH {1} \ - ] $chip_rstn - - # Create instance: ddr4_0, and set properties - set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] - set_property -dict [ list \ - CONFIG.C0.CKE_WIDTH {2} \ - CONFIG.C0.CS_WIDTH {2} \ - CONFIG.C0.DDR4_AxiAddressWidth {34} \ - CONFIG.C0.DDR4_AxiDataWidth {512} \ - CONFIG.C0.DDR4_CLKFBOUT_MULT {11} \ - CONFIG.C0.DDR4_CLKOUT0_DIVIDE {7} \ - CONFIG.C0.DDR4_CasLatency {10} \ - CONFIG.C0.DDR4_CasWriteLatency {9} \ - CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ - CONFIG.C0.DDR4_DataWidth {72} \ - CONFIG.C0.DDR4_EN_PARITY {true} \ - CONFIG.C0.DDR4_Ecc {true} \ - CONFIG.C0.DDR4_InputClockPeriod {10044} \ - CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ - CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PDZ-2G3} \ - CONFIG.C0.DDR4_MemoryType {RDIMMs} \ - CONFIG.C0.DDR4_Specify_MandD {false} \ - CONFIG.C0.DDR4_TimePeriod {1598} \ - CONFIG.C0.ODT_WIDTH {2} \ - ] $ddr4_0 - - # Create instance: proc_sys_rst_pcie, and set properties - set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] - - # Create instance: qdma_0, and set properties - set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] - set_property -dict [ list \ - CONFIG.MAILBOX_ENABLE {true} \ - CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ - CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ - CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ - CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ - CONFIG.SRIOV_CAP_ENABLE {true} \ - CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ - CONFIG.axi_data_width {256_bit} \ - CONFIG.barlite_mb_pf0 {1} \ - CONFIG.coreclk_freq {250} \ - CONFIG.dma_intf_sel_qdma {AXI_MM} \ - CONFIG.en_axi_st_qdma {false} \ - CONFIG.flr_enable {true} \ - CONFIG.mode_selection {Advanced} \ - CONFIG.pf0_ari_enabled {true} \ - CONFIG.pf0_bar0_prefetchable_qdma {true} \ - CONFIG.pf0_bar2_prefetchable_qdma {true} \ - CONFIG.pf0_device_id {902F} \ - CONFIG.pf1_bar0_prefetchable_qdma {true} \ - CONFIG.pf1_bar2_prefetchable_qdma {true} \ - CONFIG.pf1_msix_enabled_qdma {false} \ - CONFIG.pf2_bar0_prefetchable_qdma {true} \ - CONFIG.pf2_bar2_prefetchable_qdma {true} \ - CONFIG.pf2_device_id {922F} \ - CONFIG.pf2_msix_enabled_qdma {false} \ - CONFIG.pf3_bar0_prefetchable_qdma {true} \ - CONFIG.pf3_bar2_prefetchable_qdma {true} \ - CONFIG.pf3_device_id {932F} \ - CONFIG.pf3_msix_enabled_qdma {false} \ - CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ - CONFIG.testname {mm} \ - ] $qdma_0 - - # Create instance: rst_ea_CLK0, and set properties - set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] - - # Create instance: sys_rstn, and set properties - set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] - set_property -dict [ list \ - CONFIG.DIN_WIDTH {2} \ - ] $sys_rstn - - # Create instance: util_ds_buf, and set properties - set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] - set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDSGTE} \ - ] $util_ds_buf - - # Create instance: vdd_0, and set properties - set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] - - # Create interface connections - connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_xbar_pcie/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] - connect_bd_intf_net -intf_net c0_ddr4_s_axi_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins axi_xbar_pcie/S01_AXI] - connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] - connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] - connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] - connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins axi_xbar_pcie/S00_AXI] [get_bd_intf_pins qdma_0/M_AXI] - connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] - connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] - - # Create port connections - connect_bd_net -net ARESETN_1 [get_bd_pins axi_xbar_pcie/ARESETN] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] - connect_bd_net -net M00_ARESETN_1 [get_bd_pins axi_xbar_pcie/M00_ARESETN] [get_bd_pins axi_xbar_pcie/S01_ARESETN] [get_bd_pins rst_ea_CLK0/peripheral_aresetn] - connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] - connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] - connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins axi_xbar_pcie/ACLK] [get_bd_pins axi_xbar_pcie/M00_ACLK] [get_bd_pins axi_xbar_pcie/S01_ACLK] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] - connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] - connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] - connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] - connect_bd_net -net proc_sys_rst_pcie_peripheral_aresetn [get_bd_pins axi_xbar_pcie/S00_ARESETN] [get_bd_pins proc_sys_rst_pcie/peripheral_aresetn] - connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_xbar_pcie/S00_ACLK] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] - connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] - connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] - connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] - connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] - connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] - connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] - connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] - connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] - - # Create address segments - assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force - assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force - assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force - assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force - - - - # ########################################################### - # Final changes. Use this block to customize the bd - - # Decrease the PCIe speed for better timing results - - # ########################################################### - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - -close_project - -file delete -force ${tmp_build_dir}/${tmp_prj} - - From 5c0d3a7deb857ed9b223518f411ef0ac585e8212 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 14 Aug 2023 15:09:56 -0400 Subject: [PATCH 07/23] [FPGA] Update Alveo U280 constraints --- piton/design/xilinx/alveou280/constraints.xdc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index 02f6d81e5..4b630a5cb 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -13,6 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] # --------------------------------------------------------------------- +# Don't time the GPIO reset signals +set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] # 156.25MHz General purpose system clock set_property PACKAGE_PIN F30 [get_ports {chipset_clk_osc_n}] From e6229a6f446d734deb4f4d7d72be526a0d870e2f Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 29 Aug 2023 15:51:00 -0400 Subject: [PATCH 08/23] [FPGA] Bug fixing on U280 flow --- piton/design/chipset/mc/rtl/u280_polara_top.v | 2 + piton/design/xilinx/alveou280/constraints.xdc | 7 +- .../tools/src/proto/alveou280/polara_fpga.tcl | 2 +- piton/tools/src/proto/common/rtl_setup.tcl | 287 +++++++++--------- 4 files changed, 157 insertions(+), 141 deletions(-) diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v index c5e3bc0b0..7e27ac496 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.v +++ b/piton/design/chipset/mc/rtl/u280_polara_top.v @@ -1,6 +1,8 @@ `include "mc_define.h" +`include "noc_axi4_bridge_define.vh" + module u280_polara_top ( input pcie_refclk_clk_n , diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index 4b630a5cb..a79e70f5e 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -68,8 +68,8 @@ set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]} ] set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 -set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP2_225 -set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP3_225 +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP2_225 +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP3_225 set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]} ] ;# Bank 226 - MGTYRXN0_226 set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]} ] ;# Bank 226 - MGTYRXN1_226 set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]} ] ;# Bank 226 - MGTYRXN2_226 @@ -268,4 +268,5 @@ set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [ get_p set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] -set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] \ No newline at end of file +set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] + diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl index f5debf750..37ffca4eb 100644 --- a/piton/tools/src/proto/alveou280/polara_fpga.tcl +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -29,7 +29,7 @@ set script_folder [_tcl::get_script_folder] # <./tmp_proj/project_1.xpr> in the current working folder. set DV_ROOT $::env(DV_ROOT) -set PITON_ROOT $::env(PITON_ROOT)1 +set PITON_ROOT $::env(PITON_ROOT) set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo set tmp_prj "create_bd" diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 58676a147..0959cc4d5 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,7 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" # RTL include files @@ -399,153 +399,156 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_tag.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_config_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_soc_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi/src/axi_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_axi_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/wt_cache_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/axi_intf.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/acc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_soc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/wt_cache_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/axi_intf.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/cvxif_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/cf_math_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/instr_tracer_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/include/cvxif_instr_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/acc_dispatcher.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_master_connect.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_master_connect_rev.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_slave_connect.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_slave_connect_rev.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/rrarbiter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/fifo_v1.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/fifo_v2.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/fifo_v3.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/shift_reg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lfsr_8bit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lfsr.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lzc.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/exp_backoff.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/rr_arb_tree.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/rstgen_bypass.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/cdc_2phase.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/unread.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/popcount.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/fpga/tc_clk_xilinx.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/fpga/tc_sram_xilinx.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/tc_sram_xilinx_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/axi_adapter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ariane.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/controller.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/csr_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/csr_regfile.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ex_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/btb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/bht.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/ras.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_scan.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_queue.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/frontend.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/id_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/instr_realign.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/issue_read_operands.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/issue_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/load_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/load_store_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/lsu_bypass.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/mmu.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mult.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/multiplier.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/serdiv.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/perf_counters.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/ptw.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ariane_regfile_ff.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/re_name.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/scoreboard.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/store_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/amo_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/store_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/tlb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/commit_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_ctrl.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_missunit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache_axi_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_l15_adapter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_cache_subsystem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/clint.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/axi_lite_interface.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/debug_rom/debug_rom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_csrs.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_top.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_cdc.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_sba.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/fifo_v3.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/shift_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lfsr.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lzc.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/exp_backoff.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/cdc_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/unread.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/popcount.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/tc_sram_fpga_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/axi_adapter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/ariane.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/controller.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/csr_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/csr_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/ex_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/btb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/bht.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/ras.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_scan.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/frontend.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/id_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/instr_realign.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/issue_read_operands.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/issue_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/load_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/load_store_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/lsu_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/mmu.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mult.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/multiplier.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/serdiv.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/perf_counters.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/ptw.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/ariane_regfile_ff.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/re_name.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/scoreboard.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/store_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/amo_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/store_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/tlb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/commit_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_ctrl.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_missunit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache_axi_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_l15_adapter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_cache_subsystem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/clint.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/axi_lite_interface.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/debug_rom/debug_rom.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_csrs.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_sba.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_cast_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_classifier.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_divsqrt_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_fma_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_fma.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_noncomp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_block.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_fmt_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_multifmt_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_rounding.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_fma.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_top.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp_entry.sv" \ \ + "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp_entry.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/instr_tracer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/instr_tracer_if.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/cvxif_example_coprocessor.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/instr_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/counter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/delta_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/counter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axilite.sv " \ "${DV_ROOT}/design/chip/tile/ara/openpiton/strb2mask.v" \ @@ -563,8 +566,10 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_to_mem.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/ctrl_registers.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/cva6_accel_first_pass_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/power_gating_generic.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/fixed_p_rounding.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queues_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/ara_popcnt.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_alu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/valu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vmfpu.sv" \ @@ -577,6 +582,8 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_mul.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_regfile.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/masku/masku.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/p2_stride_gen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu_op_dp.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/addrgen.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vldu.sv" \ @@ -682,6 +689,12 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mailbox.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_dst.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_regs.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_err_slv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ ] set CHIP_INCLUDE_FILES [list \ From 100aa4236d4bed5cc5f98ba09bdb433f47abea4b Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 9 Oct 2023 17:27:37 -0400 Subject: [PATCH 09/23] [FPGA] Polara timing fix at 50MHz --- .../design/chipset/mc/rtl/u280_polara_top.sv | 327 +++++++++++++ piton/design/chipset/rtl/chipset.v | 4 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 9 +- .../alveou280/ip_cores/clk_mmcm/clk_mmcm.xci | 28 +- piton/design/xilinx/alveou280/constraints.xdc | 456 +++++++++--------- .../tools/src/proto/alveou280/polara_fpga.tcl | 38 +- piton/tools/src/proto/block.list | 2 +- piton/tools/src/proto/common/rtl_setup.tcl | 12 +- 8 files changed, 617 insertions(+), 259 deletions(-) create mode 100644 piton/design/chipset/mc/rtl/u280_polara_top.sv diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.sv b/piton/design/chipset/mc/rtl/u280_polara_top.sv new file mode 100644 index 000000000..cf9823117 --- /dev/null +++ b/piton/design/chipset/mc/rtl/u280_polara_top.sv @@ -0,0 +1,327 @@ + +`include "mc_define.h" + +`include "noc_axi4_bridge_define.vh" + +module u280_polara_top ( + + input logic pcie_refclk_clk_n , + input logic pcie_refclk_clk_p , + input logic pcie_perstn , + input logic [15:0] pci_express_x16_rxn , + input logic [15:0] pci_express_x16_rxp , + output logic [15:0] pci_express_x16_txn , + output logic [15:0] pci_express_x16_txp , + input logic resetn , + + output logic c0_ddr4_act_n, + output logic [16:0] c0_ddr4_adr, + output logic [1:0] c0_ddr4_ba, + output logic [1:0] c0_ddr4_bg, + output logic [0:0] c0_ddr4_ck_c, + output logic [0:0] c0_ddr4_ck_t, + output logic [0:0] c0_ddr4_cke, + output logic [0:0] c0_ddr4_cs_n, + inout wire [71:0] c0_ddr4_dq, + inout wire [17:0] c0_ddr4_dqs_c, + inout wire [17:0] c0_ddr4_dqs_t, + output logic [0:0] c0_ddr4_odt, + output logic c0_ddr4_par, + output logic c0_ddr4_reset_n, + output logic c0_ddr4_ui_clk_sync_rst, + + // Reference clock + input logic c0_sysclk_clk_n, + input logic c0_sysclk_clk_p, + // input mc_clk , + // input mc_rstn , + output logic chip_rstn , + input logic chipset_clk , + input logic chipset_rstn , + output logic c0_init_calib_complete, + + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , + + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy +); + +// ------------------Debug Section----------------- +(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_rdy_r; +(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_rdy_r; +/* +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_rdy_r; +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_rdy_r;*/ + + + logic mc_rst; + logic mc_clk; + + + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; + + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_awid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_awlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_awsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_awburst; + logic m_axi_awlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_awcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_awprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_awqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_awregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_awuser; + logic m_axi_awvalid; + logic m_axi_awready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_wdata; + logic [`AXI4_STRB_WIDTH -1:0] m_axi_wstrb; + logic m_axi_wlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; + logic m_axi_wvalid; + logic m_axi_wready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_arid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_araddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_arlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_arsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_arburst; + logic m_axi_arlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_arcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_arprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_arqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; + logic m_axi_arvalid; + logic m_axi_arready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_rid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_rdata; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_rresp; + logic m_axi_rlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_ruser; + logic m_axi_rvalid; + logic m_axi_rready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_bid; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_bresp; + logic [`AXI4_USER_WIDTH -1:0] m_axi_buser; + logic m_axi_bvalid; + logic m_axi_bready; + + noc_bidir_afifo mig_afifo ( + .clk_1 ( chipset_clk ), + .rst_1 ( ~chipset_rstn ), + + .clk_2 ( mc_clk ), + .rst_2 ( mc_rst ), + + // CPU --> MIG + .flit_in_val_1 ( mem_flit_in_val ), + .flit_in_data_1 ( mem_flit_in_data ), + .flit_in_rdy_1 ( mem_flit_in_rdy ), + + .flit_out_val_2 ( fifo_trans_val ), + .flit_out_data_2 ( fifo_trans_data ), + .flit_out_rdy_2 ( fifo_trans_rdy ), + + // MIG --> CPU + .flit_in_val_2 ( trans_fifo_val ), + .flit_in_data_2 ( trans_fifo_data ), + .flit_in_rdy_2 ( trans_fifo_rdy ), + + .flit_out_val_1 ( mem_flit_out_val ), + .flit_out_data_1 ( mem_flit_out_data ), + .flit_out_rdy_1 ( mem_flit_out_rdy ) + ); + + + noc_axi4_bridge noc_axi4_bridge ( + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( c0_init_calib_complete ), + + .src_bridge_vr_noc2_val ( fifo_trans_val ), + .src_bridge_vr_noc2_dat ( fifo_trans_data ), + .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), + + .bridge_dst_vr_noc3_val ( trans_fifo_val ), + .bridge_dst_vr_noc3_dat ( trans_fifo_data ), + .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + + .m_axi_wid ( m_axi_wid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_buser ( m_axi_buser ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + + .m_axi_rid ( m_axi_rid), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + + ); + + polara_fpga polara_i ( + + .c0_sysclk_clk_p ( c0_sysclk_clk_p ), + .c0_sysclk_clk_n ( c0_sysclk_clk_n ), + .c0_ddr4_ui_clk ( mc_clk ), + .c0_ddr4_ui_clk_sync_rst ( mc_rst ), + .c0_init_calib_complete ( c0_init_calib_complete ), + + // DDR4 physicall interface + .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_par ( c0_ddr4_par ), // output logic c0_ddr4_parity + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + + // DDR4 control interface, not used, grounded + .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_awvalid + .c0_ddr4_s_axi_ctrl_awready( ), // output logic c0_ddr4_s_axi_ctrl_awready + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output logic c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output logic c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_arvalid + .c0_ddr4_s_axi_ctrl_arready( ), // output logic c0_ddr4_s_axi_ctrl_arready + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output logic c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output logic [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_rresp + + .chip_rstn ( chip_rstn ), + + // AXI4 Memory Interface + .c0_ddr4_s_axi_awid ( m_axi_awid), // input logic [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input logic [34 : 0] c0_ddr4_s_axi_awaddr + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input logic [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input logic [2 : 0] c0_ddr4_s_axi_awsize + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input logic [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input logic [0 : 0] c0_ddr4_s_axi_awlock + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input logic [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input logic [2 : 0] c0_ddr4_s_axi_awprot + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input logic [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input logic c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output logic c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input logic [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input logic [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input logic c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input logic c0_ddr4_s_axi_wvalid + .c0_ddr4_s_axi_wready ( m_axi_wready), // output logic c0_ddr4_s_axi_wready + .c0_ddr4_s_axi_bready ( m_axi_bready), // input logic c0_ddr4_s_axi_bready + .c0_ddr4_s_axi_bid ( m_axi_bid), // output logic [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output logic [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output logic c0_ddr4_s_axi_bvalid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input logic [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input logic [34 : 0] c0_ddr4_s_axi_araddr + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input logic [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input logic [2 : 0] c0_ddr4_s_axi_arsize + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input logic [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input logic [0 : 0] c0_ddr4_s_axi_arlock + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input logic [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input logic [2 : 0] c0_ddr4_s_axi_arprot + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input logic [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input logic c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output logic c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_rready ( m_axi_rready), // input logic c0_ddr4_s_axi_rready + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output logic c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output logic c0_ddr4_s_axi_rvalid + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output logic [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output logic [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output logic [511 : 0] c0_ddr4_s_axi_rdata + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn) + ); + +always @(posedge mc_clk) begin : p_debug + fifo_trans_val_r <= fifo_trans_val; + fifo_trans_rdy_r <= fifo_trans_rdy; + trans_fifo_val_r <= trans_fifo_val; + trans_fifo_rdy_r <= trans_fifo_rdy; + +end +/*always@(posedge mc_clk) begin: p_debug + mem_flit_in_val_r <= mem_flit_in_val; + mem_flit_in_rdy_r <= mem_flit_in_rdy; + mem_flit_out_val_r <= mem_flit_out_val; + mem_flit_out_rdy_r <= mem_flit_out_rdy; +end */ + +endmodule + diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 5da36d0ef..dc0a8a367 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -93,7 +93,8 @@ module chipset( `endif `ifdef F1_BOARD input sys_clk, -`elsif ALVEO_BOARD +`else +`ifdef ALVEO_BOARD input pcie_refclk_clk_n , input pcie_refclk_clk_p , input pcie_perstn , @@ -104,6 +105,7 @@ module chipset( input resetn , output chip_rstn , // Oscillator clock +`endif //ifdef ALVEO_BOARD `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK input clk_osc_p, diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 1bf1af2dc..c98d38835 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -481,8 +481,13 @@ assign chip_buf_noc3_data = {`NOC_DATA_WIDTH{1'b0}}; assign uart_timeout_en = 1'b0; `else // ifdef PITONSYS_UART `ifndef PITONSYS_UART_BOOT - assign uart_boot_en = 1'b0; - assign uart_timeout_en = 1'b0; + `ifndef ALVEO_BOARD + assign uart_boot_en = 1'b0; + assign uart_timeout_en = 1'b0; + `else + assign uart_boot_en = 1'b1; + assign uart_timeout_en = 1'b0; + `endif // endif ALVEO_BOARD `endif // endif PITONSYS_UART_BOOT `endif // endif PITONSYS_UART `endif // endif PITONSYS_IOCTRL diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci index 02843e9a1..e25583f1d 100644 --- a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci @@ -131,17 +131,17 @@ 100.000 0000 0000 - 100.00000 + 50.00000 0000 0000 250.00000 BUFG 50.0 false - 100.00000 + 50.00000 0.000 50.000 - 100 + 50 0.000 1 0000 @@ -236,12 +236,12 @@ din 0000 1 - 0.4 - 2.0 - 1.0 - 1.0 - 4.0 - 1.0 + 0.2 + 1.0 + 0.5 + 0.5 + 2.0 + 0.5 dout drdy dwe @@ -284,7 +284,7 @@ FALSE 10.000 10.000 - 10.000 + 20.000 0.500 0.000 FALSE @@ -326,7 +326,7 @@ 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - chipset_clk__100.00000______0.000______50.0______129.254_____98.575 + chipset_clk__50.00000______0.000______50.0______147.729_____98.575 mc_sys_clk__250.00000______0.000______50.0______108.624_____98.575 sd_sys_clk__50.00000______0.000______50.0______147.729_____98.575 chipset_passthru_clk__100.00000______0.000______50.0______129.254_____98.575 @@ -448,11 +448,11 @@ 100.000 100.000 BUFG - 129.254 + 147.729 false 98.575 50.000 - 100 + 50 0.000 1 true @@ -564,7 +564,7 @@ false 10.000 10.000 - 10.000 + 20.000 0.500 0.000 false diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index a79e70f5e..fbe52f1e9 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -1,15 +1,15 @@ # Bitstream generation # --------------------------------------------------------------------- set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] #set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] ;# Choices are pullnone, pulldown, and pullup. +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] # --------------------------------------------------------------------- @@ -17,101 +17,112 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] # 156.25MHz General purpose system clock -set_property PACKAGE_PIN F30 [get_ports {chipset_clk_osc_n}] -set_property PACKAGE_PIN G30 [get_ports {chipset_clk_osc_p}] -set_property IOSTANDARD LVDS [get_ports {chipset_clk*}] +set_property PACKAGE_PIN G30 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN F30 [get_ports chipset_clk_osc_n] +set_property IOSTANDARD LVDS [get_ports chipset_clk*] # Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller -set_property PACKAGE_PIN L30 [get_ports resetn] -set_property IOSTANDARD LVCMOS18 [get_ports resetn] +set_property PACKAGE_PIN L30 [get_ports resetn] +set_property IOSTANDARD LVCMOS18 [get_ports resetn] # UART -set_property PACKAGE_PIN A28 [get_ports uart_rx] -set_property PACKAGE_PIN B33 [get_ports uart_tx] -set_property IOSTANDARD LVCMOS18 [get_ports uart_*] +set_property PACKAGE_PIN A28 [get_ports uart_rx] +set_property PACKAGE_PIN B33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_*] # PCIe MGTY Interface -set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 -set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] +set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] -set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]} ] ;# Bank 224 - MGTYRXN0_224 -set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]} ] ;# Bank 224 - MGTYRXN1_224 -set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]} ] ;# Bank 224 - MGTYRXN2_224 -set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]} ] ;# Bank 224 - MGTYRXN3_224 -set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]} ] ;# Bank 224 - MGTYRXP0_224 -set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]} ] ;# Bank 224 - MGTYRXP1_224 -set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]} ] ;# Bank 224 - MGTYRXP2_224 -set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]} ] ;# Bank 224 - MGTYRXP3_224 -set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]} ] ;# Bank 224 - MGTYTXN0_224 -set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]} ] ;# Bank 224 - MGTYTXN1_224 -set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]} ] ;# Bank 224 - MGTYTXN2_224 -set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]} ] ;# Bank 224 - MGTYTXN3_224 -set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]} ] ;# Bank 224 - MGTYTXP0_224 -set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]} ] ;# Bank 224 - MGTYTXP1_224 -set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]} ] ;# Bank 224 - MGTYTXP2_224 -set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]} ] ;# Bank 224 - MGTYTXP3_224 +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]}] +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]}] +set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]}] +set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]}] +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]}] +set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]}] +set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]}] +set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]}] +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]}] +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]}] +set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]}] +set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]}] +set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]}] +set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]}] +set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]}] +set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]}] # Clock -set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n ] ;# Bank 225 - MGTREFCLK0N_225 -set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p ] ;# Bank 225 - MGTREFCLK0P_225 +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p] -set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]} ] ;# Bank 225 - MGTYRXN0_225 -set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]} ] ;# Bank 225 - MGTYRXN1_225 -set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]} ] ;# Bank 225 - MGTYRXN2_225 -set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]} ] ;# Bank 225 - MGTYRXN3_225 -set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]} ] ;# Bank 225 - MGTYRXP0_225 -set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]} ] ;# Bank 225 - MGTYRXP1_225 -set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]} ] ;# Bank 225 - MGTYRXP2_225 -set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]} ] ;# Bank 225 - MGTYRXP3_225 -set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]} ] ;# Bank 225 - MGTYTXN0_225 -set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]} ] ;# Bank 225 - MGTYTXN1_225 -set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]} ] ;# Bank 225 - MGTYTXN2_225 -set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 -set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 -set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 -set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP2_225 -set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP3_225 -set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]} ] ;# Bank 226 - MGTYRXN0_226 -set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]} ] ;# Bank 226 - MGTYRXN1_226 -set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]} ] ;# Bank 226 - MGTYRXN2_226 -set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]} ] ;# Bank 226 - MGTYRXN3_226 -set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]} ] ;# Bank 226 - MGTYRXP0_226 -set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]} ] ;# Bank 226 - MGTYRXP1_226 -set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]} ] ;# Bank 226 - MGTYRXP2_226 -set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]} ] ;# Bank 226 - MGTYRXP3_226 -set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]} ] ;# Bank 226 - MGTYTXN0_226 -set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]} ] ;# Bank 226 - MGTYTXN1_226 -set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]} ] ;# Bank 226 - MGTYTXN2_226 -set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]} ] ;# Bank 226 - MGTYTXN3_226 -set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]} ] ;# Bank 226 - MGTYTXP0_226 -set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]} ] ;# Bank 226 - MGTYTXP1_226 -set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]} ] ;# Bank 226 - MGTYTXP2_226 -set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]} ] ;# Bank 226 - MGTYTXP3_226 +set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]}] +set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]}] +set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]}] +set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]}] +set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]}] +set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]}] +set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]}] +set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]}] +set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]}] +set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]}] +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]}] +set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]}] +set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]}] +set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]}] +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]}] +set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]}] +set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]}] +set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]}] +set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]}] +set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]}] +set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]}] +set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]}] +set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]}] +set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]}] +set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]}] +set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]}] +set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]}] +set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]}] +set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]}] +set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]}] +set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]}] +set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]}] #set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 #set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 #set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 #set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 -set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]} ] ;# Bank 227 - MGTYRXN0_227 -set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]} ] ;# Bank 227 - MGTYRXN1_227 -set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]} ] ;# Bank 227 - MGTYRXN2_227 -set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]} ] ;# Bank 227 - MGTYRXN3_227 -set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]} ] ;# Bank 227 - MGTYRXP0_227 -set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]} ] ;# Bank 227 - MGTYRXP1_227 -set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]} ] ;# Bank 227 - MGTYRXP2_227 -set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]} ] ;# Bank 227 - MGTYRXP3_227 -set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]} ] ;# Bank 227 - MGTYTXN0_227 -set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]} ] ;# Bank 227 - MGTYTXN1_227 -set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]} ] ;# Bank 227 - MGTYTXN2_227 -set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]} ] ;# Bank 227 - MGTYTXN3_227 -set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]} ] ;# Bank 227 - MGTYTXP0_227 -set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]} ] ;# Bank 227 - MGTYTXP1_227 -set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]} ] ;# Bank 227 - MGTYTXP2_227 -set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]} ] ;# Bank 227 - MGTYTXP3_227 +set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]}] +set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]}] +set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]}] +set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]}] +set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]}] +set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]}] +set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]}] +set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]}] +set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]}] +set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]}] +set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]}] +set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]}] +set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]}] +set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]}] +set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]}] +set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]}] + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] + +#-------------------------------------------- +# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing +# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 +#Collecting all units from correspondingly PCIe domain, +#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/smartconnect_0] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/qdma_0] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/axi_gpio_0] + -create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] # 100MHz DDR0 System clock -set_property PACKAGE_PIN BJ44 [get_ports {mc_clk_n}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 -set_property PACKAGE_PIN BJ43 [get_ports {mc_clk_p}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +set_property PACKAGE_PIN BJ43 [get_ports mc_clk_p] +set_property PACKAGE_PIN BJ44 [get_ports mc_clk_n] # DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank @@ -119,154 +130,157 @@ set_property PACKAGE_PIN BJ43 [get_ports {mc_clk_p}] ;# # JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 # Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 # -set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[16]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 -set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[16]}] +set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[15]}] #set_property -dict {PACKAGE_PIN BE46 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 #set_property -dict {PACKAGE_PIN BK44 IOSTANDARD SSTL12_DCI} [ get_ports {#NA} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 -set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cs_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 -set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[13]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cs_n[0]}] +set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[13]}] #set_property -dict {PACKAGE_PIN BL47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 -set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 -set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_odt[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[14]}] +set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_odt[0]}] #set_property -dict {PACKAGE_PIN BE45 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 #set_property -dict {PACKAGE_PIN BD42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 -set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 -set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[10]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 -set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 -set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[0]}] +set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[10]}] +set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_n[0]}] +set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_p[0]}] #set_property -dict {PACKAGE_PIN BK41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 #set_property -dict {PACKAGE_PIN BJ41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 -set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 -set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_parity} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 -set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 -set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 -set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 -set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[4]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 -set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[3]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[1]}] +set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [get_ports ddr_parity] +set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[0]}] +set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[2]}] +set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[1]}] +set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[4]}] +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[3]}] #set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 -set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[8]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 -set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[7]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 -set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[11]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 -set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[9]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 -set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[5]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 -set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[6]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[8]}] +set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[7]}] +set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[11]}] +set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[9]}] +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[5]}] +set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[6]}] #set_property -dict {PACKAGE_PIN BJ42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 -set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 -set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[12]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 -set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_act_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 -set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cke[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 -set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 -set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[66]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 -set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[67]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 -set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 -set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 -set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[64]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 -set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[65]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 -set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[71]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 -set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[70]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 -set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[68]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 -set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[69]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 -set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 -set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 -set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[34]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 -set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[35]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 -set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 -set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[1]}] +set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[12]}] +set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [get_ports ddr_act_n] +set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cke[0]}] +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[0]}] +set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[66]}] +set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[67]}] +set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[16]}] +set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[16]}] +set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[64]}] +set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[65]}] +set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[71]}] +set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[70]}] +set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[68]}] +set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[69]}] +set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[17]}] +set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[17]}] +set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[34]}] +set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[35]}] +set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[8]}] +set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[8]}] #set_property -dict {PACKAGE_PIN BK29 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 -set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[33]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 -set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[32]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 -set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[38]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 -set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[39]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 -set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[37]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 -set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[36]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 -set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 -set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 -set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[25]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 -set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[24]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 -set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 -set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 -set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [ get_ports {ddr_reset_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 -set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[27]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 -set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[26]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 -set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[29]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 -set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[28]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 -set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[30]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 -set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[31]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 -set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 -set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 -set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[17]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 -set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[16]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 -set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 -set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 -set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[19]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 -set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[18]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 -set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[21]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 -set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[20]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 -set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[23]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 -set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[22]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 -set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 -set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 -set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[58]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 -set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[57]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 -set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 -set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 -set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[59]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 -set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[56]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 -set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[61]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 -set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[60]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 -set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[63]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 -set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[62]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 -set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 -set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 -set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[40]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 -set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[41]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 -set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 -set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 -set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[42]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 -set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[43]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 -set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[47]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 -set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[46]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 -set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[44]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 -set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[45]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - L21_T3L_N4_AD8 P_66 -set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 -set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 -set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[49]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 -set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[50]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 -set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 -set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 -set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[48]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 -set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[51]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 -set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[52]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 -set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[55]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 -set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[53]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 -set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[54]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 -set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 -set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 -set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 -set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 -set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 -set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 -set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 -set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 -set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 -set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 -set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 -set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 -set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 -set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 -set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[9]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 -set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[8]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 -set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 -set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 -set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[10]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 -set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[11]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 -set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[12]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 -set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[13]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 -set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[14]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 -set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[15]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 -set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 -set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 +set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[33]}] +set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[32]}] +set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[38]}] +set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[39]}] +set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[37]}] +set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[36]}] +set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[9]}] +set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[9]}] +set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[25]}] +set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[24]}] +set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[6]}] +set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[6]}] +set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [get_ports ddr_reset_n] +set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[27]}] +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[26]}] +set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[29]}] +set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[28]}] +set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[30]}] +set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[31]}] +set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[7]}] +set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[7]}] +set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[17]}] +set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[16]}] +set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[4]}] +set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[4]}] +set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[19]}] +set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[18]}] +set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[21]}] +set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[20]}] +set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[23]}] +set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[22]}] +set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[5]}] +set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[5]}] +set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[58]}] +set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[57]}] +set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[14]}] +set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[14]}] +set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[59]}] +set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[56]}] +set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[61]}] +set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[60]}] +set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[63]}] +set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[62]}] +set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[15]}] +set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[15]}] +set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[40]}] +set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[41]}] +set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[10]}] +set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[10]}] +set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[42]}] +set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[43]}] +set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[47]}] +set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[46]}] +set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[44]}] +set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[45]}] +set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[11]}] +set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[11]}] +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[49]}] +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[50]}] +set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[12]}] +set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[12]}] +set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[48]}] +set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[51]}] +set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[52]}] +set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[55]}] +set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[53]}] +set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[54]}] +set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[13]}] +set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[13]}] +set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[2]}] +set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[3]}] +set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[0]}] +set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[0]}] +set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[1]}] +set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[0]}] +set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[6]}] +set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[7]}] +set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[4]}] +set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[5]}] +set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[1]}] +set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[1]}] +set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[9]}] +set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[8]}] +set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[2]}] +set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[2]}] +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[10]}] +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[11]}] +set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[12]}] +set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[13]}] +set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[14]}] +set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[15]}] +set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[3]}] +set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[3]}] + +set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] +set_property PULLDOWN true [get_ports hbm_cattrip] + +set_false_path -from [get_pins chipset/chipset_impl/u280_polara_i/polara_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] -set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] -set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl index 37ffca4eb..06b41694d 100644 --- a/piton/tools/src/proto/alveou280/polara_fpga.tcl +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -111,14 +111,14 @@ proc create_root_design { parentCell } { CONFIG.DATA_WIDTH {512} \ CONFIG.FREQ_HZ {300000000} \ CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {0} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {0} \ + CONFIG.HAS_WSTRB {1} \ CONFIG.ID_WIDTH {6} \ CONFIG.MAX_BURST_LENGTH {256} \ CONFIG.NUM_READ_OUTSTANDING {1} \ @@ -185,9 +185,6 @@ proc create_root_design { parentCell } { set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] set resetn [ create_bd_port -dir I -type rst resetn ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $resetn # Create instance: axi_gpio_0, and set properties set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] @@ -242,19 +239,31 @@ proc create_root_design { parentCell } { set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] set_property -dict [ list \ CONFIG.MAILBOX_ENABLE {true} \ - CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ - CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ - CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ - CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ + CONFIG.PF0_SRIOV_CAP_INITIAL_VF {4} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF1_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF1_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF2_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF2_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF3_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF3_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {0} \ CONFIG.SRIOV_CAP_ENABLE {true} \ CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ CONFIG.axi_data_width {256_bit} \ CONFIG.barlite_mb_pf0 {1} \ + CONFIG.barlite_mb_pf1 {0} \ + CONFIG.barlite_mb_pf2 {0} \ + CONFIG.barlite_mb_pf3 {0} \ CONFIG.coreclk_freq {250} \ CONFIG.dma_intf_sel_qdma {AXI_MM} \ CONFIG.en_axi_st_qdma {false} \ CONFIG.flr_enable {true} \ CONFIG.mode_selection {Advanced} \ + CONFIG.pcie_blk_locn {PCIE4C_X1Y0} \ + CONFIG.select_quad {GTY_Quad_227} \ CONFIG.pf0_ari_enabled {true} \ CONFIG.pf0_bar0_prefetchable_qdma {true} \ CONFIG.pf0_bar2_prefetchable_qdma {true} \ @@ -271,6 +280,7 @@ proc create_root_design { parentCell } { CONFIG.pf3_device_id {932F} \ CONFIG.pf3_msix_enabled_qdma {false} \ CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X16} \ CONFIG.testname {mm} \ ] $qdma_0 diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 3387c9e73..056f6862c 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,100,16384 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 0959cc4d5..37b714ee9 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,7 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" # RTL include files @@ -499,8 +499,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/baremetal/bootrom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ @@ -694,9 +692,11 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_regs.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_err_slv.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_cdc.sv" \ - "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ ] + + set CHIP_INCLUDE_FILES [list \ ] @@ -809,7 +809,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ - "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.sv" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ @@ -897,7 +897,7 @@ set CHIPSET_INCLUDE_FILES [list \ "${DV_ROOT}/design/chipset/include/uart16550_define.vh" \ "${DV_ROOT}/design/chipset/include/chipset_define.vh" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_define.vh" \ - "${DV_ROOT}/design/chip/tile/ariane/src/common_cells/include/common_cells/registers.svh" + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/include/common_cells/registers.svh" ] set CHIPSET_IP_FILE_PREFIXES [list \ From f3e55d79be6e13dfcadc20ce77f57664a0544910 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 31 Oct 2023 10:42:08 -0400 Subject: [PATCH 10/23] [FPGA] Fix latches in L2 and BRAM wrapper --- piton/design/common/rtl/bram_1r1w_wrapper.v | 1 + 1 file changed, 1 insertion(+) diff --git a/piton/design/common/rtl/bram_1r1w_wrapper.v b/piton/design/common/rtl/bram_1r1w_wrapper.v index 73ddcbe45..210db1dce 100644 --- a/piton/design/common/rtl/bram_1r1w_wrapper.v +++ b/piton/design/common/rtl/bram_1r1w_wrapper.v @@ -115,6 +115,7 @@ always @ * begin // note: DOUT retains value if read enable is not asserted // which is why default value is not set for DOUT + DOUTA=0; // default value if (read_enable_in_reg) begin DOUTA = bram_data_read_out_reg; if (rw_conflict_r) begin From cb5dcd77af15aa360e9ac056ce1d20aa94902394 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 31 Oct 2023 10:43:13 -0400 Subject: [PATCH 11/23] [FPGA] Update constraints --- piton/design/xilinx/alveou280/constraints.xdc | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index fbe52f1e9..19e29b9f3 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -17,8 +17,8 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] # 156.25MHz General purpose system clock -set_property PACKAGE_PIN G30 [get_ports chipset_clk_osc_p] -set_property PACKAGE_PIN F30 [get_ports chipset_clk_osc_n] +set_property PACKAGE_PIN BH6 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN BJ6 [get_ports chipset_clk_osc_n] set_property IOSTANDARD LVDS [get_ports chipset_clk*] # Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller @@ -109,14 +109,6 @@ set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]}] create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] -#-------------------------------------------- -# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing -# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 -#Collecting all units from correspondingly PCIe domain, -#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied -set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/smartconnect_0] -set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/qdma_0] -set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/axi_gpio_0] @@ -283,4 +275,7 @@ set_property PULLDOWN true [get_ports hbm_cattrip] set_false_path -from [get_pins chipset/chipset_impl/u280_polara_i/polara_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells [get_cells -of_objects [get_nets -of_objects [get_pins -hierarchical qdma_0/axi_aclk]]]] + + From 40b49ad44a37a468c5ab0308bb2954223c22dad2 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 31 Oct 2023 10:47:08 -0400 Subject: [PATCH 12/23] [FPGA] Update UART IP frequency config --- .../xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci | 6 +++--- .../ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci index 8c27abbec..446f476c3 100644 --- a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci +++ b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci @@ -53,15 +53,15 @@ 0 1 VERSAL_AI_CORE_ES1 - 100000000 + 50000000 1 25000000 25 0 0 16550 - 100000000 - 100 + 50000000 + 50 1 1 uart_16550 diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci index e3bdaecc8..2b46f7650 100644 --- a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -501,7 +501,7 @@ FIFO FIFO virtexuplusHBM - + xilinx.com:au280:part0:1.2 xcu280 fsvh2892 From df94cc38a217cdedbe0b0c012d6f81cf12f8186a Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 14 Nov 2023 10:39:47 -0500 Subject: [PATCH 13/23] Remove old U280 Polara top --- piton/design/chipset/mc/rtl/u280_polara_top.v | 249 ------------------ 1 file changed, 249 deletions(-) delete mode 100644 piton/design/chipset/mc/rtl/u280_polara_top.v diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v deleted file mode 100644 index 7e27ac496..000000000 --- a/piton/design/chipset/mc/rtl/u280_polara_top.v +++ /dev/null @@ -1,249 +0,0 @@ - -`include "mc_define.h" - -`include "noc_axi4_bridge_define.vh" - -module u280_polara_top ( - - input pcie_refclk_clk_n , - input pcie_refclk_clk_p , - input pcie_perstn , - input [15:0] pci_express_x16_rxn , - input [15:0] pci_express_x16_rxp , - output [15:0] pci_express_x16_txn , - output [15:0] pci_express_x16_txp , - input resetn , - - output c0_ddr4_act_n, - output [16:0] c0_ddr4_adr, - output [1:0] c0_ddr4_ba, - output [1:0] c0_ddr4_bg, - output [0:0] c0_ddr4_ck_c, - output [0:0] c0_ddr4_ck_t, - output [0:0] c0_ddr4_cke, - output [0:0] c0_ddr4_cs_n, - inout [71:0] c0_ddr4_dq, - inout [17:0] c0_ddr4_dqs_c, - inout [17:0] c0_ddr4_dqs_t, - output [0:0] c0_ddr4_odt, - output c0_ddr4_par, - output c0_ddr4_reset_n, - output c0_ddr4_ui_clk_sync_rst, - // Reference clock - input c0_sysclk_clk_n, - input c0_sysclk_clk_p, - // input mc_clk , - // input mc_rstn , - output chip_rstn , - input chipset_clk , - output chipset_rstn , - output c0_init_calib_complete, - - input [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , - input mem_flit_in_val , - output mem_flit_in_rdy , - - output [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , - output mem_flit_out_val , - input mem_flit_out_rdy -); - - - wire trans_fifo_val; - wire [`NOC_DATA_WIDTH-1:0] trans_fifo_data; - wire trans_fifo_rdy; - - wire fifo_trans_val; - wire [`NOC_DATA_WIDTH-1:0] fifo_trans_data; - wire fifo_trans_rdy; - - - noc_bidir_afifo mig_afifo ( - .clk_1 ( chipset_clk ), - .rst_1 ( ~chipset_rstn ), - - .clk_2 ( mc_clk ), - .rst_2 ( mc_rst ), - - // CPU --> MIG - .flit_in_val_1 ( mem_flit_in_val ), - .flit_in_data_1 ( mem_flit_in_data ), - .flit_in_rdy_1 ( mem_flit_in_rdy ), - - .flit_out_val_2 ( fifo_trans_val ), - .flit_out_data_2 ( fifo_trans_data ), - .flit_out_rdy_2 ( fifo_trans_rdy ), - - // MIG --> CPU - .flit_in_val_2 ( trans_fifo_val ), - .flit_in_data_2 ( trans_fifo_data ), - .flit_in_rdy_2 ( trans_fifo_rdy ), - - .flit_out_val_1 ( mem_flit_out_val ), - .flit_out_data_1 ( mem_flit_out_data ), - .flit_out_rdy_1 ( mem_flit_out_rdy ) - ); - - - noc_axi4_bridge noc_axi4_bridge ( - .clk ( mc_clk ), - .rst_n ( ~mc_rst ), - .uart_boot_en ( 1'b0 ), - .phy_init_done ( init_calib_complete ), - - .src_bridge_vr_noc2_val ( fifo_trans_val ), - .src_bridge_vr_noc2_dat ( fifo_trans_data ), - .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), - - .bridge_dst_vr_noc3_val ( trans_fifo_val ), - .bridge_dst_vr_noc3_dat ( trans_fifo_data ), - .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), - - .m_axi_awid ( m_axi_awid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awprot ( m_axi_awprot ), - .m_axi_awqos ( m_axi_awqos ), - .m_axi_awregion ( m_axi_awregion ), - .m_axi_awuser ( m_axi_awuser ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awready ( m_axi_awready ), - - .m_axi_wid ( m_axi_wid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_wuser ( m_axi_wuser ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wready ( m_axi_wready ), - - .m_axi_bid ( m_axi_bid ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_buser ( m_axi_buser ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_bready ( m_axi_bready ), - - .m_axi_arid ( m_axi_arid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arqos ( m_axi_arqos ), - .m_axi_arregion ( m_axi_arregion ), - .m_axi_aruser ( m_axi_aruser ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_arready ( m_axi_arready ), - - .m_axi_rid ( m_axi_rid), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_ruser ( m_axi_ruser ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rready ( m_axi_rready ) - - ); - - polara_fpga polara_i ( - - .c0_sysclk_clk_p ( c0_sysclk_clk_p ), - .c0_sysclk_clk_n ( c0_sysclk_clk_n ), - .c0_ddr4_ui_clk ( mc_clk ), - .c0_ddr4_ui_clk_sync_rst ( mc_rst ), - .c0_init_calib_complete ( init_calib_complete ), - - - // DDR4 physicall interface - .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 - .c0_ddr4_adr ( c0_ddr4_adr ), - .c0_ddr4_ba ( c0_ddr4_ba ), - .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address - .c0_ddr4_ck_t ( c0_ddr4_ck_t ), - .c0_ddr4_ck_c ( c0_ddr4_ck_c ), - .c0_ddr4_cke ( c0_ddr4_cke ), - .c0_ddr4_cs_n ( c0_ddr4_cs_n ), - .c0_ddr4_dq ( c0_ddr4_dq ), - .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), - .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), - .c0_ddr4_odt ( c0_ddr4_odt ), - .c0_ddr4_par ( c0_ddr4_par ), // output wire c0_ddr4_parity - .c0_ddr4_reset_n ( c0_ddr4_reset_n ), - - // DDR4 control interface, not used, grounded - .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_awvalid - .c0_ddr4_s_axi_ctrl_awready( ), // output wire c0_ddr4_s_axi_ctrl_awready - .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_awaddr - .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_wvalid - .c0_ddr4_s_axi_ctrl_wready ( ), // output wire c0_ddr4_s_axi_ctrl_wready - .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_wdata - .c0_ddr4_s_axi_ctrl_bvalid ( ), // output wire c0_ddr4_s_axi_ctrl_bvalid - .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_bready - .c0_ddr4_s_axi_ctrl_bresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_bresp - .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_arvalid - .c0_ddr4_s_axi_ctrl_arready( ), // output wire c0_ddr4_s_axi_ctrl_arready - .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_araddr - .c0_ddr4_s_axi_ctrl_rvalid ( ), // output wire c0_ddr4_s_axi_ctrl_rvalid - .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_rready - .c0_ddr4_s_axi_ctrl_rdata ( ), // output wire [31 : 0] c0_ddr4_s_axi_ctrl_rdata - .c0_ddr4_s_axi_ctrl_rresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_rresp - - .chip_rstn ( chip_rstn ), - - // AXI4 Memory Interface - .c0_ddr4_s_axi_awid ( m_axi_awid), // input wire [15 : 0] c0_ddr4_s_axi_awid - .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input wire [34 : 0] c0_ddr4_s_axi_awaddr - .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input wire [7 : 0] c0_ddr4_s_axi_awlen - .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input wire [2 : 0] c0_ddr4_s_axi_awsize - .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input wire [1 : 0] c0_ddr4_s_axi_awburst - .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input wire [0 : 0] c0_ddr4_s_axi_awlock - .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input wire [3 : 0] c0_ddr4_s_axi_awcache - .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input wire [2 : 0] c0_ddr4_s_axi_awprot - .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input wire [3 : 0] c0_ddr4_s_axi_awqos - .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input wire c0_ddr4_s_axi_awvalid - .c0_ddr4_s_axi_awready ( m_axi_awready), // output wire c0_ddr4_s_axi_awready - .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input wire [511 : 0] c0_ddr4_s_axi_wdata - .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input wire [63 : 0] c0_ddr4_s_axi_wstrb - .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input wire c0_ddr4_s_axi_wlast - .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input wire c0_ddr4_s_axi_wvalid - .c0_ddr4_s_axi_wready ( m_axi_wready), // output wire c0_ddr4_s_axi_wready - .c0_ddr4_s_axi_bready ( m_axi_bready), // input wire c0_ddr4_s_axi_bready - .c0_ddr4_s_axi_bid ( m_axi_bid), // output wire [15 : 0] c0_ddr4_s_axi_bid - .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output wire [1 : 0] c0_ddr4_s_axi_bresp - .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output wire c0_ddr4_s_axi_bvalid - .c0_ddr4_s_axi_arid ( m_axi_arid), // input wire [15 : 0] c0_ddr4_s_axi_arid - .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input wire [34 : 0] c0_ddr4_s_axi_araddr - .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input wire [7 : 0] c0_ddr4_s_axi_arlen - .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input wire [2 : 0] c0_ddr4_s_axi_arsize - .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input wire [1 : 0] c0_ddr4_s_axi_arburst - .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input wire [0 : 0] c0_ddr4_s_axi_arlock - .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input wire [3 : 0] c0_ddr4_s_axi_arcache - .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input wire [2 : 0] c0_ddr4_s_axi_arprot - .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input wire [3 : 0] c0_ddr4_s_axi_arqos - .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input wire c0_ddr4_s_axi_arvalid - .c0_ddr4_s_axi_arready ( m_axi_arready), // output wire c0_ddr4_s_axi_arready - .c0_ddr4_s_axi_rready ( m_axi_rready), // input wire c0_ddr4_s_axi_rready - .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output wire c0_ddr4_s_axi_rlast - .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output wire c0_ddr4_s_axi_rvalid - .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output wire [1 : 0] c0_ddr4_s_axi_rresp - .c0_ddr4_s_axi_rid ( m_axi_rid), // output wire [15 : 0] c0_ddr4_s_axi_rid - .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output wire [511 : 0] c0_ddr4_s_axi_rdata - - // PCIe - .pci_express_x16_rxn(pci_express_x16_rxn), - .pci_express_x16_rxp(pci_express_x16_rxp), - .pci_express_x16_txn(pci_express_x16_txn), - .pci_express_x16_txp(pci_express_x16_txp), - .pcie_perstn(pcie_perstn), - .pcie_refclk_clk_n(pcie_refclk_clk_n), - .pcie_refclk_clk_p(pcie_refclk_clk_p), - .resetn(resetn) - ); - -endmodule From 317cc7ffa50bb5843bf71ccea4935f3f730c32cb Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 14 Nov 2023 15:55:49 -0500 Subject: [PATCH 14/23] [FPGA] Remove debug probes --- .../design/chipset/mc/rtl/u280_polara_top.sv | 25 ------------------- 1 file changed, 25 deletions(-) diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.sv b/piton/design/chipset/mc/rtl/u280_polara_top.sv index cf9823117..1652b9060 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.sv +++ b/piton/design/chipset/mc/rtl/u280_polara_top.sv @@ -49,17 +49,6 @@ module u280_polara_top ( input logic mem_flit_out_rdy ); -// ------------------Debug Section----------------- -(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_rdy_r; -(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_rdy_r; -/* -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_rdy_r; -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_rdy_r;*/ - logic mc_rst; logic mc_clk; @@ -309,19 +298,5 @@ module u280_polara_top ( .resetn(resetn) ); -always @(posedge mc_clk) begin : p_debug - fifo_trans_val_r <= fifo_trans_val; - fifo_trans_rdy_r <= fifo_trans_rdy; - trans_fifo_val_r <= trans_fifo_val; - trans_fifo_rdy_r <= trans_fifo_rdy; - -end -/*always@(posedge mc_clk) begin: p_debug - mem_flit_in_val_r <= mem_flit_in_val; - mem_flit_in_rdy_r <= mem_flit_in_rdy; - mem_flit_out_val_r <= mem_flit_out_val; - mem_flit_out_rdy_r <= mem_flit_out_rdy; -end */ - endmodule From f3d6d5275db56607042eb3bb9ba75be4b43f6643 Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Mon, 27 Nov 2023 16:41:51 -0500 Subject: [PATCH 15/23] Merge PLIC CLINT to FPGA branch --- piton/tools/src/sims/manycore.config | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index d5ac3e635..6412e0d91 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -77,11 +77,25 @@ #endif #ifdef FLIST_ARIANE -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ara +<<<<<<< HEAD -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" +======= +<<<<<<< HEAD + -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane + -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform + -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi" +======= + -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic + -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform + -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane + -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic + -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" +>>>>>>> c4b8f67 (Integrating PLIC CLINT and Debug unit) +>>>>>>> bb7c54e (Merge PLIC CLINT to FPGA branch) -vcs_build_args=-timescale=1ps/1ps -rv64 -rv64_platform From 62ce9b0be292d973ee55d44d6934ce85dbaea3ce Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Mon, 27 Nov 2023 16:41:51 -0500 Subject: [PATCH 16/23] Fix merge conflicts PLIC CLINT --- .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv | 28 ++----------------- piton/tools/src/sims/manycore.config | 16 +---------- 2 files changed, 3 insertions(+), 41 deletions(-) diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv index 0aace9a3c..e5c89b8df 100644 --- a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv +++ b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv @@ -236,8 +236,8 @@ simplenocbuffer simplenocbuffer( .msg_val(noc2_data_val) ); -reg l15_noc2decoder_ack; -reg l15_noc2decoder_header_ack; +wire l15_noc2decoder_ack; +wire l15_noc2decoder_header_ack; wire noc2decoder_l15_val; wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; wire noc2decoder_l15_l2miss; @@ -291,30 +291,6 @@ noc2decoder noc2decoder( .l15_dmbr_l2responseIn() ); -// Mimic l15 behaviour for the l15 ACK signals -reg l15_noc2decoder_ack_next; -reg l15_noc2decoder_header_ack_next; - -always @(posedge clk) begin - if (~rst_n) begin - l15_noc2decoder_ack <= 1'b0; - l15_noc2decoder_header_ack <= 1'b0; - end else begin - l15_noc2decoder_ack <= l15_noc2decoder_ack_next; - l15_noc2decoder_header_ack <= l15_noc2decoder_header_ack_next; - end -end - -always @* begin - if (noc2_data_val) begin - l15_noc2decoder_ack_next = 1'b1; - l15_noc2decoder_header_ack_next = 1'b1; - end else begin - l15_noc2decoder_ack_next = 1'b0; - l15_noc2decoder_header_ack_next = 1'b0; - end -end - reg new_edge_irq; reg new_edge_irq_next; diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 6412e0d91..c338ab004 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -77,25 +77,11 @@ #endif #ifdef FLIST_ARIANE -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ara -<<<<<<< HEAD -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" -======= -<<<<<<< HEAD - -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane - -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform - -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi" -======= - -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic - -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform - -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane - -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic - -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" ->>>>>>> c4b8f67 (Integrating PLIC CLINT and Debug unit) ->>>>>>> bb7c54e (Merge PLIC CLINT to FPGA branch) -vcs_build_args=-timescale=1ps/1ps -rv64 -rv64_platform @@ -179,4 +165,4 @@ -midas_args=-mmu=niagara -sim_run_args=+wait_cycle_to_kill=10 -vcs_cm_args=line+tgl+cond+branch+fsm - + \ No newline at end of file From 84eefd814dd21e399560240a23d748386d063536 Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Tue, 28 Nov 2023 21:51:36 -0500 Subject: [PATCH 17/23] Fixed PLIC bug --- .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv index e5c89b8df..0aace9a3c 100644 --- a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv +++ b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv @@ -236,8 +236,8 @@ simplenocbuffer simplenocbuffer( .msg_val(noc2_data_val) ); -wire l15_noc2decoder_ack; -wire l15_noc2decoder_header_ack; +reg l15_noc2decoder_ack; +reg l15_noc2decoder_header_ack; wire noc2decoder_l15_val; wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; wire noc2decoder_l15_l2miss; @@ -291,6 +291,30 @@ noc2decoder noc2decoder( .l15_dmbr_l2responseIn() ); +// Mimic l15 behaviour for the l15 ACK signals +reg l15_noc2decoder_ack_next; +reg l15_noc2decoder_header_ack_next; + +always @(posedge clk) begin + if (~rst_n) begin + l15_noc2decoder_ack <= 1'b0; + l15_noc2decoder_header_ack <= 1'b0; + end else begin + l15_noc2decoder_ack <= l15_noc2decoder_ack_next; + l15_noc2decoder_header_ack <= l15_noc2decoder_header_ack_next; + end +end + +always @* begin + if (noc2_data_val) begin + l15_noc2decoder_ack_next = 1'b1; + l15_noc2decoder_header_ack_next = 1'b1; + end else begin + l15_noc2decoder_ack_next = 1'b0; + l15_noc2decoder_header_ack_next = 1'b0; + end +end + reg new_edge_irq; reg new_edge_irq_next; From 7f6564354ae658a28393f87adda307aab73dd870 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Wed, 6 Dec 2023 08:22:37 -0500 Subject: [PATCH 18/23] [FPGA] PLIC/CLINT Integration --- .../design/chipset/io_ctrl/rtl/int_pkt_gen.v | 2 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 43 +++++++++++++++++-- .../xilinx/alveou280/devices_ariane.xml | 21 --------- piton/tools/bin/riscvlib.py | 4 +- piton/tools/src/proto/common/rtl_setup.tcl | 17 +++++++- piton/tools/src/proto/common/setup.tcl | 2 +- 6 files changed, 60 insertions(+), 29 deletions(-) diff --git a/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v b/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v index ae747e8c0..08dad8596 100644 --- a/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v +++ b/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v @@ -178,7 +178,7 @@ always @(*) begin pkt_flit1[63:50] = chip_id; pkt_flit1[49:42] = x_pos; pkt_flit1[41:34] = y_pos; - pkt_flit1[33:30] = 4'b0; // processor + pkt_flit1[33:30] = 4'h5; // processor pkt_flit1[29:22] = 8'b1; if (NOC_ID == 1) begin pkt_flit1[21:14] = `MSG_TYPE_INTERRUPT_FWD; // interrupt forward diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index c98d38835..c9d29a2ac 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -347,6 +347,14 @@ wire chip_filter_noc3_ready; wire test_good_end; wire test_bad_end; +wire int_pkt_filter_noc2_valid; +wire [`NOC_DATA_WIDTH-1:0] int_pkt_filter_noc2_data; +wire filter_int_pkt_noc2_ready; + +wire uart_merger_filter_noc2_valid; +wire [`NOC_DATA_WIDTH-1:0] uart_merger_filter_noc2_data; +wire filter_uart_merger_noc2_ready; + <% for i in range(len(devices)): if devices[i]["virtual"]: @@ -1060,9 +1068,9 @@ uart_top uart_top ( .xbar_uart_noc3_ready ( buf_uart_noc3_ready ), // output to noc2 - .uart_xbar_noc2_valid ( uart_filter_noc2_valid ), - .uart_xbar_noc2_data ( uart_filter_noc2_data ), - .xbar_uart_noc2_ready ( filter_uart_noc2_ready ), + .uart_xbar_noc2_valid ( uart_merger_filter_noc2_valid ), + .uart_xbar_noc2_data ( uart_merger_filter_noc2_data ), + .xbar_uart_noc2_ready ( filter_uart_merger_noc2_ready ), // input from noc3 .xbar_uart_noc3_valid ( filter_uart_noc3_valid ), @@ -1075,6 +1083,35 @@ uart_top uart_top ( assign test_start = 1'b1; `endif // endif PITONSYS_UART +int_pkt_gen int_pkt_gen ( + .fpga_clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .noc_out_val ( int_pkt_filter_noc2_valid ), + .noc_out_data ( int_pkt_filter_noc2_data ), + .noc_out_rdy ( filter_int_pkt_noc2_ready ), + .interrupt ( uart_interrupt ), + .chip_id ( {(`NOC_CHIPID_WIDTH){1'b0}} ), + .x_pos ( `NOC_X_WIDTH'd0 ), + .y_pos ( `NOC_Y_WIDTH'd0 ), + .irq_le ( 1'b0 ), //0: level, 1: edge + .device_id ( 7'b1 ) // 32 devices +); + +noc_simple_merger uart_int_pkt_noc_simple_merger ( + .clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .src0_merger_vr_noc_val ( int_pkt_filter_noc2_valid ), + .src0_merger_vr_noc_dat ( int_pkt_filter_noc2_data ), + .src0_merger_vr_noc_rdy ( filter_int_pkt_noc2_ready ), + .src1_merger_vr_noc_val ( uart_merger_filter_noc2_valid ), + .src1_merger_vr_noc_dat ( uart_merger_filter_noc2_data ), + .src1_merger_vr_noc_rdy ( filter_uart_merger_noc2_ready ), + .merger_dst_vr_noc_val ( uart_filter_noc2_valid ), + .merger_dst_vr_noc_dat ( uart_filter_noc2_data ), + .merger_dst_vr_noc_rdy ( filter_uart_noc2_ready ) +); + + // SPI interface `ifdef PITONSYS_SPI `ifdef PITON_FPGA_SD_BOOT diff --git a/piton/design/xilinx/alveou280/devices_ariane.xml b/piton/design/xilinx/alveou280/devices_ariane.xml index e3f99d675..67e4a6948 100644 --- a/piton/design/xilinx/alveou280/devices_ariane.xml +++ b/piton/design/xilinx/alveou280/devices_ariane.xml @@ -45,13 +45,6 @@ Description: Peripheral address map for OpenPiton+Ariane configurations. 0x100000 --> - - - ariane_debug - 0xfff1000000 - 0x1000 - - ariane_bootrom @@ -59,19 +52,5 @@ Description: Peripheral address map for OpenPiton+Ariane configurations. 0x10000 - - - ariane_clint - 0xfff1020000 - 0xc0000 - - - - - ariane_plic - 0xfff1100000 - 0x4000000 - - diff --git a/piton/tools/bin/riscvlib.py b/piton/tools/bin/riscvlib.py index cc20337be..47b678a81 100644 --- a/piton/tools/bin/riscvlib.py +++ b/piton/tools/bin/riscvlib.py @@ -321,8 +321,8 @@ def main(): sysFreq = int(os.environ['CONFIG_SYS_FREQ']) timeStamp = time.strftime("%b %d %Y %H:%M:%S", time.localtime()) - gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) - get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) + gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/16384, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) + get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/16384, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) if __name__ == "__main__": main() diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 37b714ee9..9d7578c48 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -397,8 +397,11 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1d_tag.v" \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_data.v" \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_tag.v" \ + "${DV_ROOT}/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv" \ + "${DV_ROOT}/design/chip/tile/pmesh_rvic_rtl/rvic_wrap.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/polara_bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ @@ -516,7 +519,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ @@ -545,6 +547,18 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/reg_intf_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/top_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/tlul_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_reg_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_top.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/prim_subreg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/prim_subreg_ext.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_gateway.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_reg_top.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_target.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ @@ -807,6 +821,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/uart_reseter.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/fake_boot_ctrl.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ + "${DV_ROOT}/design/chipset/io_ctrl/rtl/int_pkt_gen.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.sv" \ diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 3d101e877..4b9b11300 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -99,7 +99,7 @@ if {[info exists ::env(PITON_PICO_HET)]} { } if {[info exists ::env(PITON_ARIANE)]} { - append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT" + append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT L2_SEND_NC_REQ" } for {set k 0} {$k < $::env(PITON_NUM_TILES)} {incr k} { From 60eeea86f985e92034d5067d6f9fd4dd8dbafd89 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Thu, 14 Dec 2023 09:55:02 -0500 Subject: [PATCH 19/23] [FPGA] Fix plic flist and latch --- .../chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv | 1 + piton/tools/src/proto/common/rtl_setup.tcl | 7 +------ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv b/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv index 88b0b97d5..4c8d3bb40 100644 --- a/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv +++ b/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv @@ -129,6 +129,7 @@ always_comb begin ie_new = '0; ie_we = '0; ie_re_o = '0; + ip_re_o = '0; threshold_new = '0; threshold_we = '0; threshold_re_o = '0; diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 9d7578c48..2b757fd25 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -419,7 +419,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/core/include/instr_tracer_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/include/cvxif_instr_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/acc_dispatcher.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv" \ @@ -444,7 +443,7 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/axi_adapter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/ariane.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ariane.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ @@ -502,10 +501,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ From 86e28fe17a0b1c92c88d0eaf1c20490b35e02f42 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Thu, 4 Jan 2024 03:42:09 -0500 Subject: [PATCH 20/23] [FPGA] Add register to interrupt signals in chip, better timing --- piton/design/chip/rtl/chip.v.pyv | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 4b22ce5f8..1fe676c21 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -352,6 +352,9 @@ module chip( `endif // ifdef PITON_RV64_PLIC `endif // ifdef PITON_RV64_PLATFORM + reg [`PITON_NUM_TILES-1:0] timer_irq_reg_i; + reg [`PITON_NUM_TILES*2-1:0] irq_reg_i; + // Tiles JTAG interface wire jtag_tiles_ucb_val; wire [`UCB_BUS_WIDTH-1:0] jtag_tiles_ucb_data; @@ -1084,11 +1087,11 @@ module chip( ,.unavailable_o ( unavailable[_FLAT_ID_] ) `endif // ifdef PITON_RV64_DEBUGUNIT `ifdef PITON_RV64_CLINT - ,.timer_irq_i ( timer_irq[_FLAT_ID_] ) + ,.timer_irq_i ( timer_irq_reg_i[_FLAT_ID_] ) ,.ipi_i ( ipi[_FLAT_ID_] ) `endif // ifdef PITON_RV64_CLINT `ifdef PITON_RV64_PLIC - ,.irq_i ( irq[_FLAT_ID_*2 +: 2] ) + ,.irq_i ( irq_reg_i[_FLAT_ID_*2 +: 2] ) `endif // ifdef PITON_RV64_PLIC `endif // ifdef PITON_RV64_PLATFORM , @@ -1284,6 +1287,11 @@ pmesh_rvic pmesh_rvic ( .tdo_oe_o ( ) // not used ); +always @(posedge clk_muxed) begin + timer_irq_reg_i <= timer_irq; + irq_reg_i <= irq; +end + endmodule `endif From c9f9948d4cc82b6e39e6ae4fe101e34a757bded5 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Sun, 10 Dec 2023 22:44:05 -0500 Subject: [PATCH 21/23] [FPGA] Update ariane wrapper From 09a758b9fdb0c707e9560ae77e421baef06a1486 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 30 Jul 2024 16:18:05 -0400 Subject: [PATCH 22/23] [FPGA] Fix FPGA timing loop in FLL --- piton/design/chip/fll/rtl/fll_clk_mux.v | 5 ++++- piton/tools/src/proto/common/rtl_setup.tcl | 10 ++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/piton/design/chip/fll/rtl/fll_clk_mux.v b/piton/design/chip/fll/rtl/fll_clk_mux.v index 8e78bee70..c05ff1bb7 100644 --- a/piton/design/chip/fll/rtl/fll_clk_mux.v +++ b/piton/design/chip/fll/rtl/fll_clk_mux.v @@ -5,6 +5,9 @@ module fll_clk_mux ( output clk_muxed ); +`ifdef PITON_FPGA_SYNTH + assign clk_muxed = clk2; +`else assign clk_muxed = clksel ? clk2 : clk1; - +`endif endmodule diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 2b757fd25..6edb6eec1 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -74,9 +74,11 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/common/rtl/noc_simple_merger.v" \ "${DV_ROOT}/design/chip/rtl/OCI.v" \ "${DV_ROOT}/design/chip/rtl/chip.v" \ - "${DV_ROOT}/design/chip/pll/rtl/pll_top.v" \ - "${DV_ROOT}/design/chip/pll/rtl/clk_mux.v" \ - "${DV_ROOT}/design/chip/pll/rtl/clk_se_to_diff.v" \ + "${DV_ROOT}/design/chip/fll/rtl/fll_top.v" \ + "${DV_ROOT}/design/chip/fll/rtl/fll_ctrl.v" \ + "${DV_ROOT}/design/chip/fll/rtl/fll_clk_div.v" \ + "${DV_ROOT}/design/chip/fll/rtl/fll_clk_mux.v" \ + "${DV_ROOT}/design/chip/fll/rtl/gf22_FLL.v" \ "${DV_ROOT}/design/chip/jtag/rtl/jtag.v" \ "${DV_ROOT}/design/chip/jtag/rtl/jtag_interface_tap.v" \ "${DV_ROOT}/design/chip/jtag/rtl/jtag_ucb_transmitter.v" \ @@ -402,7 +404,7 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/polara_bootrom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_dm_pkg.sv" \ From 59d38eba6eaf9de9cd353807818f23653bd31287 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Wed, 14 Aug 2024 11:31:37 -0400 Subject: [PATCH 23/23] Format cleanup --- .../design/chipset/mc/rtl/u280_polara_top.sv | 160 +++++++++--------- piton/design/xilinx/alveou280/constraints.xdc | 1 + .../tools/src/proto/alveou280/polara_fpga.tcl | 2 +- piton/tools/src/proto/common/rtl_setup.tcl | 1 + piton/tools/src/proto/protosyn,2.5 | 15 +- 5 files changed, 82 insertions(+), 97 deletions(-) diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.sv b/piton/design/chipset/mc/rtl/u280_polara_top.sv index 1652b9060..289940e67 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.sv +++ b/piton/design/chipset/mc/rtl/u280_polara_top.sv @@ -1,44 +1,42 @@ - +// Copyright (c) 2024 Polytechnique Montreal `include "mc_define.h" `include "noc_axi4_bridge_define.vh" module u280_polara_top ( - input logic pcie_refclk_clk_n , - input logic pcie_refclk_clk_p , - input logic pcie_perstn , + input logic pcie_refclk_clk_n , + input logic pcie_refclk_clk_p , + input logic pcie_perstn , input logic [15:0] pci_express_x16_rxn , input logic [15:0] pci_express_x16_rxp , output logic [15:0] pci_express_x16_txn , output logic [15:0] pci_express_x16_txp , - input logic resetn , + input logic resetn , - output logic c0_ddr4_act_n, + output logic c0_ddr4_act_n, output logic [16:0] c0_ddr4_adr, - output logic [1:0] c0_ddr4_ba, - output logic [1:0] c0_ddr4_bg, - output logic [0:0] c0_ddr4_ck_c, - output logic [0:0] c0_ddr4_ck_t, - output logic [0:0] c0_ddr4_cke, - output logic [0:0] c0_ddr4_cs_n, - inout wire [71:0] c0_ddr4_dq, - inout wire [17:0] c0_ddr4_dqs_c, - inout wire [17:0] c0_ddr4_dqs_t, - output logic [0:0] c0_ddr4_odt, - output logic c0_ddr4_par, - output logic c0_ddr4_reset_n, - output logic c0_ddr4_ui_clk_sync_rst, + output logic [1:0] c0_ddr4_ba, + output logic [1:0] c0_ddr4_bg, + output logic [0:0] c0_ddr4_ck_c, + output logic [0:0] c0_ddr4_ck_t, + output logic [0:0] c0_ddr4_cke, + output logic [0:0] c0_ddr4_cs_n, + inout wire [71:0] c0_ddr4_dq, + inout wire [17:0] c0_ddr4_dqs_c, + inout wire [17:0] c0_ddr4_dqs_t, + output logic [0:0] c0_ddr4_odt, + output logic c0_ddr4_par, + output logic c0_ddr4_reset_n, + output logic c0_ddr4_ui_clk_sync_rst, // Reference clock - input logic c0_sysclk_clk_n, - input logic c0_sysclk_clk_p, - // input mc_clk , - // input mc_rstn , - output logic chip_rstn , - input logic chipset_clk , - input logic chipset_rstn , - output logic c0_init_calib_complete, + input logic c0_sysclk_clk_n, + input logic c0_sysclk_clk_p, + output logic chip_rstn, + input logic chipset_clk, + input logic chipset_rstn, + output logic c0_init_calib_complete, input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , input logic mem_flit_in_val , @@ -49,18 +47,16 @@ module u280_polara_top ( input logic mem_flit_out_rdy ); - logic mc_rst; logic mc_clk; + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; - logic trans_fifo_val; - logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; - logic trans_fifo_rdy; - - logic fifo_trans_val; - logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; - logic fifo_trans_rdy; + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; logic [`AXI4_ID_WIDTH -1:0] m_axi_awid; logic [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr; @@ -140,10 +136,10 @@ module u280_polara_top ( noc_axi4_bridge noc_axi4_bridge ( - .clk ( mc_clk ), - .rst_n ( ~mc_rst ), - .uart_boot_en ( 1'b0 ), - .phy_init_done ( c0_init_calib_complete ), + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( c0_init_calib_complete), .src_bridge_vr_noc2_val ( fifo_trans_val ), .src_bridge_vr_noc2_dat ( fifo_trans_data ), @@ -232,70 +228,70 @@ module u280_polara_top ( // DDR4 control interface, not used, grounded .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_awvalid .c0_ddr4_s_axi_ctrl_awready( ), // output logic c0_ddr4_s_axi_ctrl_awready - .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_awaddr - .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_wvalid - .c0_ddr4_s_axi_ctrl_wready ( ), // output logic c0_ddr4_s_axi_ctrl_wready - .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_wdata - .c0_ddr4_s_axi_ctrl_bvalid ( ), // output logic c0_ddr4_s_axi_ctrl_bvalid - .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_bready - .c0_ddr4_s_axi_ctrl_bresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output logic c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output logic c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_bresp .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_arvalid .c0_ddr4_s_axi_ctrl_arready( ), // output logic c0_ddr4_s_axi_ctrl_arready - .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_araddr - .c0_ddr4_s_axi_ctrl_rvalid ( ), // output logic c0_ddr4_s_axi_ctrl_rvalid - .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_rready - .c0_ddr4_s_axi_ctrl_rdata ( ), // output logic [31 : 0] c0_ddr4_s_axi_ctrl_rdata - .c0_ddr4_s_axi_ctrl_rresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_rresp + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output logic c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output logic [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_rresp .chip_rstn ( chip_rstn ), // AXI4 Memory Interface - .c0_ddr4_s_axi_awid ( m_axi_awid), // input logic [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awid ( m_axi_awid), // input logic [15 : 0] c0_ddr4_s_axi_awid .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input logic [34 : 0] c0_ddr4_s_axi_awaddr - .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input logic [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input logic [7 : 0] c0_ddr4_s_axi_awlen .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input logic [2 : 0] c0_ddr4_s_axi_awsize - .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input logic [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input logic [1 : 0] c0_ddr4_s_axi_awburst .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input logic [0 : 0] c0_ddr4_s_axi_awlock - .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input logic [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input logic [3 : 0] c0_ddr4_s_axi_awcache .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input logic [2 : 0] c0_ddr4_s_axi_awprot - .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input logic [3 : 0] c0_ddr4_s_axi_awqos - .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input logic c0_ddr4_s_axi_awvalid - .c0_ddr4_s_axi_awready ( m_axi_awready), // output logic c0_ddr4_s_axi_awready - .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input logic [511 : 0] c0_ddr4_s_axi_wdata - .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input logic [63 : 0] c0_ddr4_s_axi_wstrb - .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input logic c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input logic [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input logic c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output logic c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input logic [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input logic [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input logic c0_ddr4_s_axi_wlast .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input logic c0_ddr4_s_axi_wvalid .c0_ddr4_s_axi_wready ( m_axi_wready), // output logic c0_ddr4_s_axi_wready .c0_ddr4_s_axi_bready ( m_axi_bready), // input logic c0_ddr4_s_axi_bready - .c0_ddr4_s_axi_bid ( m_axi_bid), // output logic [15 : 0] c0_ddr4_s_axi_bid - .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output logic [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bid ( m_axi_bid), // output logic [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output logic [1 : 0] c0_ddr4_s_axi_bresp .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output logic c0_ddr4_s_axi_bvalid - .c0_ddr4_s_axi_arid ( m_axi_arid), // input logic [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input logic [15 : 0] c0_ddr4_s_axi_arid .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input logic [34 : 0] c0_ddr4_s_axi_araddr - .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input logic [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input logic [7 : 0] c0_ddr4_s_axi_arlen .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input logic [2 : 0] c0_ddr4_s_axi_arsize - .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input logic [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input logic [1 : 0] c0_ddr4_s_axi_arburst .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input logic [0 : 0] c0_ddr4_s_axi_arlock - .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input logic [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input logic [3 : 0] c0_ddr4_s_axi_arcache .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input logic [2 : 0] c0_ddr4_s_axi_arprot - .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input logic [3 : 0] c0_ddr4_s_axi_arqos - .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input logic c0_ddr4_s_axi_arvalid - .c0_ddr4_s_axi_arready ( m_axi_arready), // output logic c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input logic [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input logic c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output logic c0_ddr4_s_axi_arready .c0_ddr4_s_axi_rready ( m_axi_rready), // input logic c0_ddr4_s_axi_rready - .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output logic c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output logic c0_ddr4_s_axi_rlast .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output logic c0_ddr4_s_axi_rvalid - .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output logic [1 : 0] c0_ddr4_s_axi_rresp - .c0_ddr4_s_axi_rid ( m_axi_rid), // output logic [15 : 0] c0_ddr4_s_axi_rid - .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output logic [511 : 0] c0_ddr4_s_axi_rdata + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output logic [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output logic [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output logic [511 : 0] c0_ddr4_s_axi_rdata // PCIe - .pci_express_x16_rxn(pci_express_x16_rxn), - .pci_express_x16_rxp(pci_express_x16_rxp), - .pci_express_x16_txn(pci_express_x16_txn), - .pci_express_x16_txp(pci_express_x16_txp), - .pcie_perstn(pcie_perstn), - .pcie_refclk_clk_n(pcie_refclk_clk_n), - .pcie_refclk_clk_p(pcie_refclk_clk_p), - .resetn(resetn) + .pci_express_x16_rxn (pci_express_x16_rxn), + .pci_express_x16_rxp (pci_express_x16_rxp), + .pci_express_x16_txn (pci_express_x16_txn), + .pci_express_x16_txp (pci_express_x16_txp), + .pcie_perstn (pcie_perstn), + .pcie_refclk_clk_n (pcie_refclk_clk_n), + .pcie_refclk_clk_p (pcie_refclk_clk_p), + .resetn (resetn) ); endmodule diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index 19e29b9f3..1a3526ab5 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -1,3 +1,4 @@ +# Copyright (c) 2024 Polytechnique Montreal # Bitstream generation # --------------------------------------------------------------------- set_property CONFIG_VOLTAGE 1.8 [current_design] diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl index 06b41694d..1c5a746df 100644 --- a/piton/tools/src/proto/alveou280/polara_fpga.tcl +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -1,4 +1,4 @@ - +# Copyright (c) 2024 Polytechnique Montreal ################################################################ # This is a generated script based on design: polara_fpga # diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 6edb6eec1..245665e26 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -1,4 +1,5 @@ # Copyright (c) 2016 Princeton University +# Copyright (c) 2024 Polytechnique Montreal # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 2fd0e35b2..ea542b4a9 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -75,7 +75,6 @@ def usage(): print(" pico (32bit RISCV core)", file=sys.stderr) print(" pico_het (heterogeneous pico+sparc arrangement)", file=sys.stderr) print(" ariane (64bit RISCV core)", file=sys.stderr) - print(" ara (64bit RISCV vec core)", file=sys.stderr) print("\n --network_config ", file=sys.stderr) print(" Name of the network type to be used:", file=sys.stderr) print(" 2dmesh_config (default)", file=sys.stderr) @@ -492,7 +491,7 @@ def makeDefList(options): #defines.append(df) # disable CSM in this case - if (options.core == 'ariane') or (options.core == 'ara'): + if (options.core == 'ariane'): defines.append("NO_RTL_CSM") if (options.board == "f1"): @@ -777,15 +776,6 @@ def main(): os.environ['RTL_SPARC' + str(i)] = "1" print_info('setenv RTL_SPARC' + str(i)) - elif options.core == 'ara': - os.environ['PITON_ARA'] = "1" - os.environ['PITON_RV64_PLATFORM'] = "1" - os.environ['WT_DCACHE'] = "1" - - for i in range(int(options.num_tiles)): - os.environ['RTL_ARA' + str(i)] = "1" - print_info('setenv RTL_ARA' + str(i)) - else: print_error("invalid core configuration " + str(options.core)) sys.exit(1) @@ -859,9 +849,6 @@ def main(): if options.core == 'ariane': config += ' -ariane' - - if options.core == 'ara': - config += ' -ara' print_info("Synthesizing a test: %s" % options.test_name) print_info("Compilation started")