From 2bf40173fd8c1a107a09ffa9129cc733a9486b9f Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 7 Aug 2023 10:09:41 -0400 Subject: [PATCH 001/144] Adding Ara RTL to FPGA Protosyn flow --- piton/tools/src/proto/common/rtl_setup.tcl | 142 ++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 7bcf1d82d..ab99f7f41 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,8 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include" + # RTL include files set GLOBAL_INCLUDE_FILES [list \ @@ -541,6 +542,144 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axilite.sv " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/strb2mask.v" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/axilite_noc_bridge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axi.sv " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/axi_noc_bridge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ara_verilog_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/accel_dispatcher_ideal.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_dispatcher.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_sequencer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_soc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_system.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_inval_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_to_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ctrl_registers.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/cva6_accel_first_pass_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/fixed_p_rounding.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queues_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_alu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/valu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vmfpu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/lane_sequencer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_div.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_fus_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/lane.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_requester.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_mul.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/masku/masku.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/addrgen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vldu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vlsu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vstu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_detect.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/fifo_v3.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator_tx.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_omega_net.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/delta_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_to_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/clock_divider_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/fifo_v2.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/prioarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/pulp_sync.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/rrarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/clock_divider.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_fifo.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/fifo_v1.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/find_first_one.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/pulp_sync_wedge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_fifo_adv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/isochronous_spill_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sub_per_hash.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fifo.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/fall_through_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/exp_backoff.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rstgen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_decode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lzc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_fifo_gray.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/id_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cb_filter_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/serial_deglitch.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_arbiter_flushable.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/onehot_to_bin.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/clk_div.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fork.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_delay.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rr_arb_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/max_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_arbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/addr_decode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator_rx.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/binary_to_gray.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/spill_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cb_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/spill_register_flushable.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_fifo_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_encode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/plru_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/shift_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr_16bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fork_dynamic.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/unread.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/popcount.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sync.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rstgen_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sync_wedge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/gray_to_binary.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/mv_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_to_axi.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_src.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_modify_address.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_downsizer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_err_slv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_to_axi_lite.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_serializer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_converter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cut.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_upsizer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_atop_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_burst_splitter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_delayer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_regs.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_to_apb.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_isolate.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_multicut.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_sim_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_id_prepend.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mailbox.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_dst.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mux.sv" \ ] set CHIP_INCLUDE_FILES [list \ @@ -655,6 +794,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ From 407ebb0cde87072794dbde285ee4cf8b676a9138 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 7 Aug 2023 10:12:10 -0400 Subject: [PATCH 002/144] Adding Alveo U280 board to FPGA Protosyn flow --- piton/design/chipset/mc/rtl/u280_polara_top.v | 247 ++++++++++++ .../chipset/xilinx/alveou280/.gitignore | 2 + piton/design/xilinx/alveou280/constraints.xdc | 269 +++++++++++++ piton/design/xilinx/alveou280/devices.xml | 57 +++ .../xilinx/alveou280/devices_ariane.xml | 77 ++++ piton/tools/src/proto/alveou280/board.tcl | 45 +++ piton/tools/src/proto/alveou280/polara.tcl | 364 ++++++++++++++++++ piton/tools/src/proto/block.list | 2 +- piton/tools/src/proto/board.list | 1 + piton/tools/src/proto/protosyn,2.5 | 18 +- 10 files changed, 1079 insertions(+), 3 deletions(-) create mode 100644 piton/design/chipset/mc/rtl/u280_polara_top.v create mode 100644 piton/design/chipset/xilinx/alveou280/.gitignore create mode 100644 piton/design/xilinx/alveou280/constraints.xdc create mode 100644 piton/design/xilinx/alveou280/devices.xml create mode 100644 piton/design/xilinx/alveou280/devices_ariane.xml create mode 100644 piton/tools/src/proto/alveou280/board.tcl create mode 100644 piton/tools/src/proto/alveou280/polara.tcl diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v new file mode 100644 index 000000000..f0dc03286 --- /dev/null +++ b/piton/design/chipset/mc/rtl/u280_polara_top.v @@ -0,0 +1,247 @@ + +`include "mc_define.h" + +module u280_polara_top ( + + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + + output c0_ddr4_act_n, + output [16:0] c0_ddr4_adr, + output [1:0] c0_ddr4_ba, + output [1:0] c0_ddr4_bg, + output [0:0] c0_ddr4_ck_c, + output [0:0] c0_ddr4_ck_t, + output [0:0] c0_ddr4_cke, + output [0:0] c0_ddr4_cs_n, + inout [71:0] c0_ddr4_dq, + inout [17:0] c0_ddr4_dqs_c, + inout [17:0] c0_ddr4_dqs_t, + output [0:0] c0_ddr4_odt, + output c0_ddr4_par, + output c0_ddr4_reset_n, + output c0_ddr4_ui_clk_sync_rst, + // Reference clock + input c0_sysclk_clk_n, + input c0_sysclk_clk_p, + // input mc_clk , + // input mc_rstn , + output chip_rstn , + input chipset_clk , + output chipset_rstn , + output c0_init_calib_complete, + + input [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input mem_flit_in_val , + output mem_flit_in_rdy , + + output [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output mem_flit_out_val , + input mem_flit_out_rdy +); + + + wire trans_fifo_val; + wire [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + wire trans_fifo_rdy; + + wire fifo_trans_val; + wire [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + wire fifo_trans_rdy; + + + noc_bidir_afifo mig_afifo ( + .clk_1 ( chipset_clk ), + .rst_1 ( ~chipset_rstn ), + + .clk_2 ( mc_clk ), + .rst_2 ( mc_rst ), + + // CPU --> MIG + .flit_in_val_1 ( mem_flit_in_val ), + .flit_in_data_1 ( mem_flit_in_data ), + .flit_in_rdy_1 ( mem_flit_in_rdy ), + + .flit_out_val_2 ( fifo_trans_val ), + .flit_out_data_2 ( fifo_trans_data ), + .flit_out_rdy_2 ( fifo_trans_rdy ), + + // MIG --> CPU + .flit_in_val_2 ( trans_fifo_val ), + .flit_in_data_2 ( trans_fifo_data ), + .flit_in_rdy_2 ( trans_fifo_rdy ), + + .flit_out_val_1 ( mem_flit_out_val ), + .flit_out_data_1 ( mem_flit_out_data ), + .flit_out_rdy_1 ( mem_flit_out_rdy ) + ); + + + noc_axi4_bridge noc_axi4_bridge ( + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( init_calib_complete ), + + .src_bridge_vr_noc2_val ( fifo_trans_val ), + .src_bridge_vr_noc2_dat ( fifo_trans_data ), + .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), + + .bridge_dst_vr_noc3_val ( trans_fifo_val ), + .bridge_dst_vr_noc3_dat ( trans_fifo_data ), + .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + + .m_axi_wid ( m_axi_wid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_buser ( m_axi_buser ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + + .m_axi_rid ( m_axi_rid), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + + ); + + polara polara_i ( + + .c0_sysclk_clk_p ( c0_sysclk_clk_p ), + .c0_sysclk_clk_n ( c0_sysclk_clk_n ), + .c0_ddr4_ui_clk ( mc_clk ), + .c0_ddr4_ui_clk_sync_rst ( mc_rst ), + .c0_init_calib_complete ( init_calib_complete ), + + + // DDR4 physicall interface + .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_par ( c0_ddr4_par ), // output wire c0_ddr4_parity + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + + // DDR4 control interface, not used, grounded + .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_awvalid + .c0_ddr4_s_axi_ctrl_awready( ), // output wire c0_ddr4_s_axi_ctrl_awready + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output wire c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output wire c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_arvalid + .c0_ddr4_s_axi_ctrl_arready( ), // output wire c0_ddr4_s_axi_ctrl_arready + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output wire c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output wire [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_rresp + + .chip_rstn ( chip_rstn ), + + // AXI4 Memory Interface + .c0_ddr4_s_axi_awid ( m_axi_awid), // input wire [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input wire [34 : 0] c0_ddr4_s_axi_awaddr + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input wire [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input wire [2 : 0] c0_ddr4_s_axi_awsize + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input wire [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input wire [0 : 0] c0_ddr4_s_axi_awlock + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input wire [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input wire [2 : 0] c0_ddr4_s_axi_awprot + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input wire [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input wire c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output wire c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input wire [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input wire [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input wire c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input wire c0_ddr4_s_axi_wvalid + .c0_ddr4_s_axi_wready ( m_axi_wready), // output wire c0_ddr4_s_axi_wready + .c0_ddr4_s_axi_bready ( m_axi_bready), // input wire c0_ddr4_s_axi_bready + .c0_ddr4_s_axi_bid ( m_axi_bid), // output wire [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output wire [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output wire c0_ddr4_s_axi_bvalid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input wire [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input wire [34 : 0] c0_ddr4_s_axi_araddr + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input wire [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input wire [2 : 0] c0_ddr4_s_axi_arsize + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input wire [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input wire [0 : 0] c0_ddr4_s_axi_arlock + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input wire [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input wire [2 : 0] c0_ddr4_s_axi_arprot + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input wire [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input wire c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output wire c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_rready ( m_axi_rready), // input wire c0_ddr4_s_axi_rready + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output wire c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output wire c0_ddr4_s_axi_rvalid + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output wire [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output wire [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output wire [511 : 0] c0_ddr4_s_axi_rdata + + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn) + ); + +endmodule diff --git a/piton/design/chipset/xilinx/alveou280/.gitignore b/piton/design/chipset/xilinx/alveou280/.gitignore new file mode 100644 index 000000000..9f9934c3f --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/.gitignore @@ -0,0 +1,2 @@ +!ip_cores +polara_fpga \ No newline at end of file diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc new file mode 100644 index 000000000..02f6d81e5 --- /dev/null +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -0,0 +1,269 @@ +# Bitstream generation +# --------------------------------------------------------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] ;# Choices are pullnone, pulldown, and pullup. +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# --------------------------------------------------------------------- + + +# 156.25MHz General purpose system clock +set_property PACKAGE_PIN F30 [get_ports {chipset_clk_osc_n}] +set_property PACKAGE_PIN G30 [get_ports {chipset_clk_osc_p}] +set_property IOSTANDARD LVDS [get_ports {chipset_clk*}] + +# Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller +set_property PACKAGE_PIN L30 [get_ports resetn] +set_property IOSTANDARD LVCMOS18 [get_ports resetn] + +# UART +set_property PACKAGE_PIN A28 [get_ports uart_rx] +set_property PACKAGE_PIN B33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_*] + +# PCIe MGTY Interface +set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 + +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]} ] ;# Bank 224 - MGTYRXN0_224 +set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]} ] ;# Bank 224 - MGTYRXN1_224 +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]} ] ;# Bank 224 - MGTYRXN2_224 +set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]} ] ;# Bank 224 - MGTYRXN3_224 +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]} ] ;# Bank 224 - MGTYRXP0_224 +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]} ] ;# Bank 224 - MGTYRXP1_224 +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]} ] ;# Bank 224 - MGTYRXP2_224 +set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]} ] ;# Bank 224 - MGTYRXP3_224 +set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]} ] ;# Bank 224 - MGTYTXN0_224 +set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]} ] ;# Bank 224 - MGTYTXN1_224 +set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]} ] ;# Bank 224 - MGTYTXN2_224 +set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]} ] ;# Bank 224 - MGTYTXN3_224 +set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]} ] ;# Bank 224 - MGTYTXP0_224 +set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]} ] ;# Bank 224 - MGTYTXP1_224 +set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]} ] ;# Bank 224 - MGTYTXP2_224 +set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]} ] ;# Bank 224 - MGTYTXP3_224 +# Clock +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n ] ;# Bank 225 - MGTREFCLK0N_225 +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p ] ;# Bank 225 - MGTREFCLK0P_225 + +set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]} ] ;# Bank 225 - MGTYRXN0_225 +set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]} ] ;# Bank 225 - MGTYRXN1_225 +set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]} ] ;# Bank 225 - MGTYRXN2_225 +set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]} ] ;# Bank 225 - MGTYRXN3_225 +set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]} ] ;# Bank 225 - MGTYRXP0_225 +set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]} ] ;# Bank 225 - MGTYRXP1_225 +set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]} ] ;# Bank 225 - MGTYRXP2_225 +set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]} ] ;# Bank 225 - MGTYRXP3_225 +set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]} ] ;# Bank 225 - MGTYTXN0_225 +set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]} ] ;# Bank 225 - MGTYTXN1_225 +set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]} ] ;# Bank 225 - MGTYTXN2_225 +set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 +set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 +set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP2_225 +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP3_225 +set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]} ] ;# Bank 226 - MGTYRXN0_226 +set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]} ] ;# Bank 226 - MGTYRXN1_226 +set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]} ] ;# Bank 226 - MGTYRXN2_226 +set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]} ] ;# Bank 226 - MGTYRXN3_226 +set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]} ] ;# Bank 226 - MGTYRXP0_226 +set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]} ] ;# Bank 226 - MGTYRXP1_226 +set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]} ] ;# Bank 226 - MGTYRXP2_226 +set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]} ] ;# Bank 226 - MGTYRXP3_226 +set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]} ] ;# Bank 226 - MGTYTXN0_226 +set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]} ] ;# Bank 226 - MGTYTXN1_226 +set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]} ] ;# Bank 226 - MGTYTXN2_226 +set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]} ] ;# Bank 226 - MGTYTXN3_226 +set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]} ] ;# Bank 226 - MGTYTXP0_226 +set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]} ] ;# Bank 226 - MGTYTXP1_226 +set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]} ] ;# Bank 226 - MGTYTXP2_226 +set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]} ] ;# Bank 226 - MGTYTXP3_226 +#set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 +set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]} ] ;# Bank 227 - MGTYRXN0_227 +set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]} ] ;# Bank 227 - MGTYRXN1_227 +set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]} ] ;# Bank 227 - MGTYRXN2_227 +set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]} ] ;# Bank 227 - MGTYRXN3_227 +set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]} ] ;# Bank 227 - MGTYRXP0_227 +set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]} ] ;# Bank 227 - MGTYRXP1_227 +set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]} ] ;# Bank 227 - MGTYRXP2_227 +set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]} ] ;# Bank 227 - MGTYRXP3_227 +set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]} ] ;# Bank 227 - MGTYTXN0_227 +set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]} ] ;# Bank 227 - MGTYTXN1_227 +set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]} ] ;# Bank 227 - MGTYTXN2_227 +set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]} ] ;# Bank 227 - MGTYTXN3_227 +set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]} ] ;# Bank 227 - MGTYTXP0_227 +set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]} ] ;# Bank 227 - MGTYTXP1_227 +set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]} ] ;# Bank 227 - MGTYTXP2_227 +set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]} ] ;# Bank 227 - MGTYTXP3_227 + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] + +# 100MHz DDR0 System clock +set_property PACKAGE_PIN BJ44 [get_ports {mc_clk_n}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property PACKAGE_PIN BJ43 [get_ports {mc_clk_p}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 + + +# DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank +# <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# +set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[16]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 +set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +#set_property -dict {PACKAGE_PIN BE46 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property -dict {PACKAGE_PIN BK44 IOSTANDARD SSTL12_DCI} [ get_ports {#NA} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cs_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[13]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +#set_property -dict {PACKAGE_PIN BL47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 +set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_odt[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +#set_property -dict {PACKAGE_PIN BE45 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property -dict {PACKAGE_PIN BD42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[10]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property -dict {PACKAGE_PIN BK41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property -dict {PACKAGE_PIN BJ41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_parity} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 +set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[4]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[3]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[8]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[7]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[11]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[9]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[5]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 +set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[6]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +#set_property -dict {PACKAGE_PIN BJ42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[12]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_act_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 +set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cke[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 +set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[66]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[67]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[64]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[65]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[71]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[70]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[68]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 +set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[69]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 +set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[34]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[35]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property -dict {PACKAGE_PIN BK29 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[33]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[32]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[38]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 +set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[39]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 +set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[37]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 +set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[36]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 +set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[25]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 +set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[24]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 +set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 +set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 +set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [ get_ports {ddr_reset_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 +set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[27]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[26]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 +set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[29]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 +set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[28]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 +set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[30]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 +set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[31]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 +set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 +set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 +set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[17]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 +set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[16]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 +set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 +set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 +set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[19]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 +set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[18]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 +set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[21]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 +set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[20]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 +set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[23]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 +set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[22]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 +set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 +set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 +set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[58]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[57]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[59]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[56]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[61]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[60]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[63]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[62]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 +set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 +set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[40]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[41]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 +set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[42]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[43]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[47]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[46]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[44]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[45]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - L21_T3L_N4_AD8 P_66 +set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[49]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[50]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 +set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[48]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[51]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[52]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[55]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[53]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[54]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 +set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 +set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 +set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 +set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 +set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 +set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 +set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 +set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 +set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 +set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 +set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 +set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[9]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 +set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[8]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 +set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 +set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[10]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[11]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 +set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[12]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 +set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[13]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 +set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[14]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 +set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[15]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 +set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 +set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 + +set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] +set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] \ No newline at end of file diff --git a/piton/design/xilinx/alveou280/devices.xml b/piton/design/xilinx/alveou280/devices.xml new file mode 100644 index 000000000..8162e9c91 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices.xml @@ -0,0 +1,57 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + net + 0xfff0d00000 + 0x100000 + + diff --git a/piton/design/xilinx/alveou280/devices_ariane.xml b/piton/design/xilinx/alveou280/devices_ariane.xml new file mode 100644 index 000000000..e3f99d675 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices_ariane.xml @@ -0,0 +1,77 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x200000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + diff --git a/piton/tools/src/proto/alveou280/board.tcl b/piton/tools/src/proto/alveou280/board.tcl new file mode 100644 index 000000000..e479b8b76 --- /dev/null +++ b/piton/tools/src/proto/alveou280/board.tcl @@ -0,0 +1,45 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "" +set FPGA_PART "xcu280-fsvh2892-2l-e" +set VIVADO_FLOW_PERF_OPT 0 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" + + +# Create a block design containing PCIe and GPIO using the FPGA_PART variable +# It will produce the "meep_shell.bd" file + +source $DV_ROOT/tools/src/proto/${BOARD}/polara.tcl + +# Grab the file from where the above tcl script has placed it +set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/alveou280/polara_fpga/polara_fpga] + + diff --git a/piton/tools/src/proto/alveou280/polara.tcl b/piton/tools/src/proto/alveou280/polara.tcl new file mode 100644 index 000000000..274132d03 --- /dev/null +++ b/piton/tools/src/proto/alveou280/polara.tcl @@ -0,0 +1,364 @@ + +################################################################ +# This is a generated script based on design: polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./tmp_proj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT)1 + +set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2l-e + set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] +} + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 +current_bd_design $design_name + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create interface ports + set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {156250000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $c0_sysclk + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi_ctrl} \ + ] $c0_ddr4_ui_clk + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $resetn + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: axi_xbar_pcie, and set properties + set axi_xbar_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar_pcie ] + set_property -dict [ list \ + CONFIG.M00_HAS_REGSLICE {4} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.S00_HAS_REGSLICE {4} \ + CONFIG.S01_HAS_REGSLICE {4} \ + ] $axi_xbar_pcie + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0.CKE_WIDTH {2} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {11} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {7} \ + CONFIG.C0.DDR4_CasLatency {10} \ + CONFIG.C0.DDR4_CasWriteLatency {9} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod {10044} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PDZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_Specify_MandD {false} \ + CONFIG.C0.DDR4_TimePeriod {1598} \ + CONFIG.C0.ODT_WIDTH {2} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.MAILBOX_ENABLE {true} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.coreclk_freq {250} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.flr_enable {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf0_device_id {902F} \ + CONFIG.pf1_bar0_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar0_prefetchable_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_device_id {922F} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar0_prefetchable_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_device_id {932F} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.testname {mm} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_xbar_pcie/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net c0_ddr4_s_axi_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins axi_xbar_pcie/S01_AXI] + connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins axi_xbar_pcie/S00_AXI] [get_bd_intf_pins qdma_0/M_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net ARESETN_1 [get_bd_pins axi_xbar_pcie/ARESETN] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] + connect_bd_net -net M00_ARESETN_1 [get_bd_pins axi_xbar_pcie/M00_ARESETN] [get_bd_pins axi_xbar_pcie/S01_ARESETN] [get_bd_pins rst_ea_CLK0/peripheral_aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins axi_xbar_pcie/ACLK] [get_bd_pins axi_xbar_pcie/M00_ACLK] [get_bd_pins axi_xbar_pcie/S01_ACLK] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net proc_sys_rst_pcie_peripheral_aresetn [get_bd_pins axi_xbar_pcie/S00_ARESETN] [get_bd_pins proc_sys_rst_pcie/peripheral_aresetn] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_xbar_pcie/S00_ACLK] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + + + + # ########################################################### + # Final changes. Use this block to customize the bd + + # Decrease the PCIe speed for better timing results + + # ########################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 04a332390..3387c9e73 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,100,16384 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/board.list b/piton/tools/src/proto/board.list index 6149781e9..d51b4ffed 100644 --- a/piton/tools/src/proto/board.list +++ b/piton/tools/src/proto/board.list @@ -30,3 +30,4 @@ nexysVideo vivado f1 vivado vcu118 vivado xupp3r vivado +alveou280 vivado diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 376e7143f..d0326f536 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -64,6 +64,7 @@ def usage(): print(" genesys2", file=sys.stderr) print(" nexysVideo", file=sys.stderr) print(" f1", file=sys.stderr) + print(" alveou280", file=sys.stderr) print("\n -d, --design ", file=sys.stderr) print(" Name of design module to synthesize. The default is 'system', which", file=sys.stderr) print(" synthesizes a full system with chip and chipset. See", file=sys.stderr) @@ -74,6 +75,7 @@ def usage(): print(" pico (32bit RISCV core)", file=sys.stderr) print(" pico_het (heterogeneous pico+sparc arrangement)", file=sys.stderr) print(" ariane (64bit RISCV core)", file=sys.stderr) + print(" ara (64bit RISCV vec core)", file=sys.stderr) print("\n --network_config ", file=sys.stderr) print(" Name of the network type to be used:", file=sys.stderr) print(" 2dmesh_config (default)", file=sys.stderr) @@ -490,7 +492,7 @@ def makeDefList(options): #defines.append(df) # disable CSM in this case - if options.core == 'ariane': + if (options.core == 'ariane') or (options.core == 'ara'): defines.append("NO_RTL_CSM") if (options.board == "f1"): @@ -514,7 +516,7 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1"}): + if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1", "alveou280"}): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") @@ -772,6 +774,15 @@ def main(): os.environ['RTL_SPARC' + str(i)] = "1" print_info('setenv RTL_SPARC' + str(i)) + elif options.core == 'ara': + os.environ['PITON_ARA'] = "1" + os.environ['PITON_RV64_PLATFORM'] = "1" + os.environ['WT_DCACHE'] = "1" + + for i in range(int(options.num_tiles)): + os.environ['RTL_ARA' + str(i)] = "1" + print_info('setenv RTL_ARA' + str(i)) + else: print_error("invalid core configuration " + str(options.core)) sys.exit(1) @@ -845,6 +856,9 @@ def main(): if options.core == 'ariane': config += ' -ariane' + + if options.core == 'ara': + config += ' -ara' print_info("Synthesizing a test: %s" % options.test_name) print_info("Compilation started") From 9d3e173424bd2e67352a894343497ef497b36333 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:04:09 -0400 Subject: [PATCH 003/144] Include BD in Protosyn flow --- piton/tools/src/proto/common/setup.tcl | 7 ++++++- piton/tools/src/proto/vivado/setup.tcl | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 3a2f15efa..3d101e877 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -62,6 +62,11 @@ foreach ip_file ${ALL_IP_FILE_PREFIXES} { lappend ALL_XCO_IP_FILES "${ip_file}.xco" } +set ALL_BD_FILES [list ] +foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" +} + set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] set ALL_PRJ_IP_FILES [concat ${DESIGN_PRJ_IP_FILES}] @@ -94,7 +99,7 @@ if {[info exists ::env(PITON_PICO_HET)]} { } if {[info exists ::env(PITON_ARIANE)]} { - append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE" + append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT" } for {set k 0} {$k < $::env(PITON_NUM_TILES)} {incr k} { diff --git a/piton/tools/src/proto/vivado/setup.tcl b/piton/tools/src/proto/vivado/setup.tcl index b63e811ae..c5a724e40 100644 --- a/piton/tools/src/proto/vivado/setup.tcl +++ b/piton/tools/src/proto/vivado/setup.tcl @@ -34,4 +34,5 @@ set ALL_FILES [concat \ $ALL_COE_FILES \ $ALL_PRJ_IP_FILES \ $ALL_XCI_IP_FILES \ + $ALL_BD_FILES \ ] From 0fbb74bafd0aacdad1f12afe1e2ece139ebb52e9 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:08:21 -0400 Subject: [PATCH 004/144] Update Polara BD for Protosyn --- piton/design/chipset/mc/rtl/u280_polara_top.v | 2 +- piton/tools/src/proto/alveou280/board.tcl | 4 +- .../tools/src/proto/alveou280/polara_fpga.tcl | 364 ++++++++++++++++++ piton/tools/src/proto/common/rtl_setup.tcl | 2 + 4 files changed, 369 insertions(+), 3 deletions(-) create mode 100644 piton/tools/src/proto/alveou280/polara_fpga.tcl diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v index f0dc03286..c5e3bc0b0 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.v +++ b/piton/design/chipset/mc/rtl/u280_polara_top.v @@ -149,7 +149,7 @@ module u280_polara_top ( ); - polara polara_i ( + polara_fpga polara_i ( .c0_sysclk_clk_p ( c0_sysclk_clk_p ), .c0_sysclk_clk_n ( c0_sysclk_clk_n ), diff --git a/piton/tools/src/proto/alveou280/board.tcl b/piton/tools/src/proto/alveou280/board.tcl index e479b8b76..ca739787f 100644 --- a/piton/tools/src/proto/alveou280/board.tcl +++ b/piton/tools/src/proto/alveou280/board.tcl @@ -35,9 +35,9 @@ set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" # Create a block design containing PCIe and GPIO using the FPGA_PART variable -# It will produce the "meep_shell.bd" file +# It will produce the "polara_fpga.bd" file -source $DV_ROOT/tools/src/proto/${BOARD}/polara.tcl +source $DV_ROOT/tools/src/proto/${BOARD}/polara_fpga.tcl # Grab the file from where the above tcl script has placed it set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/alveou280/polara_fpga/polara_fpga] diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl new file mode 100644 index 000000000..f5debf750 --- /dev/null +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -0,0 +1,364 @@ + +################################################################ +# This is a generated script based on design: polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./tmp_proj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT)1 + +set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2L-e + set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] +} + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 +current_bd_design $design_name + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create interface ports + set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $c0_sysclk + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi:c0_ddr4_s_axi_ctrl} \ + ] $c0_ddr4_ui_clk + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $resetn + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.CKE_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {1} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiNarrowBurst.VALUE_SRC {USER} \ + CONFIG.C0.DDR4_AxiIDWidth.VALUE_SRC {USER} \ + CONFIG.C0.DDR4_AxiIDWidth {7} \ + CONFIG.C0.DDR4_AxiNarrowBurst {true} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {15} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataMask {NONE} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_Specify_MandD {false} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.ODT_WIDTH {1} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.MAILBOX_ENABLE {true} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.coreclk_freq {250} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.flr_enable {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf0_device_id {902F} \ + CONFIG.pf1_bar0_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar0_prefetchable_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_device_id {922F} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar0_prefetchable_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_device_id {932F} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.testname {mm} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + ] $smartconnect_0 + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins qdma_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + + # Create port connections + connect_bd_net -net ARESETN_1 [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] [get_bd_pins smartconnect_0/aclk1] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + + + + # ########################################################### + # Final changes. Use this block to customize the bd + + # Decrease the PCIe speed for better timing results + + # ########################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index ab99f7f41..58676a147 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -70,6 +70,8 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/common/rtl/bram_1rw_wrapper.v" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ "${DV_ROOT}/design/common/rtl/synchronizer.v" \ + "${DV_ROOT}/design/common/rtl/noc_simple_splitter.v" \ + "${DV_ROOT}/design/common/rtl/noc_simple_merger.v" \ "${DV_ROOT}/design/chip/rtl/OCI.v" \ "${DV_ROOT}/design/chip/rtl/chip.v" \ "${DV_ROOT}/design/chip/pll/rtl/pll_top.v" \ From 5d50d096c87bcb4cefcd2f59061ca26d11ce147e Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:13:35 -0400 Subject: [PATCH 005/144] Add Alveo U280 config options and IPs --- piton/design/chipset/include/mc_define.h | 19 + .../ip_cores/uart_16550/uart_16550.xci | 142 +++ piton/design/chipset/rtl/chipset.v | 44 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 70 +- .../afifo_w64_d128_std/afifo_w64_d128_std.xci | 582 +++++++++++++ .../alveou280/ip_cores/clk_mmcm/clk_mmcm.xci | 823 ++++++++++++++++++ piton/design/include/piton_system.vh | 15 + piton/design/rtl/system.v | 49 +- piton/tools/src/proto/fpga_lib.py | 15 +- piton/tools/src/proto/protosyn,2.5 | 5 +- 10 files changed, 1746 insertions(+), 18 deletions(-) create mode 100644 piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci create mode 100644 piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci create mode 100644 piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci diff --git a/piton/design/chipset/include/mc_define.h b/piton/design/chipset/include/mc_define.h index 133877099..15edf8ef5 100644 --- a/piton/design/chipset/include/mc_define.h +++ b/piton/design/chipset/include/mc_define.h @@ -105,6 +105,25 @@ `define DDR3_CS_WIDTH 2 `define DDR3_BG_WIDTH 2 `define DDR3_ODT_WIDTH 2 +`elsif ALVEO_BOARD + `define BOARD_MEM_SIZE_MB 8192 + `define WORDS_PER_BURST 8 + `define WORD_SIZE 8 // in bytes + `define MIG_APP_ADDR_WIDTH 32 + `define MIG_APP_CMD_WIDTH 3 + `define MIG_APP_DATA_WIDTH 512 + `define MIG_APP_MASK_WIDTH 64 + + `define DDR3_DQ_WIDTH 72 + `define DDR3_DQS_WIDTH 18 + `define DDR3_ADDR_WIDTH 17 + `define DDR3_BA_WIDTH 2 + `define DDR3_DM_WIDTH 0 + `define DDR3_CK_WIDTH 1 + `define DDR3_CKE_WIDTH 1 + `define DDR3_CS_WIDTH 1 + `define DDR3_BG_WIDTH 2 + `define DDR3_ODT_WIDTH 1 `elsif NEXYS4DDR_BOARD `define BOARD_MEM_SIZE_MB 256 `define WORDS_PER_BURST 8 diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci new file mode 100644 index 000000000..8c27abbec --- /dev/null +++ b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci @@ -0,0 +1,142 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_16550 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 25000000 + virtexuplushbm + 0 + 0 + 1 + VERSAL_AI_CORE_ES1 + 100000000 + 1 + 25000000 + 25 + 0 + 0 + 16550 + 100000000 + 100 + 1 + 1 + uart_16550 + Custom + false + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 26 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index fdbfddf60..55a881f64 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -88,7 +88,16 @@ module chipset( `ifdef F1_BOARD input sys_clk, -`else +`elsif ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , // Oscillator clock `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK @@ -244,11 +253,11 @@ module chipset( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -462,13 +471,13 @@ module chipset( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, - `elsif XUPP3R_BOARD + `elsif XUPP3R_OR_ALVEO // no switches :( `else input [7:0] sw, `endif - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO output [3:0] leds `else output [7:0] leds @@ -755,7 +764,7 @@ end `ifdef VCU118_BOARD assign uart_boot_en = sw[0]; assign uart_timeout_en = sw[1]; - `elsif XUPP3R_BOARD + `elsif XUPP3R_OR_ALVEO assign uart_boot_en = 1'b1; assign uart_timeout_en = 1'b0; `else @@ -813,6 +822,11 @@ end assign leds[1] = init_calib_complete; assign leds[2] = processor_offchip_noc2_valid; assign leds[3] = offchip_processor_noc3_valid; +`elsif ALVEO_BOARD + assign leds[0] = 1'b1; + assign leds[1] = init_calib_complete; + assign leds[2] = processor_offchip_noc2_valid; + assign leds[3] = offchip_processor_noc3_valid; `else // PITON_BOARD assign leds[0] = clk_locked; assign leds[1] = ~piton_ready_n; @@ -1307,11 +1321,11 @@ chipset_impl_noc_power_test chipset_impl ( .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), - `endif // XUPP3R_BOARD + `endif // XUPP3R_OR_ALVEO .ddr_odt(ddr_odt) `else // ifndef F1_BOARD .mc_clk(mc_clk), @@ -1421,6 +1435,20 @@ chipset_impl_noc_power_test chipset_impl ( `endif // PITON_FPGA_ETHERNETLITE `endif // endif PITONSYS_IOCTRL + `ifdef ALVEO_BOARD + , // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + .chip_rstn (chip_rstn) + + `endif + `ifdef PITON_RV64_PLATFORM `ifdef PITON_RV64_DEBUGUNIT ,.ndmreset_o ( ndmreset_o ) diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 76bfff05b..75a5f0418 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -87,6 +87,18 @@ module chipset_impl( // invalid access inside packet filter output invalid_access_o, +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , +`endif + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD @@ -152,11 +164,11 @@ module chipset_impl( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -778,6 +790,54 @@ credit_to_valrdy noc3_xbar_to_%s( .m_axi_bready(m_axi_bready), .ddr_ready(ddr_ready) ); + `elsif ALVEO_BOARD + u280_polara_top u280_polara_i ( + + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + + // DDR4 physicall interface + .c0_ddr4_act_n ( ddr_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( ddr_addr ), + .c0_ddr4_ba ( ddr_ba ), + .c0_ddr4_bg ( ddr_bg ), // bank group address + .c0_ddr4_ck_t ( ddr_ck_p ), + .c0_ddr4_ck_c ( ddr_ck_n ), + .c0_ddr4_cke ( ddr_cke ), + .c0_ddr4_cs_n ( ddr_cs_n ), + .c0_ddr4_dq ( ddr_dq ), + .c0_ddr4_dqs_c ( ddr_dqs_n ), + .c0_ddr4_dqs_t ( ddr_dqs_p ), + .c0_ddr4_odt ( ddr_odt ), + .c0_ddr4_par ( ddr_parity ), // output wire c0_ddr4_parity + .c0_ddr4_reset_n ( ddr_reset_n ), + + // DDR4 clock & reset + .c0_sysclk_clk_p ( mc_clk_p ), + .c0_sysclk_clk_n ( mc_clk_n ), + + .c0_init_calib_complete ( init_calib_complete ), + + .chip_rstn (chip_rstn ), + .chipset_clk (chipset_clk ), + .chipset_rstn (chipset_rst_n ), + + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_rdy(buf_mem_noc3_ready) + + ); `else mc_top mc_top( .mc_ui_clk_sync_rst(mc_ui_clk_sync_rst), @@ -1121,7 +1181,11 @@ fake_uart fake_uart ( // this is for selecting the right bootrom (1: baremetal, 0: linux) wire ariane_boot_sel; `ifdef PITON_FPGA_SYNTH - assign ariane_boot_sel = uart_boot_en; + `ifdef ALVEO_BOARD + assign ariane_boot_sel = 1'b1; + `else + assign ariane_boot_sel = uart_boot_en; + `endif `else `ifdef ARIANE_SIM_LINUX_BOOT assign ariane_boot_sel = 1'b0; diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci new file mode 100644 index 000000000..e3bdaecc8 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w64_d128_std + + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 7 + BlankString + 64 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 64 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplusHBM + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x72 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1 + 7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 7 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + afifo_w64_d128_std + 64 + false + 7 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 64 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 64 + 128 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 7 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 7 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci new file mode 100644 index 000000000..02843e9a1 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci @@ -0,0 +1,823 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 100.000 + 0000 + 0000 + 100.00000 + 0000 + 0000 + 250.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100 + 0.000 + 1 + 0000 + 0000 + 50.00000 + BUFG + 50.0 + false + 250.00000 + 0.000 + 50.000 + 250.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 50.00000 + 0.000 + 50.000 + 50 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 25.00000 + BUFG + 50.0 + false + 100.00000 + 180.000 + 50.000 + 100.000 + 180.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 25.00000 + 0.000 + 50.000 + 25.000 + 0.000 + 1 + 1 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + VCO + clk_in_sel + chipset_clk + mc_sys_clk + sd_sys_clk + chipset_passthru_clk + chipset_passthru_clk_n + net_phy_clk + net_axi_clk + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.4 + 2.0 + 1.0 + 1.0 + 4.0 + 1.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________100_______________35 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 10.000 + 0.000 + FALSE + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 20 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + 10 + 0.500 + 180.000 + FALSE + 40 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.004 + 0.010 + FALSE + 128.000 + 2.000 + 7 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + chipset_clk__100.00000______0.000______50.0______129.254_____98.575 + mc_sys_clk__250.00000______0.000______50.0______108.624_____98.575 + sd_sys_clk__50.00000______0.000______50.0______147.729_____98.575 + chipset_passthru_clk__100.00000______0.000______50.0______129.254_____98.575 + chipset_passthru_clk_n__100.00000____180.000______50.0______129.254_____98.575 + net_phy_clk__25.00000______0.000______50.0______168.830_____98.575 + net_axi_clk__100.00000______0.000______50.0______129.254_____98.575 + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1600.000 + 800.000 + clk_mmcm + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 35 + 100.000 + 100.000 + BUFG + 129.254 + false + 98.575 + 50.000 + 100 + 0.000 + 1 + true + BUFG + 108.624 + false + 98.575 + 50.000 + 250.000 + 0.000 + 1 + true + BUFG + 147.729 + false + 98.575 + 50.000 + 50 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 180.000 + 1 + true + BUFG + 168.830 + false + 98.575 + 50.000 + 25.000 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + 600.000 + Custom + Custom + clk_in_sel + chipset_clk + false + mc_sys_clk + false + sd_sys_clk + false + chipset_passthru_clk + false + chipset_passthru_clk_n + false + net_phy_clk + false + net_axi_clk + false + CLK_VALID + auto + clk_mmcm + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + PS + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 20 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + 10 + 0.500 + 180.000 + false + 40 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.004 + 0.010 + false + 7 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/include/piton_system.vh b/piton/design/include/piton_system.vh index 5b6618fd8..0c25e8f71 100644 --- a/piton/design/include/piton_system.vh +++ b/piton/design/include/piton_system.vh @@ -122,6 +122,8 @@ `define PITON_CHIPSET_DIFF_CLK `elsif GENESYS2_BOARD `define PITON_CHIPSET_DIFF_CLK +`elsif ALVEO_BOARD + `define PITON_CHIPSET_DIFF_CLK `elsif PITON_BOARD `define PITON_CHIPSET_DIFF_CLK `define PITON_CHIPSET_DIFF_CLK_POLARITY_CAPS @@ -134,6 +136,8 @@ `define PITON_FPGA_RST_ACT_HIGH `elsif VCU118_BOARD `define PITON_FPGA_RST_ACT_HIGH +`elsif ALVEO_BOARD + `define PITON_FPGA_RST_ACT_HIGH `endif `ifdef XUPP3R_BOARD @@ -143,6 +147,9 @@ `undef PITON_FPGA_SD_BOOT `undef PITONSYS_SPI `define PITONSYS_AXI4_MEM +`elsif ALVEO_BOARD + `undef PITON_FPGA_SD_BOOT + `undef PITONSYS_SPI `endif // If PITON_FPGA_SD_BOOT is set we should always include SPI @@ -159,4 +166,12 @@ `define PITONSYS_DDR4 `elsif XUPP3R_BOARD `define PITONSYS_DDR4 +`elsif ALVEO_BOARD + `define PITONSYS_DDR4 `endif + +`ifdef XUPP3R_BOARD + `define XUPP3R_OR_ALVEO +`elsif ALVEO_BOARD + `define XUPP3R_OR_ALVEO +`endif \ No newline at end of file diff --git a/piton/design/rtl/system.v b/piton/design/rtl/system.v index e0ed161ac..4860d5a07 100644 --- a/piton/design/rtl/system.v +++ b/piton/design/rtl/system.v @@ -107,6 +107,17 @@ module system( input passthru_chipset_clk_n, `endif // endif PITON_PASSTHRU_CLKS_GEN `endif // endif PITON_SYS_INC_PASSTHRU + +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , +`endif `ifndef F1_BOARD `ifdef PITON_CHIPSET_CLKS_GEN @@ -142,7 +153,9 @@ module system( input sys_clk, `endif +`ifndef ALVEO_BOARD input sys_rst_n, +`endif `ifndef PITON_FPGA_SYNTH input pll_rst_n, @@ -180,6 +193,7 @@ module system( `ifndef VCU118_BOARD `ifndef NEXYSVIDEO_BOARD `ifndef XUPP3R_BOARD +`ifndef ALVEO_BOARD `ifndef F1_BOARD input tck_i, input tms_i, @@ -187,6 +201,7 @@ module system( input td_i, output td_o, `endif//F1_BOARD +`endif //ALVEO_BOARD `endif//XUPP3R_BOARD `endif //NEXYSVIDEO_BOARD `endif //VCU118_BOARD @@ -230,11 +245,11 @@ module system( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, - `endif // XUPP3R_BOARD + `endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -384,7 +399,7 @@ module system( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, -`elsif XUPP3R_BOARD +`elsif XUPP3R_OR_ALVEO // no switches :( `else input [7:0] sw, @@ -392,6 +407,8 @@ module system( `ifdef XUPP3R_BOARD output [3:0] leds +`elsif ALVEO_BOARD + output hbm_cattrip `else output [7:0] leds `endif @@ -560,6 +577,13 @@ assign rtc = rtc_div[6]; assign uart_rts = 1'b0; `endif // VCU118_BOARD +`ifdef ALVEO_BOARD + + wire sys_rst_n; + assign hbm_cattrip = 1'b0; + +`endif + // Different reset active levels for different boards always @ * begin @@ -945,6 +969,17 @@ chipset chipset( .mc_clk_n(mc_clk_n), `endif // PITONSYS_DDR4 +`ifdef ALVEO_BOARD + .pcie_refclk_clk_n (pcie_refclk_clk_n) , + .pcie_refclk_clk_p (pcie_refclk_clk_p) , + .pcie_perstn (pcie_perstn) , + .pci_express_x16_rxn (pci_express_x16_rxn) , + .pci_express_x16_rxp (pci_express_x16_rxp) , + .pci_express_x16_txn (pci_express_x16_txn ) , + .pci_express_x16_txp (pci_express_x16_txp) , + .resetn (resetn), +`endif + `else // ifndef PITON_CHIPSET_CLKS_GEN .chipset_clk(chipset_clk), `ifndef PITONSYS_NO_MC @@ -1066,7 +1101,7 @@ chipset chipset( `ifndef NEXYSVIDEO_BOARD .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), @@ -1134,6 +1169,10 @@ chipset chipset( `endif // PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC +`ifdef ALVEO_BOARD + .chip_rstn (sys_rst_n), +`endif + `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART .uart_tx(uart_tx), @@ -1203,7 +1242,7 @@ chipset chipset( .btnc(btnc), `endif -`ifndef XUPP3R_BOARD +`ifndef XUPP3R_OR_ALVEO .sw(sw), `endif .leds(leds) diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index 46f0870ea..a223f1536 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -48,6 +48,7 @@ NOC_PAYLOAD_WIDTH = 512 STORAGE_BLOCK_BIT_WIDTH = { "ddr": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":128, "genesys2":256, @@ -56,6 +57,7 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -65,6 +67,7 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -76,6 +79,7 @@ STORAGE_ADDRESSABLE_BIT_WIDTH = { "ddr": { "vc707":64, "vcu118":64, + "alveou280":72, "xupp3r":64, "nexys4ddr":16, "genesys2":32, @@ -84,6 +88,7 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -93,17 +98,21 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, "nexysVideo":512, "piton_board":512, "f1":512 + }, + "hbm": { "alveou280":33 } } STORAGE_BIT_SIZE = { "ddr": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, @@ -112,6 +121,7 @@ }, "bram": { "vc707":16384*512, "vcu118":16384*512, + "alveou280":116384*512, "xupp3r":16384*512, "nexys4ddr":16384*512, "genesys2":16384*512, @@ -121,11 +131,14 @@ }, "dmw": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, "nexysVideo":8*512*2**20, "f1":8*4*2**30 + }, + "hbm": { "alveou280":8*4*2*33 } } DW_BIT_SIZE = 64 @@ -345,7 +358,7 @@ def buildProjectSuccess(log_dir): dbg.print_error("Check: %s" % fpath) return False - dbg.print_info("Project was build successfully!") + dbg.print_info("Project was built successfully!") return True diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index d0326f536..2fd0e35b2 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -498,6 +498,9 @@ def makeDefList(options): if (options.board == "f1"): print_info("design option is ignored for f1") + if (options.board == "alveou280"): + defines.append("PITON_ALVEO") + # --no-ddr option if (options.no_ddr == True) or (options.board == "piton_board"): defines.append("PITONSYS_NO_MC") @@ -516,7 +519,7 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1", "alveou280"}): + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") From 6c7e18bb1ef496a5eb13955584f65be3e06e195d Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Fri, 11 Aug 2023 12:15:11 -0400 Subject: [PATCH 006/144] Replaced Polara BD creation file --- piton/tools/src/proto/alveou280/polara.tcl | 364 --------------------- 1 file changed, 364 deletions(-) delete mode 100644 piton/tools/src/proto/alveou280/polara.tcl diff --git a/piton/tools/src/proto/alveou280/polara.tcl b/piton/tools/src/proto/alveou280/polara.tcl deleted file mode 100644 index 274132d03..000000000 --- a/piton/tools/src/proto/alveou280/polara.tcl +++ /dev/null @@ -1,364 +0,0 @@ - -################################################################ -# This is a generated script based on design: polara_fpga -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source design_1_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./tmp_proj/project_1.xpr> in the current working folder. - -set DV_ROOT $::env(DV_ROOT) -set PITON_ROOT $::env(PITON_ROOT)1 - -set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo -set tmp_prj "create_bd" - -file delete -force ${tmp_build_dir}/${tmp_prj} - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2l-e - set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] -} - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name polara_fpga - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 -current_bd_design $design_name - - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - - -################################################################## -# DESIGN PROCs -################################################################## - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - # Create interface ports - set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] - - set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {64} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {512} \ - CONFIG.FREQ_HZ {156250000} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {1} \ - CONFIG.HAS_CACHE {1} \ - CONFIG.HAS_LOCK {1} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {1} \ - CONFIG.HAS_REGION {1} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.MAX_BURST_LENGTH {256} \ - CONFIG.NUM_READ_OUTSTANDING {1} \ - CONFIG.NUM_READ_THREADS {1} \ - CONFIG.NUM_WRITE_OUTSTANDING {1} \ - CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {1} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $c0_ddr4_s_axi - - set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {32} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {0} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {0} \ - CONFIG.ID_WIDTH {0} \ - CONFIG.MAX_BURST_LENGTH {1} \ - CONFIG.NUM_READ_OUTSTANDING {1} \ - CONFIG.NUM_READ_THREADS {1} \ - CONFIG.NUM_WRITE_OUTSTANDING {1} \ - CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PROTOCOL {AXI4LITE} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {0} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $c0_ddr4_s_axi_ctrl - - set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {100000000} \ - ] $c0_sysclk - - set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] - - set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] - - - # Create ports - set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] - set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi_ctrl} \ - ] $c0_ddr4_ui_clk - set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] - set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] - set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] - set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] - set resetn [ create_bd_port -dir I -type rst resetn ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $resetn - - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] - set_property -dict [ list \ - CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_GPIO_WIDTH {2} \ - ] $axi_gpio_0 - - # Create instance: axi_xbar_pcie, and set properties - set axi_xbar_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar_pcie ] - set_property -dict [ list \ - CONFIG.M00_HAS_REGSLICE {4} \ - CONFIG.NUM_MI {1} \ - CONFIG.NUM_SI {2} \ - CONFIG.S00_HAS_REGSLICE {4} \ - CONFIG.S01_HAS_REGSLICE {4} \ - ] $axi_xbar_pcie - - # Create instance: chip_rstn, and set properties - set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] - set_property -dict [ list \ - CONFIG.DIN_FROM {1} \ - CONFIG.DIN_TO {1} \ - CONFIG.DIN_WIDTH {2} \ - CONFIG.DOUT_WIDTH {1} \ - ] $chip_rstn - - # Create instance: ddr4_0, and set properties - set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] - set_property -dict [ list \ - CONFIG.C0.CKE_WIDTH {2} \ - CONFIG.C0.CS_WIDTH {2} \ - CONFIG.C0.DDR4_AxiAddressWidth {34} \ - CONFIG.C0.DDR4_AxiDataWidth {512} \ - CONFIG.C0.DDR4_CLKFBOUT_MULT {11} \ - CONFIG.C0.DDR4_CLKOUT0_DIVIDE {7} \ - CONFIG.C0.DDR4_CasLatency {10} \ - CONFIG.C0.DDR4_CasWriteLatency {9} \ - CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ - CONFIG.C0.DDR4_DataWidth {72} \ - CONFIG.C0.DDR4_EN_PARITY {true} \ - CONFIG.C0.DDR4_Ecc {true} \ - CONFIG.C0.DDR4_InputClockPeriod {10044} \ - CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ - CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PDZ-2G3} \ - CONFIG.C0.DDR4_MemoryType {RDIMMs} \ - CONFIG.C0.DDR4_Specify_MandD {false} \ - CONFIG.C0.DDR4_TimePeriod {1598} \ - CONFIG.C0.ODT_WIDTH {2} \ - ] $ddr4_0 - - # Create instance: proc_sys_rst_pcie, and set properties - set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] - - # Create instance: qdma_0, and set properties - set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] - set_property -dict [ list \ - CONFIG.MAILBOX_ENABLE {true} \ - CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ - CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ - CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ - CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ - CONFIG.SRIOV_CAP_ENABLE {true} \ - CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ - CONFIG.axi_data_width {256_bit} \ - CONFIG.barlite_mb_pf0 {1} \ - CONFIG.coreclk_freq {250} \ - CONFIG.dma_intf_sel_qdma {AXI_MM} \ - CONFIG.en_axi_st_qdma {false} \ - CONFIG.flr_enable {true} \ - CONFIG.mode_selection {Advanced} \ - CONFIG.pf0_ari_enabled {true} \ - CONFIG.pf0_bar0_prefetchable_qdma {true} \ - CONFIG.pf0_bar2_prefetchable_qdma {true} \ - CONFIG.pf0_device_id {902F} \ - CONFIG.pf1_bar0_prefetchable_qdma {true} \ - CONFIG.pf1_bar2_prefetchable_qdma {true} \ - CONFIG.pf1_msix_enabled_qdma {false} \ - CONFIG.pf2_bar0_prefetchable_qdma {true} \ - CONFIG.pf2_bar2_prefetchable_qdma {true} \ - CONFIG.pf2_device_id {922F} \ - CONFIG.pf2_msix_enabled_qdma {false} \ - CONFIG.pf3_bar0_prefetchable_qdma {true} \ - CONFIG.pf3_bar2_prefetchable_qdma {true} \ - CONFIG.pf3_device_id {932F} \ - CONFIG.pf3_msix_enabled_qdma {false} \ - CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ - CONFIG.testname {mm} \ - ] $qdma_0 - - # Create instance: rst_ea_CLK0, and set properties - set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] - - # Create instance: sys_rstn, and set properties - set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] - set_property -dict [ list \ - CONFIG.DIN_WIDTH {2} \ - ] $sys_rstn - - # Create instance: util_ds_buf, and set properties - set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] - set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDSGTE} \ - ] $util_ds_buf - - # Create instance: vdd_0, and set properties - set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] - - # Create interface connections - connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_xbar_pcie/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] - connect_bd_intf_net -intf_net c0_ddr4_s_axi_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins axi_xbar_pcie/S01_AXI] - connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] - connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] - connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] - connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins axi_xbar_pcie/S00_AXI] [get_bd_intf_pins qdma_0/M_AXI] - connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] - connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] - - # Create port connections - connect_bd_net -net ARESETN_1 [get_bd_pins axi_xbar_pcie/ARESETN] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] - connect_bd_net -net M00_ARESETN_1 [get_bd_pins axi_xbar_pcie/M00_ARESETN] [get_bd_pins axi_xbar_pcie/S01_ARESETN] [get_bd_pins rst_ea_CLK0/peripheral_aresetn] - connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] - connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] - connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins axi_xbar_pcie/ACLK] [get_bd_pins axi_xbar_pcie/M00_ACLK] [get_bd_pins axi_xbar_pcie/S01_ACLK] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] - connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] - connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] - connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] - connect_bd_net -net proc_sys_rst_pcie_peripheral_aresetn [get_bd_pins axi_xbar_pcie/S00_ARESETN] [get_bd_pins proc_sys_rst_pcie/peripheral_aresetn] - connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_xbar_pcie/S00_ACLK] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] - connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] - connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] - connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] - connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] - connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] - connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] - connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] - connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] - - # Create address segments - assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force - assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force - assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force - assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force - - - - # ########################################################### - # Final changes. Use this block to customize the bd - - # Decrease the PCIe speed for better timing results - - # ########################################################### - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - -close_project - -file delete -force ${tmp_build_dir}/${tmp_prj} - - From 6ad340ae6cb1f41fb70c2a97e8884116457aaba1 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 14 Aug 2023 15:09:56 -0400 Subject: [PATCH 007/144] [FPGA] Update Alveo U280 constraints --- piton/design/xilinx/alveou280/constraints.xdc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index 02f6d81e5..4b630a5cb 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -13,6 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] # --------------------------------------------------------------------- +# Don't time the GPIO reset signals +set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] # 156.25MHz General purpose system clock set_property PACKAGE_PIN F30 [get_ports {chipset_clk_osc_n}] From 958d0f68ae953d12c5546ee18f8a410d439b4123 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 29 Aug 2023 15:51:00 -0400 Subject: [PATCH 008/144] [FPGA] Bug fixing on U280 flow --- piton/design/chipset/mc/rtl/u280_polara_top.v | 2 + piton/design/xilinx/alveou280/constraints.xdc | 7 +- .../tools/src/proto/alveou280/polara_fpga.tcl | 2 +- piton/tools/src/proto/common/rtl_setup.tcl | 287 +++++++++--------- 4 files changed, 157 insertions(+), 141 deletions(-) diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v index c5e3bc0b0..7e27ac496 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.v +++ b/piton/design/chipset/mc/rtl/u280_polara_top.v @@ -1,6 +1,8 @@ `include "mc_define.h" +`include "noc_axi4_bridge_define.vh" + module u280_polara_top ( input pcie_refclk_clk_n , diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index 4b630a5cb..a79e70f5e 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -68,8 +68,8 @@ set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]} ] set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 -set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP2_225 -set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP3_225 +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP2_225 +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP3_225 set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]} ] ;# Bank 226 - MGTYRXN0_226 set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]} ] ;# Bank 226 - MGTYRXN1_226 set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]} ] ;# Bank 226 - MGTYRXN2_226 @@ -268,4 +268,5 @@ set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [ get_p set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] -set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] \ No newline at end of file +set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] + diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl index f5debf750..37ffca4eb 100644 --- a/piton/tools/src/proto/alveou280/polara_fpga.tcl +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -29,7 +29,7 @@ set script_folder [_tcl::get_script_folder] # <./tmp_proj/project_1.xpr> in the current working folder. set DV_ROOT $::env(DV_ROOT) -set PITON_ROOT $::env(PITON_ROOT)1 +set PITON_ROOT $::env(PITON_ROOT) set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo set tmp_prj "create_bd" diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 58676a147..0959cc4d5 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,7 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" # RTL include files @@ -399,153 +399,156 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_tag.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_config_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_soc_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi/src/axi_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_axi_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/wt_cache_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/axi_intf.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/acc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_soc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/wt_cache_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/axi_intf.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/cvxif_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/cf_math_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/instr_tracer_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/include/cvxif_instr_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/acc_dispatcher.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_master_connect.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_master_connect_rev.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_slave_connect.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_slave_connect_rev.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/rrarbiter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/fifo_v1.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/fifo_v2.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/fifo_v3.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/shift_reg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lfsr_8bit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lfsr.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lzc.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/exp_backoff.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/rr_arb_tree.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/rstgen_bypass.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/cdc_2phase.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/unread.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/popcount.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/fpga/tc_clk_xilinx.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/fpga/tc_sram_xilinx.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/tc_sram_xilinx_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/axi_adapter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ariane.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/controller.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/csr_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/csr_regfile.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ex_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/btb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/bht.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/ras.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_scan.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_queue.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/frontend.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/id_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/instr_realign.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/issue_read_operands.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/issue_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/load_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/load_store_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/lsu_bypass.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/mmu.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mult.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/multiplier.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/serdiv.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/perf_counters.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/ptw.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ariane_regfile_ff.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/re_name.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/scoreboard.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/store_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/amo_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/store_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/tlb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/commit_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_ctrl.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_missunit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache_axi_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_l15_adapter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_cache_subsystem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/clint.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/axi_lite_interface.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/debug_rom/debug_rom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_csrs.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_top.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_cdc.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_sba.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/fifo_v3.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/shift_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lfsr.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lzc.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/exp_backoff.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/cdc_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/unread.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/popcount.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/tc_sram_fpga_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/axi_adapter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/ariane.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/controller.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/csr_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/csr_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/ex_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/btb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/bht.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/ras.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_scan.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/frontend.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/id_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/instr_realign.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/issue_read_operands.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/issue_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/load_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/load_store_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/lsu_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/mmu.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mult.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/multiplier.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/serdiv.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/perf_counters.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/ptw.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/ariane_regfile_ff.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/re_name.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/scoreboard.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/store_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/amo_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/store_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/tlb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/commit_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_ctrl.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_missunit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache_axi_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_l15_adapter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_cache_subsystem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/clint.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/axi_lite_interface.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/debug_rom/debug_rom.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_csrs.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_sba.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_cast_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_classifier.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_divsqrt_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_fma_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_fma.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_noncomp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_block.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_fmt_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_multifmt_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_rounding.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_fma.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_top.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp_entry.sv" \ \ + "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp_entry.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/instr_tracer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/instr_tracer_if.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/cvxif_example_coprocessor.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/instr_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/counter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/delta_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/counter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axilite.sv " \ "${DV_ROOT}/design/chip/tile/ara/openpiton/strb2mask.v" \ @@ -563,8 +566,10 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_to_mem.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/ctrl_registers.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/cva6_accel_first_pass_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/power_gating_generic.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/fixed_p_rounding.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queues_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/ara_popcnt.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_alu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/valu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vmfpu.sv" \ @@ -577,6 +582,8 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_mul.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_regfile.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/masku/masku.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/p2_stride_gen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu_op_dp.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/addrgen.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vldu.sv" \ @@ -682,6 +689,12 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mailbox.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_dst.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_regs.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_err_slv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ ] set CHIP_INCLUDE_FILES [list \ From c81482f35f4f140fa29370f334023f7d571e6fb2 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Mon, 9 Oct 2023 17:27:37 -0400 Subject: [PATCH 009/144] [FPGA] Polara timing fix at 50MHz --- .../design/chipset/mc/rtl/u280_polara_top.sv | 327 +++++++++++++ piton/design/chipset/rtl/chipset.v | 4 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 9 +- .../alveou280/ip_cores/clk_mmcm/clk_mmcm.xci | 28 +- piton/design/xilinx/alveou280/constraints.xdc | 456 +++++++++--------- .../tools/src/proto/alveou280/polara_fpga.tcl | 38 +- piton/tools/src/proto/block.list | 2 +- piton/tools/src/proto/common/rtl_setup.tcl | 12 +- 8 files changed, 617 insertions(+), 259 deletions(-) create mode 100644 piton/design/chipset/mc/rtl/u280_polara_top.sv diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.sv b/piton/design/chipset/mc/rtl/u280_polara_top.sv new file mode 100644 index 000000000..cf9823117 --- /dev/null +++ b/piton/design/chipset/mc/rtl/u280_polara_top.sv @@ -0,0 +1,327 @@ + +`include "mc_define.h" + +`include "noc_axi4_bridge_define.vh" + +module u280_polara_top ( + + input logic pcie_refclk_clk_n , + input logic pcie_refclk_clk_p , + input logic pcie_perstn , + input logic [15:0] pci_express_x16_rxn , + input logic [15:0] pci_express_x16_rxp , + output logic [15:0] pci_express_x16_txn , + output logic [15:0] pci_express_x16_txp , + input logic resetn , + + output logic c0_ddr4_act_n, + output logic [16:0] c0_ddr4_adr, + output logic [1:0] c0_ddr4_ba, + output logic [1:0] c0_ddr4_bg, + output logic [0:0] c0_ddr4_ck_c, + output logic [0:0] c0_ddr4_ck_t, + output logic [0:0] c0_ddr4_cke, + output logic [0:0] c0_ddr4_cs_n, + inout wire [71:0] c0_ddr4_dq, + inout wire [17:0] c0_ddr4_dqs_c, + inout wire [17:0] c0_ddr4_dqs_t, + output logic [0:0] c0_ddr4_odt, + output logic c0_ddr4_par, + output logic c0_ddr4_reset_n, + output logic c0_ddr4_ui_clk_sync_rst, + + // Reference clock + input logic c0_sysclk_clk_n, + input logic c0_sysclk_clk_p, + // input mc_clk , + // input mc_rstn , + output logic chip_rstn , + input logic chipset_clk , + input logic chipset_rstn , + output logic c0_init_calib_complete, + + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , + + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy +); + +// ------------------Debug Section----------------- +(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_rdy_r; +(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_rdy_r; +/* +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_rdy_r; +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_val_r; +(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_rdy_r;*/ + + + logic mc_rst; + logic mc_clk; + + + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; + + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_awid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_awlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_awsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_awburst; + logic m_axi_awlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_awcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_awprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_awqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_awregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_awuser; + logic m_axi_awvalid; + logic m_axi_awready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_wdata; + logic [`AXI4_STRB_WIDTH -1:0] m_axi_wstrb; + logic m_axi_wlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; + logic m_axi_wvalid; + logic m_axi_wready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_arid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_araddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_arlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_arsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_arburst; + logic m_axi_arlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_arcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_arprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_arqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; + logic m_axi_arvalid; + logic m_axi_arready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_rid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_rdata; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_rresp; + logic m_axi_rlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_ruser; + logic m_axi_rvalid; + logic m_axi_rready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_bid; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_bresp; + logic [`AXI4_USER_WIDTH -1:0] m_axi_buser; + logic m_axi_bvalid; + logic m_axi_bready; + + noc_bidir_afifo mig_afifo ( + .clk_1 ( chipset_clk ), + .rst_1 ( ~chipset_rstn ), + + .clk_2 ( mc_clk ), + .rst_2 ( mc_rst ), + + // CPU --> MIG + .flit_in_val_1 ( mem_flit_in_val ), + .flit_in_data_1 ( mem_flit_in_data ), + .flit_in_rdy_1 ( mem_flit_in_rdy ), + + .flit_out_val_2 ( fifo_trans_val ), + .flit_out_data_2 ( fifo_trans_data ), + .flit_out_rdy_2 ( fifo_trans_rdy ), + + // MIG --> CPU + .flit_in_val_2 ( trans_fifo_val ), + .flit_in_data_2 ( trans_fifo_data ), + .flit_in_rdy_2 ( trans_fifo_rdy ), + + .flit_out_val_1 ( mem_flit_out_val ), + .flit_out_data_1 ( mem_flit_out_data ), + .flit_out_rdy_1 ( mem_flit_out_rdy ) + ); + + + noc_axi4_bridge noc_axi4_bridge ( + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( c0_init_calib_complete ), + + .src_bridge_vr_noc2_val ( fifo_trans_val ), + .src_bridge_vr_noc2_dat ( fifo_trans_data ), + .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), + + .bridge_dst_vr_noc3_val ( trans_fifo_val ), + .bridge_dst_vr_noc3_dat ( trans_fifo_data ), + .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + + .m_axi_wid ( m_axi_wid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_buser ( m_axi_buser ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + + .m_axi_rid ( m_axi_rid), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + + ); + + polara_fpga polara_i ( + + .c0_sysclk_clk_p ( c0_sysclk_clk_p ), + .c0_sysclk_clk_n ( c0_sysclk_clk_n ), + .c0_ddr4_ui_clk ( mc_clk ), + .c0_ddr4_ui_clk_sync_rst ( mc_rst ), + .c0_init_calib_complete ( c0_init_calib_complete ), + + // DDR4 physicall interface + .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_par ( c0_ddr4_par ), // output logic c0_ddr4_parity + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + + // DDR4 control interface, not used, grounded + .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_awvalid + .c0_ddr4_s_axi_ctrl_awready( ), // output logic c0_ddr4_s_axi_ctrl_awready + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output logic c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output logic c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_arvalid + .c0_ddr4_s_axi_ctrl_arready( ), // output logic c0_ddr4_s_axi_ctrl_arready + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output logic c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output logic [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_rresp + + .chip_rstn ( chip_rstn ), + + // AXI4 Memory Interface + .c0_ddr4_s_axi_awid ( m_axi_awid), // input logic [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input logic [34 : 0] c0_ddr4_s_axi_awaddr + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input logic [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input logic [2 : 0] c0_ddr4_s_axi_awsize + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input logic [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input logic [0 : 0] c0_ddr4_s_axi_awlock + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input logic [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input logic [2 : 0] c0_ddr4_s_axi_awprot + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input logic [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input logic c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output logic c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input logic [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input logic [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input logic c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input logic c0_ddr4_s_axi_wvalid + .c0_ddr4_s_axi_wready ( m_axi_wready), // output logic c0_ddr4_s_axi_wready + .c0_ddr4_s_axi_bready ( m_axi_bready), // input logic c0_ddr4_s_axi_bready + .c0_ddr4_s_axi_bid ( m_axi_bid), // output logic [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output logic [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output logic c0_ddr4_s_axi_bvalid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input logic [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input logic [34 : 0] c0_ddr4_s_axi_araddr + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input logic [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input logic [2 : 0] c0_ddr4_s_axi_arsize + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input logic [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input logic [0 : 0] c0_ddr4_s_axi_arlock + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input logic [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input logic [2 : 0] c0_ddr4_s_axi_arprot + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input logic [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input logic c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output logic c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_rready ( m_axi_rready), // input logic c0_ddr4_s_axi_rready + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output logic c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output logic c0_ddr4_s_axi_rvalid + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output logic [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output logic [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output logic [511 : 0] c0_ddr4_s_axi_rdata + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn) + ); + +always @(posedge mc_clk) begin : p_debug + fifo_trans_val_r <= fifo_trans_val; + fifo_trans_rdy_r <= fifo_trans_rdy; + trans_fifo_val_r <= trans_fifo_val; + trans_fifo_rdy_r <= trans_fifo_rdy; + +end +/*always@(posedge mc_clk) begin: p_debug + mem_flit_in_val_r <= mem_flit_in_val; + mem_flit_in_rdy_r <= mem_flit_in_rdy; + mem_flit_out_val_r <= mem_flit_out_val; + mem_flit_out_rdy_r <= mem_flit_out_rdy; +end */ + +endmodule + diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 55a881f64..b0ad831be 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -88,7 +88,8 @@ module chipset( `ifdef F1_BOARD input sys_clk, -`elsif ALVEO_BOARD +`else +`ifdef ALVEO_BOARD input pcie_refclk_clk_n , input pcie_refclk_clk_p , input pcie_perstn , @@ -99,6 +100,7 @@ module chipset( input resetn , output chip_rstn , // Oscillator clock +`endif //ifdef ALVEO_BOARD `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK input clk_osc_p, diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 75a5f0418..f325938e0 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -476,8 +476,13 @@ assign chip_buf_noc3_data = {`NOC_DATA_WIDTH{1'b0}}; assign uart_timeout_en = 1'b0; `else // ifdef PITONSYS_UART `ifndef PITONSYS_UART_BOOT - assign uart_boot_en = 1'b0; - assign uart_timeout_en = 1'b0; + `ifndef ALVEO_BOARD + assign uart_boot_en = 1'b0; + assign uart_timeout_en = 1'b0; + `else + assign uart_boot_en = 1'b1; + assign uart_timeout_en = 1'b0; + `endif // endif ALVEO_BOARD `endif // endif PITONSYS_UART_BOOT `endif // endif PITONSYS_UART `endif // endif PITONSYS_IOCTRL diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci index 02843e9a1..e25583f1d 100644 --- a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci @@ -131,17 +131,17 @@ 100.000 0000 0000 - 100.00000 + 50.00000 0000 0000 250.00000 BUFG 50.0 false - 100.00000 + 50.00000 0.000 50.000 - 100 + 50 0.000 1 0000 @@ -236,12 +236,12 @@ din 0000 1 - 0.4 - 2.0 - 1.0 - 1.0 - 4.0 - 1.0 + 0.2 + 1.0 + 0.5 + 0.5 + 2.0 + 0.5 dout drdy dwe @@ -284,7 +284,7 @@ FALSE 10.000 10.000 - 10.000 + 20.000 0.500 0.000 FALSE @@ -326,7 +326,7 @@ 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - chipset_clk__100.00000______0.000______50.0______129.254_____98.575 + chipset_clk__50.00000______0.000______50.0______147.729_____98.575 mc_sys_clk__250.00000______0.000______50.0______108.624_____98.575 sd_sys_clk__50.00000______0.000______50.0______147.729_____98.575 chipset_passthru_clk__100.00000______0.000______50.0______129.254_____98.575 @@ -448,11 +448,11 @@ 100.000 100.000 BUFG - 129.254 + 147.729 false 98.575 50.000 - 100 + 50 0.000 1 true @@ -564,7 +564,7 @@ false 10.000 10.000 - 10.000 + 20.000 0.500 0.000 false diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index a79e70f5e..fbe52f1e9 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -1,15 +1,15 @@ # Bitstream generation # --------------------------------------------------------------------- set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] #set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] ;# Choices are pullnone, pulldown, and pullup. +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] # --------------------------------------------------------------------- @@ -17,101 +17,112 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] # 156.25MHz General purpose system clock -set_property PACKAGE_PIN F30 [get_ports {chipset_clk_osc_n}] -set_property PACKAGE_PIN G30 [get_ports {chipset_clk_osc_p}] -set_property IOSTANDARD LVDS [get_ports {chipset_clk*}] +set_property PACKAGE_PIN G30 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN F30 [get_ports chipset_clk_osc_n] +set_property IOSTANDARD LVDS [get_ports chipset_clk*] # Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller -set_property PACKAGE_PIN L30 [get_ports resetn] -set_property IOSTANDARD LVCMOS18 [get_ports resetn] +set_property PACKAGE_PIN L30 [get_ports resetn] +set_property IOSTANDARD LVCMOS18 [get_ports resetn] # UART -set_property PACKAGE_PIN A28 [get_ports uart_rx] -set_property PACKAGE_PIN B33 [get_ports uart_tx] -set_property IOSTANDARD LVCMOS18 [get_ports uart_*] +set_property PACKAGE_PIN A28 [get_ports uart_rx] +set_property PACKAGE_PIN B33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_*] # PCIe MGTY Interface -set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 -set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] +set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] -set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]} ] ;# Bank 224 - MGTYRXN0_224 -set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]} ] ;# Bank 224 - MGTYRXN1_224 -set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]} ] ;# Bank 224 - MGTYRXN2_224 -set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]} ] ;# Bank 224 - MGTYRXN3_224 -set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]} ] ;# Bank 224 - MGTYRXP0_224 -set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]} ] ;# Bank 224 - MGTYRXP1_224 -set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]} ] ;# Bank 224 - MGTYRXP2_224 -set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]} ] ;# Bank 224 - MGTYRXP3_224 -set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]} ] ;# Bank 224 - MGTYTXN0_224 -set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]} ] ;# Bank 224 - MGTYTXN1_224 -set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]} ] ;# Bank 224 - MGTYTXN2_224 -set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]} ] ;# Bank 224 - MGTYTXN3_224 -set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]} ] ;# Bank 224 - MGTYTXP0_224 -set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]} ] ;# Bank 224 - MGTYTXP1_224 -set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]} ] ;# Bank 224 - MGTYTXP2_224 -set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]} ] ;# Bank 224 - MGTYTXP3_224 +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]}] +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]}] +set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]}] +set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]}] +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]}] +set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]}] +set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]}] +set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]}] +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]}] +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]}] +set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]}] +set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]}] +set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]}] +set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]}] +set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]}] +set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]}] # Clock -set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n ] ;# Bank 225 - MGTREFCLK0N_225 -set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p ] ;# Bank 225 - MGTREFCLK0P_225 +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p] -set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]} ] ;# Bank 225 - MGTYRXN0_225 -set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]} ] ;# Bank 225 - MGTYRXN1_225 -set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]} ] ;# Bank 225 - MGTYRXN2_225 -set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]} ] ;# Bank 225 - MGTYRXN3_225 -set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]} ] ;# Bank 225 - MGTYRXP0_225 -set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]} ] ;# Bank 225 - MGTYRXP1_225 -set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]} ] ;# Bank 225 - MGTYRXP2_225 -set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]} ] ;# Bank 225 - MGTYRXP3_225 -set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]} ] ;# Bank 225 - MGTYTXN0_225 -set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]} ] ;# Bank 225 - MGTYTXN1_225 -set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]} ] ;# Bank 225 - MGTYTXN2_225 -set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 -set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 -set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 -set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]} ] ;# Bank 225 - MGTYTXP2_225 -set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]} ] ;# Bank 225 - MGTYTXP3_225 -set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]} ] ;# Bank 226 - MGTYRXN0_226 -set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]} ] ;# Bank 226 - MGTYRXN1_226 -set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]} ] ;# Bank 226 - MGTYRXN2_226 -set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]} ] ;# Bank 226 - MGTYRXN3_226 -set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]} ] ;# Bank 226 - MGTYRXP0_226 -set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]} ] ;# Bank 226 - MGTYRXP1_226 -set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]} ] ;# Bank 226 - MGTYRXP2_226 -set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]} ] ;# Bank 226 - MGTYRXP3_226 -set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]} ] ;# Bank 226 - MGTYTXN0_226 -set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]} ] ;# Bank 226 - MGTYTXN1_226 -set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]} ] ;# Bank 226 - MGTYTXN2_226 -set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]} ] ;# Bank 226 - MGTYTXN3_226 -set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]} ] ;# Bank 226 - MGTYTXP0_226 -set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]} ] ;# Bank 226 - MGTYTXP1_226 -set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]} ] ;# Bank 226 - MGTYTXP2_226 -set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]} ] ;# Bank 226 - MGTYTXP3_226 +set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]}] +set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]}] +set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]}] +set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]}] +set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]}] +set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]}] +set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]}] +set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]}] +set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]}] +set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]}] +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]}] +set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]}] +set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]}] +set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]}] +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]}] +set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]}] +set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]}] +set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]}] +set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]}] +set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]}] +set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]}] +set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]}] +set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]}] +set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]}] +set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]}] +set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]}] +set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]}] +set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]}] +set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]}] +set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]}] +set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]}] +set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]}] #set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 #set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 #set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 #set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 -set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]} ] ;# Bank 227 - MGTYRXN0_227 -set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]} ] ;# Bank 227 - MGTYRXN1_227 -set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]} ] ;# Bank 227 - MGTYRXN2_227 -set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]} ] ;# Bank 227 - MGTYRXN3_227 -set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]} ] ;# Bank 227 - MGTYRXP0_227 -set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]} ] ;# Bank 227 - MGTYRXP1_227 -set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]} ] ;# Bank 227 - MGTYRXP2_227 -set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]} ] ;# Bank 227 - MGTYRXP3_227 -set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]} ] ;# Bank 227 - MGTYTXN0_227 -set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]} ] ;# Bank 227 - MGTYTXN1_227 -set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]} ] ;# Bank 227 - MGTYTXN2_227 -set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]} ] ;# Bank 227 - MGTYTXN3_227 -set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]} ] ;# Bank 227 - MGTYTXP0_227 -set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]} ] ;# Bank 227 - MGTYTXP1_227 -set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]} ] ;# Bank 227 - MGTYTXP2_227 -set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]} ] ;# Bank 227 - MGTYTXP3_227 +set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]}] +set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]}] +set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]}] +set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]}] +set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]}] +set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]}] +set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]}] +set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]}] +set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]}] +set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]}] +set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]}] +set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]}] +set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]}] +set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]}] +set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]}] +set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]}] + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] + +#-------------------------------------------- +# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing +# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 +#Collecting all units from correspondingly PCIe domain, +#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/smartconnect_0] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/qdma_0] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/axi_gpio_0] + -create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] # 100MHz DDR0 System clock -set_property PACKAGE_PIN BJ44 [get_ports {mc_clk_n}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 -set_property PACKAGE_PIN BJ43 [get_ports {mc_clk_p}] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +set_property PACKAGE_PIN BJ43 [get_ports mc_clk_p] +set_property PACKAGE_PIN BJ44 [get_ports mc_clk_n] # DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank @@ -119,154 +130,157 @@ set_property PACKAGE_PIN BJ43 [get_ports {mc_clk_p}] ;# # JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 # Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 # -set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[16]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 -set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[16]}] +set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[15]}] #set_property -dict {PACKAGE_PIN BE46 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 #set_property -dict {PACKAGE_PIN BK44 IOSTANDARD SSTL12_DCI} [ get_ports {#NA} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 -set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cs_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 -set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[13]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cs_n[0]}] +set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[13]}] #set_property -dict {PACKAGE_PIN BL47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 -set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 -set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_odt[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[14]}] +set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_odt[0]}] #set_property -dict {PACKAGE_PIN BE45 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 #set_property -dict {PACKAGE_PIN BD42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 -set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 -set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[10]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 -set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 -set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[0]}] +set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[10]}] +set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_n[0]}] +set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_p[0]}] #set_property -dict {PACKAGE_PIN BK41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 #set_property -dict {PACKAGE_PIN BJ41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 -set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_ba[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 -set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_parity} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 -set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 -set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 -set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 -set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[4]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 -set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[3]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[1]}] +set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [get_ports ddr_parity] +set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[0]}] +set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[2]}] +set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[1]}] +set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[4]}] +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[3]}] #set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 -set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[8]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 -set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[7]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 -set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[11]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 -set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[9]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 -set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[5]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 -set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[6]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[8]}] +set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[7]}] +set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[11]}] +set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[9]}] +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[5]}] +set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[6]}] #set_property -dict {PACKAGE_PIN BJ42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 -set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 -set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[12]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 -set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_act_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 -set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_cke[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 -set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_bg[0]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 -set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[66]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 -set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[67]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 -set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 -set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[16]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 -set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[64]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 -set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[65]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 -set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[71]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 -set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[70]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 -set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[68]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 -set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[69]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 -set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 -set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[17]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 -set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[34]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 -set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[35]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 -set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 -set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[8]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[1]}] +set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[12]}] +set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [get_ports ddr_act_n] +set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cke[0]}] +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[0]}] +set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[66]}] +set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[67]}] +set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[16]}] +set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[16]}] +set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[64]}] +set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[65]}] +set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[71]}] +set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[70]}] +set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[68]}] +set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[69]}] +set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[17]}] +set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[17]}] +set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[34]}] +set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[35]}] +set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[8]}] +set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[8]}] #set_property -dict {PACKAGE_PIN BK29 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 -set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[33]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 -set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[32]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 -set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[38]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 -set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[39]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 -set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[37]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 -set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[36]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 -set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 -set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[9]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 -set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[25]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 -set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[24]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 -set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 -set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 -set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [ get_ports {ddr_reset_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 -set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[27]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 -set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[26]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 -set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[29]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 -set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[28]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 -set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[30]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 -set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[31]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 -set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 -set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 -set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[17]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 -set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[16]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 -set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 -set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 -set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[19]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 -set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[18]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 -set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[21]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 -set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[20]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 -set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[23]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 -set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[22]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 -set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 -set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 -set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[58]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 -set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[57]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 -set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 -set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[14]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 -set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[59]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 -set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[56]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 -set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[61]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 -set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[60]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 -set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[63]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 -set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[62]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 -set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 -set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[15]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 -set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[40]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 -set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[41]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 -set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 -set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[10]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 -set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[42]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 -set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[43]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 -set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[47]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 -set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[46]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 -set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[44]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 -set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[45]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - L21_T3L_N4_AD8 P_66 -set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 -set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[11]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 -set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[49]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 -set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[50]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 -set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 -set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[12]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 -set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[48]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 -set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[51]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 -set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[52]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 -set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[55]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 -set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[53]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 -set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[54]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 -set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 -set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[13]} ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 -set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 -set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 -set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 -set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 -set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 -set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[0]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 -set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[6]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 -set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[7]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 -set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[4]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 -set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[5]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 -set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 -set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[1]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 -set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[9]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 -set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[8]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 -set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 -set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[2]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 -set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[10]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 -set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[11]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 -set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[12]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 -set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[13]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 -set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[14]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 -set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [ get_ports {ddr_dq[15]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 -set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_n[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 -set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [ get_ports {ddr_dqs_p[3]} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 +set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[33]}] +set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[32]}] +set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[38]}] +set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[39]}] +set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[37]}] +set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[36]}] +set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[9]}] +set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[9]}] +set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[25]}] +set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[24]}] +set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[6]}] +set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[6]}] +set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [get_ports ddr_reset_n] +set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[27]}] +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[26]}] +set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[29]}] +set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[28]}] +set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[30]}] +set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[31]}] +set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[7]}] +set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[7]}] +set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[17]}] +set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[16]}] +set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[4]}] +set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[4]}] +set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[19]}] +set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[18]}] +set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[21]}] +set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[20]}] +set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[23]}] +set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[22]}] +set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[5]}] +set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[5]}] +set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[58]}] +set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[57]}] +set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[14]}] +set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[14]}] +set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[59]}] +set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[56]}] +set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[61]}] +set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[60]}] +set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[63]}] +set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[62]}] +set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[15]}] +set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[15]}] +set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[40]}] +set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[41]}] +set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[10]}] +set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[10]}] +set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[42]}] +set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[43]}] +set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[47]}] +set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[46]}] +set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[44]}] +set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[45]}] +set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[11]}] +set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[11]}] +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[49]}] +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[50]}] +set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[12]}] +set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[12]}] +set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[48]}] +set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[51]}] +set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[52]}] +set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[55]}] +set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[53]}] +set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[54]}] +set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[13]}] +set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[13]}] +set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[2]}] +set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[3]}] +set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[0]}] +set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[0]}] +set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[1]}] +set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[0]}] +set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[6]}] +set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[7]}] +set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[4]}] +set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[5]}] +set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[1]}] +set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[1]}] +set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[9]}] +set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[8]}] +set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[2]}] +set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[2]}] +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[10]}] +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[11]}] +set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[12]}] +set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[13]}] +set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[14]}] +set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[15]}] +set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[3]}] +set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[3]}] + +set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] +set_property PULLDOWN true [get_ports hbm_cattrip] + +set_false_path -from [get_pins chipset/chipset_impl/u280_polara_i/polara_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] -set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] -set_property PULLTYPE PULLDOWN [get_ports hbm_cattrip] diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl index 37ffca4eb..06b41694d 100644 --- a/piton/tools/src/proto/alveou280/polara_fpga.tcl +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -111,14 +111,14 @@ proc create_root_design { parentCell } { CONFIG.DATA_WIDTH {512} \ CONFIG.FREQ_HZ {300000000} \ CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {0} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {0} \ + CONFIG.HAS_WSTRB {1} \ CONFIG.ID_WIDTH {6} \ CONFIG.MAX_BURST_LENGTH {256} \ CONFIG.NUM_READ_OUTSTANDING {1} \ @@ -185,9 +185,6 @@ proc create_root_design { parentCell } { set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] set resetn [ create_bd_port -dir I -type rst resetn ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $resetn # Create instance: axi_gpio_0, and set properties set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] @@ -242,19 +239,31 @@ proc create_root_design { parentCell } { set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] set_property -dict [ list \ CONFIG.MAILBOX_ENABLE {true} \ - CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {4} \ - CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {7} \ - CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {10} \ - CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {13} \ + CONFIG.PF0_SRIOV_CAP_INITIAL_VF {4} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF1_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF1_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF2_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF2_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF3_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF3_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {0} \ CONFIG.SRIOV_CAP_ENABLE {true} \ CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ CONFIG.axi_data_width {256_bit} \ CONFIG.barlite_mb_pf0 {1} \ + CONFIG.barlite_mb_pf1 {0} \ + CONFIG.barlite_mb_pf2 {0} \ + CONFIG.barlite_mb_pf3 {0} \ CONFIG.coreclk_freq {250} \ CONFIG.dma_intf_sel_qdma {AXI_MM} \ CONFIG.en_axi_st_qdma {false} \ CONFIG.flr_enable {true} \ CONFIG.mode_selection {Advanced} \ + CONFIG.pcie_blk_locn {PCIE4C_X1Y0} \ + CONFIG.select_quad {GTY_Quad_227} \ CONFIG.pf0_ari_enabled {true} \ CONFIG.pf0_bar0_prefetchable_qdma {true} \ CONFIG.pf0_bar2_prefetchable_qdma {true} \ @@ -271,6 +280,7 @@ proc create_root_design { parentCell } { CONFIG.pf3_device_id {932F} \ CONFIG.pf3_msix_enabled_qdma {false} \ CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X16} \ CONFIG.testname {mm} \ ] $qdma_0 diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 3387c9e73..056f6862c 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,100,16384 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 0959cc4d5..37b714ee9 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,7 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" # RTL include files @@ -499,8 +499,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/baremetal/bootrom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ @@ -694,9 +692,11 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_regs.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_err_slv.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_cdc.sv" \ - "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ ] + + set CHIP_INCLUDE_FILES [list \ ] @@ -809,7 +809,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ - "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.sv" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ @@ -897,7 +897,7 @@ set CHIPSET_INCLUDE_FILES [list \ "${DV_ROOT}/design/chipset/include/uart16550_define.vh" \ "${DV_ROOT}/design/chipset/include/chipset_define.vh" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_define.vh" \ - "${DV_ROOT}/design/chip/tile/ariane/src/common_cells/include/common_cells/registers.svh" + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/include/common_cells/registers.svh" ] set CHIPSET_IP_FILE_PREFIXES [list \ From be5c370ac04af359cd73c5caceec00214a8f3f49 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 31 Oct 2023 10:42:08 -0400 Subject: [PATCH 010/144] [FPGA] Fix latches in L2 and BRAM wrapper --- piton/design/chip/tile/l2/rtl/l2_pipe1_ctrl.v.pyv | 1 + piton/design/common/rtl/bram_1r1w_wrapper.v | 1 + 2 files changed, 2 insertions(+) diff --git a/piton/design/chip/tile/l2/rtl/l2_pipe1_ctrl.v.pyv b/piton/design/chip/tile/l2/rtl/l2_pipe1_ctrl.v.pyv index 5f4ec2376..3122d153a 100644 --- a/piton/design/chip/tile/l2/rtl/l2_pipe1_ctrl.v.pyv +++ b/piton/design/chip/tile/l2/rtl/l2_pipe1_ctrl.v.pyv @@ -3624,6 +3624,7 @@ end always @ * begin + msg_send_data_size_S4 = `MSG_DATA_SIZE_0B; // default send 0 if (msg_send_valid_S4) begin case (msg_send_type_S4) diff --git a/piton/design/common/rtl/bram_1r1w_wrapper.v b/piton/design/common/rtl/bram_1r1w_wrapper.v index 73ddcbe45..210db1dce 100644 --- a/piton/design/common/rtl/bram_1r1w_wrapper.v +++ b/piton/design/common/rtl/bram_1r1w_wrapper.v @@ -115,6 +115,7 @@ always @ * begin // note: DOUT retains value if read enable is not asserted // which is why default value is not set for DOUT + DOUTA=0; // default value if (read_enable_in_reg) begin DOUTA = bram_data_read_out_reg; if (rw_conflict_r) begin From fb3fc4813fb51102d4cad1bc0d30bbb18928b687 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 31 Oct 2023 10:43:13 -0400 Subject: [PATCH 011/144] [FPGA] Update constraints --- piton/design/xilinx/alveou280/constraints.xdc | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc index fbe52f1e9..19e29b9f3 100644 --- a/piton/design/xilinx/alveou280/constraints.xdc +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -17,8 +17,8 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] # 156.25MHz General purpose system clock -set_property PACKAGE_PIN G30 [get_ports chipset_clk_osc_p] -set_property PACKAGE_PIN F30 [get_ports chipset_clk_osc_n] +set_property PACKAGE_PIN BH6 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN BJ6 [get_ports chipset_clk_osc_n] set_property IOSTANDARD LVDS [get_ports chipset_clk*] # Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller @@ -109,14 +109,6 @@ set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]}] create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] -#-------------------------------------------- -# Specifying the placement of PCIe clock domain modules into single SLR to facilitate routing -# https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=386 -#Collecting all units from correspondingly PCIe domain, -#Setting specific SLR to which PCIe pins are wired since placer may miss it if just "group_name" is applied -set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/smartconnect_0] -set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/qdma_0] -set_property USER_SLR_ASSIGNMENT SLR0 [get_cells chipset/chipset_impl/u280_polara_i/polara_i/axi_gpio_0] @@ -283,4 +275,7 @@ set_property PULLDOWN true [get_ports hbm_cattrip] set_false_path -from [get_pins chipset/chipset_impl/u280_polara_i/polara_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells [get_cells -of_objects [get_nets -of_objects [get_pins -hierarchical qdma_0/axi_aclk]]]] + + From 35c2c158ce94004320794709c4ac889e21112daa Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 31 Oct 2023 10:47:08 -0400 Subject: [PATCH 012/144] [FPGA] Update UART IP frequency config --- .../xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci | 6 +++--- .../ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci index 8c27abbec..446f476c3 100644 --- a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci +++ b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci @@ -53,15 +53,15 @@ 0 1 VERSAL_AI_CORE_ES1 - 100000000 + 50000000 1 25000000 25 0 0 16550 - 100000000 - 100 + 50000000 + 50 1 1 uart_16550 diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci index e3bdaecc8..2b46f7650 100644 --- a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -501,7 +501,7 @@ FIFO FIFO virtexuplusHBM - + xilinx.com:au280:part0:1.2 xcu280 fsvh2892 From 39f3a51311fbc63c11186b43b601c53078b8e401 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 14 Nov 2023 10:39:47 -0500 Subject: [PATCH 013/144] Remove old U280 Polara top --- piton/design/chipset/mc/rtl/u280_polara_top.v | 249 ------------------ 1 file changed, 249 deletions(-) delete mode 100644 piton/design/chipset/mc/rtl/u280_polara_top.v diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.v b/piton/design/chipset/mc/rtl/u280_polara_top.v deleted file mode 100644 index 7e27ac496..000000000 --- a/piton/design/chipset/mc/rtl/u280_polara_top.v +++ /dev/null @@ -1,249 +0,0 @@ - -`include "mc_define.h" - -`include "noc_axi4_bridge_define.vh" - -module u280_polara_top ( - - input pcie_refclk_clk_n , - input pcie_refclk_clk_p , - input pcie_perstn , - input [15:0] pci_express_x16_rxn , - input [15:0] pci_express_x16_rxp , - output [15:0] pci_express_x16_txn , - output [15:0] pci_express_x16_txp , - input resetn , - - output c0_ddr4_act_n, - output [16:0] c0_ddr4_adr, - output [1:0] c0_ddr4_ba, - output [1:0] c0_ddr4_bg, - output [0:0] c0_ddr4_ck_c, - output [0:0] c0_ddr4_ck_t, - output [0:0] c0_ddr4_cke, - output [0:0] c0_ddr4_cs_n, - inout [71:0] c0_ddr4_dq, - inout [17:0] c0_ddr4_dqs_c, - inout [17:0] c0_ddr4_dqs_t, - output [0:0] c0_ddr4_odt, - output c0_ddr4_par, - output c0_ddr4_reset_n, - output c0_ddr4_ui_clk_sync_rst, - // Reference clock - input c0_sysclk_clk_n, - input c0_sysclk_clk_p, - // input mc_clk , - // input mc_rstn , - output chip_rstn , - input chipset_clk , - output chipset_rstn , - output c0_init_calib_complete, - - input [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , - input mem_flit_in_val , - output mem_flit_in_rdy , - - output [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , - output mem_flit_out_val , - input mem_flit_out_rdy -); - - - wire trans_fifo_val; - wire [`NOC_DATA_WIDTH-1:0] trans_fifo_data; - wire trans_fifo_rdy; - - wire fifo_trans_val; - wire [`NOC_DATA_WIDTH-1:0] fifo_trans_data; - wire fifo_trans_rdy; - - - noc_bidir_afifo mig_afifo ( - .clk_1 ( chipset_clk ), - .rst_1 ( ~chipset_rstn ), - - .clk_2 ( mc_clk ), - .rst_2 ( mc_rst ), - - // CPU --> MIG - .flit_in_val_1 ( mem_flit_in_val ), - .flit_in_data_1 ( mem_flit_in_data ), - .flit_in_rdy_1 ( mem_flit_in_rdy ), - - .flit_out_val_2 ( fifo_trans_val ), - .flit_out_data_2 ( fifo_trans_data ), - .flit_out_rdy_2 ( fifo_trans_rdy ), - - // MIG --> CPU - .flit_in_val_2 ( trans_fifo_val ), - .flit_in_data_2 ( trans_fifo_data ), - .flit_in_rdy_2 ( trans_fifo_rdy ), - - .flit_out_val_1 ( mem_flit_out_val ), - .flit_out_data_1 ( mem_flit_out_data ), - .flit_out_rdy_1 ( mem_flit_out_rdy ) - ); - - - noc_axi4_bridge noc_axi4_bridge ( - .clk ( mc_clk ), - .rst_n ( ~mc_rst ), - .uart_boot_en ( 1'b0 ), - .phy_init_done ( init_calib_complete ), - - .src_bridge_vr_noc2_val ( fifo_trans_val ), - .src_bridge_vr_noc2_dat ( fifo_trans_data ), - .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), - - .bridge_dst_vr_noc3_val ( trans_fifo_val ), - .bridge_dst_vr_noc3_dat ( trans_fifo_data ), - .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), - - .m_axi_awid ( m_axi_awid ), - .m_axi_awaddr ( m_axi_awaddr ), - .m_axi_awlen ( m_axi_awlen ), - .m_axi_awsize ( m_axi_awsize ), - .m_axi_awburst ( m_axi_awburst ), - .m_axi_awlock ( m_axi_awlock ), - .m_axi_awcache ( m_axi_awcache ), - .m_axi_awprot ( m_axi_awprot ), - .m_axi_awqos ( m_axi_awqos ), - .m_axi_awregion ( m_axi_awregion ), - .m_axi_awuser ( m_axi_awuser ), - .m_axi_awvalid ( m_axi_awvalid ), - .m_axi_awready ( m_axi_awready ), - - .m_axi_wid ( m_axi_wid ), - .m_axi_wdata ( m_axi_wdata ), - .m_axi_wstrb ( m_axi_wstrb ), - .m_axi_wlast ( m_axi_wlast ), - .m_axi_wuser ( m_axi_wuser ), - .m_axi_wvalid ( m_axi_wvalid ), - .m_axi_wready ( m_axi_wready ), - - .m_axi_bid ( m_axi_bid ), - .m_axi_bresp ( m_axi_bresp ), - .m_axi_buser ( m_axi_buser ), - .m_axi_bvalid ( m_axi_bvalid ), - .m_axi_bready ( m_axi_bready ), - - .m_axi_arid ( m_axi_arid ), - .m_axi_araddr ( m_axi_araddr ), - .m_axi_arlen ( m_axi_arlen ), - .m_axi_arsize ( m_axi_arsize ), - .m_axi_arburst ( m_axi_arburst ), - .m_axi_arlock ( m_axi_arlock ), - .m_axi_arcache ( m_axi_arcache ), - .m_axi_arprot ( m_axi_arprot ), - .m_axi_arqos ( m_axi_arqos ), - .m_axi_arregion ( m_axi_arregion ), - .m_axi_aruser ( m_axi_aruser ), - .m_axi_arvalid ( m_axi_arvalid ), - .m_axi_arready ( m_axi_arready ), - - .m_axi_rid ( m_axi_rid), - .m_axi_rdata ( m_axi_rdata ), - .m_axi_rresp ( m_axi_rresp ), - .m_axi_rlast ( m_axi_rlast ), - .m_axi_ruser ( m_axi_ruser ), - .m_axi_rvalid ( m_axi_rvalid ), - .m_axi_rready ( m_axi_rready ) - - ); - - polara_fpga polara_i ( - - .c0_sysclk_clk_p ( c0_sysclk_clk_p ), - .c0_sysclk_clk_n ( c0_sysclk_clk_n ), - .c0_ddr4_ui_clk ( mc_clk ), - .c0_ddr4_ui_clk_sync_rst ( mc_rst ), - .c0_init_calib_complete ( init_calib_complete ), - - - // DDR4 physicall interface - .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 - .c0_ddr4_adr ( c0_ddr4_adr ), - .c0_ddr4_ba ( c0_ddr4_ba ), - .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address - .c0_ddr4_ck_t ( c0_ddr4_ck_t ), - .c0_ddr4_ck_c ( c0_ddr4_ck_c ), - .c0_ddr4_cke ( c0_ddr4_cke ), - .c0_ddr4_cs_n ( c0_ddr4_cs_n ), - .c0_ddr4_dq ( c0_ddr4_dq ), - .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), - .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), - .c0_ddr4_odt ( c0_ddr4_odt ), - .c0_ddr4_par ( c0_ddr4_par ), // output wire c0_ddr4_parity - .c0_ddr4_reset_n ( c0_ddr4_reset_n ), - - // DDR4 control interface, not used, grounded - .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_awvalid - .c0_ddr4_s_axi_ctrl_awready( ), // output wire c0_ddr4_s_axi_ctrl_awready - .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_awaddr - .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_wvalid - .c0_ddr4_s_axi_ctrl_wready ( ), // output wire c0_ddr4_s_axi_ctrl_wready - .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_wdata - .c0_ddr4_s_axi_ctrl_bvalid ( ), // output wire c0_ddr4_s_axi_ctrl_bvalid - .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_bready - .c0_ddr4_s_axi_ctrl_bresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_bresp - .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input wire c0_ddr4_s_axi_ctrl_arvalid - .c0_ddr4_s_axi_ctrl_arready( ), // output wire c0_ddr4_s_axi_ctrl_arready - .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input wire [31 : 0] c0_ddr4_s_axi_ctrl_araddr - .c0_ddr4_s_axi_ctrl_rvalid ( ), // output wire c0_ddr4_s_axi_ctrl_rvalid - .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input wire c0_ddr4_s_axi_ctrl_rready - .c0_ddr4_s_axi_ctrl_rdata ( ), // output wire [31 : 0] c0_ddr4_s_axi_ctrl_rdata - .c0_ddr4_s_axi_ctrl_rresp ( ), // output wire [1 : 0] c0_ddr4_s_axi_ctrl_rresp - - .chip_rstn ( chip_rstn ), - - // AXI4 Memory Interface - .c0_ddr4_s_axi_awid ( m_axi_awid), // input wire [15 : 0] c0_ddr4_s_axi_awid - .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input wire [34 : 0] c0_ddr4_s_axi_awaddr - .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input wire [7 : 0] c0_ddr4_s_axi_awlen - .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input wire [2 : 0] c0_ddr4_s_axi_awsize - .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input wire [1 : 0] c0_ddr4_s_axi_awburst - .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input wire [0 : 0] c0_ddr4_s_axi_awlock - .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input wire [3 : 0] c0_ddr4_s_axi_awcache - .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input wire [2 : 0] c0_ddr4_s_axi_awprot - .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input wire [3 : 0] c0_ddr4_s_axi_awqos - .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input wire c0_ddr4_s_axi_awvalid - .c0_ddr4_s_axi_awready ( m_axi_awready), // output wire c0_ddr4_s_axi_awready - .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input wire [511 : 0] c0_ddr4_s_axi_wdata - .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input wire [63 : 0] c0_ddr4_s_axi_wstrb - .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input wire c0_ddr4_s_axi_wlast - .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input wire c0_ddr4_s_axi_wvalid - .c0_ddr4_s_axi_wready ( m_axi_wready), // output wire c0_ddr4_s_axi_wready - .c0_ddr4_s_axi_bready ( m_axi_bready), // input wire c0_ddr4_s_axi_bready - .c0_ddr4_s_axi_bid ( m_axi_bid), // output wire [15 : 0] c0_ddr4_s_axi_bid - .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output wire [1 : 0] c0_ddr4_s_axi_bresp - .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output wire c0_ddr4_s_axi_bvalid - .c0_ddr4_s_axi_arid ( m_axi_arid), // input wire [15 : 0] c0_ddr4_s_axi_arid - .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input wire [34 : 0] c0_ddr4_s_axi_araddr - .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input wire [7 : 0] c0_ddr4_s_axi_arlen - .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input wire [2 : 0] c0_ddr4_s_axi_arsize - .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input wire [1 : 0] c0_ddr4_s_axi_arburst - .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input wire [0 : 0] c0_ddr4_s_axi_arlock - .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input wire [3 : 0] c0_ddr4_s_axi_arcache - .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input wire [2 : 0] c0_ddr4_s_axi_arprot - .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input wire [3 : 0] c0_ddr4_s_axi_arqos - .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input wire c0_ddr4_s_axi_arvalid - .c0_ddr4_s_axi_arready ( m_axi_arready), // output wire c0_ddr4_s_axi_arready - .c0_ddr4_s_axi_rready ( m_axi_rready), // input wire c0_ddr4_s_axi_rready - .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output wire c0_ddr4_s_axi_rlast - .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output wire c0_ddr4_s_axi_rvalid - .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output wire [1 : 0] c0_ddr4_s_axi_rresp - .c0_ddr4_s_axi_rid ( m_axi_rid), // output wire [15 : 0] c0_ddr4_s_axi_rid - .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output wire [511 : 0] c0_ddr4_s_axi_rdata - - // PCIe - .pci_express_x16_rxn(pci_express_x16_rxn), - .pci_express_x16_rxp(pci_express_x16_rxp), - .pci_express_x16_txn(pci_express_x16_txn), - .pci_express_x16_txp(pci_express_x16_txp), - .pcie_perstn(pcie_perstn), - .pcie_refclk_clk_n(pcie_refclk_clk_n), - .pcie_refclk_clk_p(pcie_refclk_clk_p), - .resetn(resetn) - ); - -endmodule From 04ceb37d745c466ce94159e170be5e33962636f3 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Tue, 14 Nov 2023 15:55:49 -0500 Subject: [PATCH 014/144] [FPGA] Remove debug probes --- .../design/chipset/mc/rtl/u280_polara_top.sv | 25 ------------------- 1 file changed, 25 deletions(-) diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.sv b/piton/design/chipset/mc/rtl/u280_polara_top.sv index cf9823117..1652b9060 100644 --- a/piton/design/chipset/mc/rtl/u280_polara_top.sv +++ b/piton/design/chipset/mc/rtl/u280_polara_top.sv @@ -49,17 +49,6 @@ module u280_polara_top ( input logic mem_flit_out_rdy ); -// ------------------Debug Section----------------- -(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg fifo_trans_rdy_r; -(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg trans_fifo_rdy_r; -/* -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_in_rdy_r; -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_val_r; -(* keep="TRUE", mark_debug="TRUE" *) reg mem_flit_out_rdy_r;*/ - logic mc_rst; logic mc_clk; @@ -309,19 +298,5 @@ module u280_polara_top ( .resetn(resetn) ); -always @(posedge mc_clk) begin : p_debug - fifo_trans_val_r <= fifo_trans_val; - fifo_trans_rdy_r <= fifo_trans_rdy; - trans_fifo_val_r <= trans_fifo_val; - trans_fifo_rdy_r <= trans_fifo_rdy; - -end -/*always@(posedge mc_clk) begin: p_debug - mem_flit_in_val_r <= mem_flit_in_val; - mem_flit_in_rdy_r <= mem_flit_in_rdy; - mem_flit_out_val_r <= mem_flit_out_val; - mem_flit_out_rdy_r <= mem_flit_out_rdy; -end */ - endmodule From bb7c54ee22077d0b994a7665e241bd043b4720d2 Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Mon, 27 Nov 2023 16:41:51 -0500 Subject: [PATCH 015/144] Merge PLIC CLINT to FPGA branch --- piton/design/chip/rtl/chip.v.pyv | 125 ++- .../chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic | 2 + .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv | 822 ++++++++++++++++++ piton/tools/src/sims/manycore.config | 25 + .../diag/c/riscv/ariane/clint_plic_access.c | 57 +- 5 files changed, 1001 insertions(+), 30 deletions(-) create mode 100644 piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic create mode 100644 piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 9f553283c..fb09cc325 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -345,6 +345,26 @@ module chip( wire tiles_jtag_ucb_val; wire [`UCB_BUS_WIDTH-1:0] tiles_jtag_ucb_data; +`ifdef PITON_RV64_PLATFORM +`ifdef PITON_RV64_DEBUGUNIT + // Debug + wire ndmreset; // non-debug module reset + wire [`PITON_NUM_TILES-1:0] debug_req; // async debug request + wire [`PITON_NUM_TILES-1:0] unavailable; // communicate whether the hart is unavailable (e.g.: power down) +`endif // ifdef PITON_RV64_DEBUGUNIT + +`ifdef PITON_RV64_CLINT + // CLINT + wire [`PITON_NUM_TILES-1:0] timer_irq; // Timer interrupts + wire [`PITON_NUM_TILES-1:0] ipi; // software interrupt (a.k.a inter-process-interrupt) +`endif // ifdef PITON_RV64_CLINT + +`ifdef PITON_RV64_PLIC + // PLIC + wire [`PITON_NUM_TILES*2-1:0] irq; // level sensitive IR lines, mip & sip (async) +`endif // ifdef PITON_RV64_PLIC +`endif // ifdef PITON_RV64_PLATFORM + // Tiles JTAG interface wire jtag_tiles_ucb_val; wire [`UCB_BUS_WIDTH-1:0] jtag_tiles_ucb_data; @@ -436,6 +456,35 @@ module chip( print("wire offchip_out_E_noc%d_yummy;" % (k)) %> + // make some PLIC, CLINT, debug unit signals + wire [`DATA_WIDTH-1:0] rvic_out_S_noc1_data = `DATA_WIDTH'b0; + wire rvic_out_S_noc1_valid = 1'b0; + wire rvic_out_S_noc1_yummy; + wire [`DATA_WIDTH-1:0] rvic_out_S_noc2_data; + wire rvic_out_S_noc2_valid; + wire rvic_out_S_noc2_yummy; + wire [`DATA_WIDTH-1:0] rvic_out_S_noc3_data = `DATA_WIDTH'b0; + wire rvic_out_S_noc3_valid = 1'b0; + wire rvic_out_S_noc3_yummy = 1'b0; + wire [`DATA_WIDTH-1:0] clint_out_S_noc1_data = `DATA_WIDTH'b0; + wire clint_out_S_noc1_valid = 1'b0; + wire clint_out_S_noc1_yummy; + wire [`DATA_WIDTH-1:0] clint_out_S_noc2_data; + wire clint_out_S_noc2_valid; + wire clint_out_S_noc2_yummy; + wire [`DATA_WIDTH-1:0] clint_out_S_noc3_data = `DATA_WIDTH'b0; + wire clint_out_S_noc3_valid = 1'b0; + wire clint_out_S_noc3_yummy = 1'b0; + wire [`DATA_WIDTH-1:0] debug_out_W_noc1_data = `DATA_WIDTH'b0; + wire debug_out_S_noc1_valid = 1'b0; + wire debug_out_S_noc1_yummy = 1'b0; + wire [`DATA_WIDTH-1:0] debug_out_W_noc2_data; + wire debug_out_S_noc2_valid; + wire debug_out_S_noc2_yummy; + wire [`DATA_WIDTH-1:0] debug_out_W_noc3_data = `DATA_WIDTH'b0; + wire debug_out_S_noc3_valid = 1'b0; + wire debug_out_S_noc3_yummy = 1'b0; + ////////////////////// // Sequential logic ////////////////////// @@ -1169,7 +1218,12 @@ module chip( # special case for core 0 if i == 0 and j == 0: idW = "offchip" - idN = "dummy" + idN = "rvic" + + # special case for core 1 + if i == 1 and j == 0: + idN = "clint" + # idE = "debug" currenttile = currenttile.replace("in_N", idN + "_out_S"); currenttile = currenttile.replace("in_S", idS + "_out_N"); @@ -1180,6 +1234,75 @@ module chip( print(currenttile) # print "`endif" %> + +// RTC generator +reg [13:0] rtc_divider = 14'b00000000000000; + +always @(posedge clk_muxed) begin + rtc_divider <= rtc_divider + 1; + if (rtc_divider == 16384) begin + rtc_divider <= 0; + end +end +assign rtc = rtc_divider[13]; + + +pmesh_rvic pmesh_rvic ( + .clk ( clk_muxed ), + .rst_n ( rst_n_inter_sync ), + + // Interrupt status is received from noc2 + .src_rvic_cr_noc2_val ( tile_0_0_out_N_noc2_valid ), + .src_rvic_cr_noc2_dat ( tile_0_0_out_N_noc2_data ), + .src_rvic_cr_noc2_yum ( rvic_out_S_noc2_yummy ), + + // input from noc1 (load/store to RVIC) + .src_rvic_cr_noc1_val ( tile_0_0_out_N_noc1_valid ), + .src_rvic_cr_noc1_dat ( tile_0_0_out_N_noc1_data ), + .src_rvic_cr_noc1_yum ( rvic_out_S_noc1_yummy ), + + // output to noc2 (load/store response) + .rvic_dst_cr_noc2_val ( rvic_out_S_noc2_valid ), + .rvic_dst_cr_noc2_dat ( rvic_out_S_noc2_data ), + .rvic_dst_cr_noc2_yum ( tile_0_0_out_N_noc2_yummy ), + + // Interrupt targets go to core + .irq_targets ( irq ), + + // CLINT + .src_clint_cr_noc1_val ( tile_0_1_out_N_noc1_valid ), + .src_clint_cr_noc1_dat ( tile_0_1_out_N_noc1_data ), + .src_clint_cr_noc1_yum ( clint_out_S_noc1_yummy ), + + .clint_dst_cr_noc2_val ( clint_out_S_noc2_valid ), + .clint_dst_cr_noc2_dat ( clint_out_S_noc2_data ), + .clint_dst_cr_noc2_yum ( tile_0_1_out_N_noc2_yummy ), + + .rtc_i ( rtc ), // Real-time clock in (usually 32.768 kHz) + .timer_irq_o ( timer_irq ), // Timer interrupts + .ipi_o ( ipi ), // software interrupt (a.k.a inter-process-interrupt) + + // Debug unit + .src_debug_cr_noc1_val ( tile_0_1_out_E_noc1_valid ), + .src_debug_cr_noc1_dat ( tile_0_1_out_E_noc1_data ), + .src_debug_cr_noc1_yum ( tile_0_1_out_E_noc1_yummy ), + + .debug_dst_cr_noc2_val ( debug_out_W_noc2_valid ), + .debug_dst_cr_noc2_dat ( debug_out_W_noc2_data ), + .debug_dst_cr_noc2_yum ( debug_out_W_noc2_yummy ), + + .ndmreset_o ( ), // not used + .dmactive_o ( ), // not used + .debug_req_o ( debug_req ), + .unavailable_i ( unavailable ), + .tck_i ( jtag_clk_inter ), + .tms_i ( jtag_rst_l_inter ), + .trst_ni ( jtag_modesel_inter ), + .td_i ( jtag_datain_inter ), + .td_o ( jtag_dataout_inter ), + .tdo_oe_o ( ) // not used +); + endmodule `endif diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic b/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic new file mode 100644 index 000000000..dd6bc1924 --- /dev/null +++ b/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic @@ -0,0 +1,2 @@ +pmesh_rvic.sv +rvic_wrap.sv diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv new file mode 100644 index 000000000..e5c89b8df --- /dev/null +++ b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv @@ -0,0 +1,822 @@ +// Copyright (c) 2020 Princeton University +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of Princeton University nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +`include "l15.tmp.h" +`include "define.tmp.h" + +module pmesh_rvic #( + parameter integer NUM_SOURCES = 16, + parameter integer NUM_HARTS = 4, + parameter integer MAX_PRIORITY = 7, + parameter CLINT_BASE = 64'he110500000, // north of the northeast tile + parameter PLIC_BASE = 64'he200000000, // north of the northwest tile + parameter DEBUG_BASE = 64'he110400000, // east of the northeast tile + parameter SWAP_ENDIANESS = 1 +) ( + input clk, + input rst_n, + + // PLIC + + // Interrupt status is received from noc2 + input src_rvic_cr_noc2_val, + input [`NOC_DATA_WIDTH-1:0] src_rvic_cr_noc2_dat, + output src_rvic_cr_noc2_yum, + + // input from noc1 (load/store to PLIC) + input src_rvic_cr_noc1_val, + input [`NOC_DATA_WIDTH-1:0] src_rvic_cr_noc1_dat, + output src_rvic_cr_noc1_yum, + + // output to noc2 (load/store PLIC response) + output rvic_dst_cr_noc2_val, + output [`NOC_DATA_WIDTH-1:0] rvic_dst_cr_noc2_dat, + input rvic_dst_cr_noc2_yum, + + // Interrupt targets go to core + output [NUM_HARTS*2-1:0] irq_targets, + + // CLINT + // input from noc1 (load/store to CLINT) + input src_clint_cr_noc1_val, + input [`NOC_DATA_WIDTH-1:0] src_clint_cr_noc1_dat, + output src_clint_cr_noc1_yum, + + // output to noc2 (load/store CLINT response) + output clint_dst_cr_noc2_val, + output [`NOC_DATA_WIDTH-1:0] clint_dst_cr_noc2_dat, + input clint_dst_cr_noc2_yum, + + input rtc_i, // Real-time clock in (usually 32.768 kHz) + output [NUM_HARTS-1:0] timer_irq_o, // Timer interrupts + output [NUM_HARTS-1:0] ipi_o, // software interrupt (a.k.a inter-process-interrupt) + + // Debug unit + // input from noc1 (load/store to debug unit) + input src_debug_cr_noc1_val, + input [`NOC_DATA_WIDTH-1:0] src_debug_cr_noc1_dat, + output src_debug_cr_noc1_yum, + + // output to noc2 (load/store debug unit response) + output debug_dst_cr_noc2_val, + output [`NOC_DATA_WIDTH-1:0] debug_dst_cr_noc2_dat, + input debug_dst_cr_noc2_yum, + + // Debug sigs to cores + output ndmreset_o, // non-debug module reset + output dmactive_o, // debug module is active + output [NUM_HARTS-1:0] debug_req_o, // async debug request + input [NUM_HARTS-1:0] unavailable_i, // communicate whether the hart is unavailable (e.g.: power down) + + // JTAG + input tck_i, + input tms_i, + input trst_ni, + input td_i, + output td_o, + output tdo_oe_o +); + +// Interrupt status is received from noc2 +wire src_rvic_vr_noc2_val; +wire [`NOC_DATA_WIDTH-1:0] src_rvic_vr_noc2_dat; +wire src_rvic_vr_noc2_rdy; + +// input from noc1 (load/store to PLIC) +wire src_rvic_vr_noc1_val; +wire [`NOC_DATA_WIDTH-1:0] src_rvic_vr_noc1_dat; +wire src_rvic_vr_noc1_rdy; + +// output to noc2 (load/store PLIC response) +wire rvic_dst_vr_noc2_val; +wire [`NOC_DATA_WIDTH-1:0] rvic_dst_vr_noc2_dat; +wire rvic_dst_vr_noc2_rdy; + +// CLINT +// input from noc1 (load/store to CLINT) +wire src_clint_vr_noc1_val; +wire [`NOC_DATA_WIDTH-1:0] src_clint_vr_noc1_dat; +wire src_clint_vr_noc1_rdy; + +// output to noc2 (load/store CLINT response) +wire clint_dst_vr_noc2_val; +wire [`NOC_DATA_WIDTH-1:0] clint_dst_vr_noc2_dat; +wire clint_dst_vr_noc2_rdy; + +// Debug unit +// input from noc1 (load/store to debug unit) +wire src_debug_vr_noc1_val; +wire [`NOC_DATA_WIDTH-1:0] src_debug_vr_noc1_dat; +wire src_debug_vr_noc1_rdy; + +// output to noc2 (load/store debug unit response) +wire debug_dst_vr_noc2_val; +wire [`NOC_DATA_WIDTH-1:0] debug_dst_vr_noc2_dat; +wire debug_dst_vr_noc2_rdy; + +credit_to_valrdy src_rvic_noc2_c2v( + .clk (clk), + .reset (~rst_n), + .data_in (src_rvic_cr_noc2_dat), + .valid_in (src_rvic_cr_noc2_val), + .yummy_in (src_rvic_cr_noc2_yum), + + .data_out (src_rvic_vr_noc2_dat), + .valid_out (src_rvic_vr_noc2_val), + .ready_out (src_rvic_vr_noc2_rdy) +); + +credit_to_valrdy src_rvic_noc1_c2v( + .clk (clk), + .reset (~rst_n), + .data_in (src_rvic_cr_noc1_dat), + .valid_in (src_rvic_cr_noc1_val), + .yummy_in (src_rvic_cr_noc1_yum), + + .data_out (src_rvic_vr_noc1_dat), + .valid_out (src_rvic_vr_noc1_val), + .ready_out (src_rvic_vr_noc1_rdy) +); + +valrdy_to_credit #(4, 3) rvic_dst_noc2_v2c( + .clk (clk), + .reset (~rst_n), + .data_in (rvic_dst_vr_noc2_dat), + .valid_in (rvic_dst_vr_noc2_val), + .ready_in (rvic_dst_vr_noc2_rdy), + + .data_out (rvic_dst_cr_noc2_dat), + .valid_out (rvic_dst_cr_noc2_val), + .yummy_out (rvic_dst_cr_noc2_yum) +); + +credit_to_valrdy src_clint_noc1_c2v( + .clk (clk), + .reset (~rst_n), + .data_in (src_clint_cr_noc1_dat), + .valid_in (src_clint_cr_noc1_val), + .yummy_in (src_clint_cr_noc1_yum), + + .data_out (src_clint_vr_noc1_dat), + .valid_out (src_clint_vr_noc1_val), + .ready_out (src_clint_vr_noc1_rdy) +); + +valrdy_to_credit #(4, 3) clint_dst_noc2_v2c( + .clk (clk), + .reset (~rst_n), + .data_in (clint_dst_vr_noc2_dat), + .valid_in (clint_dst_vr_noc2_val), + .ready_in (clint_dst_vr_noc2_rdy), + + .data_out (clint_dst_cr_noc2_dat), + .valid_out (clint_dst_cr_noc2_val), + .yummy_out (clint_dst_cr_noc2_yum) +); + +credit_to_valrdy src_debug_noc1_c2v( + .clk (clk), + .reset (~rst_n), + .data_in (src_debug_cr_noc1_dat), + .valid_in (src_debug_cr_noc1_val), + .yummy_in (src_debug_cr_noc1_yum), + + .data_out (src_debug_vr_noc1_dat), + .valid_out (src_debug_vr_noc1_val), + .ready_out (src_debug_vr_noc1_rdy) +); + +valrdy_to_credit #(4, 3) debug_dst_noc2_v2c( + .clk (clk), + .reset (~rst_n), + .data_in (debug_dst_vr_noc2_dat), + .valid_in (debug_dst_vr_noc2_val), + .ready_in (debug_dst_vr_noc2_rdy), + + .data_out (debug_dst_cr_noc2_dat), + .valid_out (debug_dst_cr_noc2_val), + .yummy_out (debug_dst_cr_noc2_yum) +); + + +wire [511:0] noc2_data; +wire noc2_data_val; +wire noc2_data_ack; + +simplenocbuffer simplenocbuffer( + .clk(clk), + .rst_n(rst_n), + .noc_in_val(src_rvic_vr_noc2_val), + .noc_in_data(src_rvic_vr_noc2_dat), + .msg_ack(noc2_data_ack), + .noc_in_rdy(src_rvic_vr_noc2_rdy), + .msg(noc2_data), + .msg_val(noc2_data_val) +); + +wire l15_noc2decoder_ack; +wire l15_noc2decoder_header_ack; +wire noc2decoder_l15_val; +wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; +wire noc2decoder_l15_l2miss; +wire noc2decoder_l15_icache_type; +wire noc2decoder_l15_f4b; +wire [`MSG_TYPE_WIDTH-1:0] noc2decoder_l15_reqtype; +wire [`L15_MESI_STATE_WIDTH-1:0] noc2decoder_l15_ack_state; +wire [63:0] noc2decoder_l15_data_0; +wire [63:0] noc2decoder_l15_data_1; +wire [63:0] noc2decoder_l15_data_2; +wire [63:0] noc2decoder_l15_data_3; +wire [`L15_PADDR_HI:0] noc2decoder_l15_address; +wire [3:0] noc2decoder_l15_fwd_subcacheline_vector; +wire [`PACKET_HOME_ID_WIDTH-1:0] noc2decoder_l15_src_homeid; + +wire [`L15_CSM_NUM_TICKETS_LOG2-1:0] noc2decoder_l15_csm_mshrid; +wire [`L15_THREADID_MASK] noc2decoder_l15_threadid; +wire noc2decoder_l15_hmc_fill; + +/* + noc2decoder takes the data from the buffer and decode it to meaningful signals + to the l15 +*/ +noc2decoder noc2decoder( + .clk(clk), + .rst_n(rst_n), + .noc2_data(noc2_data), + .noc2_data_val(noc2_data_val), + .l15_noc2decoder_ack(l15_noc2decoder_ack), + .l15_noc2decoder_header_ack(l15_noc2decoder_header_ack), + .noc2_data_ack(noc2_data_ack), + .noc2decoder_l15_val(noc2decoder_l15_val), + .noc2decoder_l15_mshrid(noc2decoder_l15_mshrid), + .noc2decoder_l15_l2miss(noc2decoder_l15_l2miss), + .noc2decoder_l15_icache_type(noc2decoder_l15_icache_type), + .noc2decoder_l15_f4b(noc2decoder_l15_f4b), + .noc2decoder_l15_reqtype(noc2decoder_l15_reqtype), + .noc2decoder_l15_ack_state(noc2decoder_l15_ack_state), + .noc2decoder_l15_data_0(noc2decoder_l15_data_0), + .noc2decoder_l15_data_1(noc2decoder_l15_data_1), + .noc2decoder_l15_data_2(noc2decoder_l15_data_2), + .noc2decoder_l15_data_3(noc2decoder_l15_data_3), + .noc2decoder_l15_address(noc2decoder_l15_address), + .noc2decoder_l15_fwd_subcacheline_vector(noc2decoder_l15_fwd_subcacheline_vector), + .noc2decoder_l15_src_homeid(noc2decoder_l15_src_homeid), + .noc2decoder_l15_csm_mshrid(noc2decoder_l15_csm_mshrid), + .noc2decoder_l15_threadid(noc2decoder_l15_threadid), + .noc2decoder_l15_hmc_fill(noc2decoder_l15_hmc_fill), + .l15_dmbr_l2missIn(), + .l15_dmbr_l2missTag(), + .l15_dmbr_l2responseIn() +); + +reg new_edge_irq; +reg new_edge_irq_next; + +reg [NUM_SOURCES:0] lev_or_edge; +reg [NUM_SOURCES:0] lev_or_edge_next; +reg [NUM_SOURCES:0] irq_sources; +reg [NUM_SOURCES:0] irq_sources_next; + +reg [6:0] most_recent_source; +reg [6:0] most_recent_source_next; + +reg [9:0] source_id_field; + +// flit2: +// 63 1 +// 59:56 source id bit [9:6], for decades, only use bit[6:0] +// 33:26 ypos +// 25:18 xpos +// 17:16 type +// 15:9 0 +// 8 threadid +// 7 0:level, 1:edge +// 6 0:rising, 1:falling +// 5:0 source id bit [5:0] +// Read from the l15 message +// for edge-sensitive or rising edge of level-sensitive, +// the next cycle of that interrupt should be high. +// The edge sensitive interrupt will automatically return to 0 after 1 cycle +always @* begin + new_edge_irq_next = 1'b0; + most_recent_source_next = most_recent_source; + irq_sources_next = irq_sources; + lev_or_edge_next = lev_or_edge; + source_id_field = 10'b0; + if (noc2decoder_l15_val && (noc2decoder_l15_reqtype == `MSG_TYPE_INTERRUPT) && ~new_edge_irq && (noc2decoder_l15_data_0[17:16] == 2'b0)) begin + // Comebine the source id together + source_id_field = {noc2decoder_l15_data_0[59:56], noc2decoder_l15_data_0[5:0]}; + // Either level sensitive edge or rising edge of edge sensitive pulse + new_edge_irq_next = noc2decoder_l15_data_0[7]; + most_recent_source_next = source_id_field[6:0]; + irq_sources_next[source_id_field[6:0]] = noc2decoder_l15_data_0[7] | (~noc2decoder_l15_data_0[7] & ~noc2decoder_l15_data_0[6]); // edge-sensitive or rising edge of level-sensitive + lev_or_edge_next[source_id_field[6:0]] = noc2decoder_l15_data_0[7]; + end else if (new_edge_irq) begin + // Edge sensitive automatic falling edge of pulse + most_recent_source_next = 7'b0; + irq_sources_next[most_recent_source] = 1'b0; + end +end + +always @(posedge clk) begin + if (~rst_n) begin + new_edge_irq <= 1'b0; + most_recent_source <= 7'b0; + end else begin + new_edge_irq <= new_edge_irq_next; + most_recent_source <= most_recent_source_next; + end +end + +always @(posedge clk) begin + if (~rst_n) begin + irq_sources <= {NUM_SOURCES+1{1'b0}}; + lev_or_edge <= {NUM_SOURCES+1{1'b0}}; + end else begin + irq_sources <= irq_sources_next; + lev_or_edge <= lev_or_edge_next; + end +end + +wire [63:0] aw_addr; +wire aw_valid; +wire aw_ready; +wire [63:0] w_data; +wire [7:0] w_strb; +wire w_valid; +wire w_ready; +wire [63:0] ar_addr; +wire ar_valid; +wire ar_ready; +wire [63:0] r_data; +wire [1:0] r_resp; +wire r_valid; +wire r_ready; +wire [1:0] b_resp; +wire b_valid; +wire b_ready; +wire [2:0] aw_size; +wire [2:0] ar_size; + +wire [63:0] clint_aw_addr; +wire clint_aw_valid; +wire clint_aw_ready; +wire [63:0] clint_w_data; +wire [7:0] clint_w_strb; +wire clint_w_valid; +wire clint_w_ready; +wire [63:0] clint_ar_addr; +wire clint_ar_valid; +wire clint_ar_ready; +wire [63:0] clint_r_data; +wire [1:0] clint_r_resp; +wire clint_r_valid; +wire clint_r_ready; +wire [1:0] clint_b_resp; +wire clint_b_valid; +wire clint_b_ready; + +// Fake int for testing +// parameter OK_INT_CNT = 40000; +// reg [63:0] int_cnt; +// wire int_sent; +// reg fake_int; +// assign int_sent = int_cnt == OK_INT_CNT; +// +// always @(posedge clk) begin +// if (~rst_n) begin +// int_cnt <= 32'b0; +// fake_int <= 1'b0; +// end +// else begin +// int_cnt <= int_sent ? int_cnt : int_cnt + 1'b1 ; +// //fake_int <= ( (int_cnt == OK_INT_CNT-2) || (int_cnt == OK_INT_CNT-1) ) ? ~fake_int : fake_int; +// fake_int <= (int_cnt == OK_INT_CNT-1) ? ~fake_int : fake_int; +// end +// end + + + +noc_axilite_bridge #( + // this enables variable width accesses + // note that the accesses are still 64bit, but the + // write-enables are generated according to the access size + .SLAVE_RESP_BYTEWIDTH ( 0 ), + .SWAP_ENDIANESS ( SWAP_ENDIANESS ), + // this disables shifting of unaligned read data + .ALIGN_RDATA ( 0 ) +) rvic_axilite_bridge ( + .clk ( clk ), + .rst ( ~rst_n ), + // to/from NOC + .splitter_bridge_val ( src_rvic_vr_noc1_val ), + .splitter_bridge_data ( src_rvic_vr_noc1_dat ), + .bridge_splitter_rdy ( src_rvic_vr_noc1_rdy ), + .bridge_splitter_val ( rvic_dst_vr_noc2_val ), + .bridge_splitter_data ( rvic_dst_vr_noc2_dat ), + .splitter_bridge_rdy ( rvic_dst_vr_noc2_rdy ), + //axi lite signals + //write address channel + .m_axi_awaddr ( aw_addr ), + .m_axi_awvalid ( aw_valid ), + .m_axi_awready ( aw_ready ), + //write data channel + .m_axi_wdata ( w_data ), + .m_axi_wstrb ( w_strb ), + .m_axi_wvalid ( w_valid ), + .m_axi_wready ( w_ready ), + //read address channel + .m_axi_araddr ( ar_addr ), + .m_axi_arvalid ( ar_valid ), + .m_axi_arready ( ar_ready ), + //read data channel + .m_axi_rdata ( r_data ), + .m_axi_rresp ( r_resp ), + .m_axi_rvalid ( r_valid ), + .m_axi_rready ( r_ready ), + //write response channel + .m_axi_bresp ( b_resp ), + .m_axi_bvalid ( b_valid ), + .m_axi_bready ( b_ready ), + // non-axi-lite signals + .w_reqbuf_size ( aw_size ), + .r_reqbuf_size ( ar_size ) +); + +// CLINT +noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 8 ), + .SWAP_ENDIANESS ( SWAP_ENDIANESS ) +) i_clint_axilite_bridge ( + .clk ( clk ), + .rst ( ~rst_n ), + // to/from NOC + .splitter_bridge_val ( src_clint_vr_noc1_val ), + .splitter_bridge_data ( src_clint_vr_noc1_dat ), + .bridge_splitter_rdy ( src_clint_vr_noc1_rdy ), + .bridge_splitter_val ( clint_dst_vr_noc2_val ), + .bridge_splitter_data ( clint_dst_vr_noc2_dat ), + .splitter_bridge_rdy ( clint_dst_vr_noc2_rdy ), + //axi lite signals + //write address channel + .m_axi_awaddr ( clint_aw_addr ), + .m_axi_awvalid ( clint_aw_valid ), + .m_axi_awready ( clint_aw_ready ), + //write data channel + .m_axi_wdata ( clint_w_data ), + .m_axi_wstrb ( clint_w_strb ), + .m_axi_wvalid ( clint_w_valid ), + .m_axi_wready ( clint_w_ready ), + //read address channel + .m_axi_araddr ( clint_ar_addr ), + .m_axi_arvalid ( clint_ar_valid ), + .m_axi_arready ( clint_ar_ready ), + //read data channel + .m_axi_rdata ( clint_r_data ), + .m_axi_rresp ( clint_r_resp ), + .m_axi_rvalid ( clint_r_valid ), + .m_axi_rready ( clint_r_ready ), + //write response channel + .m_axi_bresp ( clint_b_resp ), + .m_axi_bvalid ( clint_b_valid ), + .m_axi_bready ( clint_b_ready ), + // non-axi-lite signals + .w_reqbuf_size ( ), + .r_reqbuf_size ( ) + ); + + +rvic_wrap #( + .NumSources ( NUM_SOURCES ), + .NumHarts ( NUM_HARTS ), + .PlicMaxPriority ( MAX_PRIORITY ), + .ClintBase ( CLINT_BASE ), + .PlicBase ( PLIC_BASE ) +) rvic_wrap ( + .clk ( clk ), + .rst_n ( rst_n ), + //axi lite signals + .axi_awaddr ( aw_addr ), + .axi_awvalid ( aw_valid ), + .axi_awready ( aw_ready ), + .axi_wdata ( w_data ), + .axi_wstrb ( w_strb ), + .axi_wvalid ( w_valid ), + .axi_wready ( w_ready ), + .axi_araddr ( ar_addr ), + .axi_arvalid ( ar_valid ), + .axi_arready ( ar_ready ), + .axi_rdata ( r_data ), + .axi_rresp ( r_resp ), + .axi_rvalid ( r_valid ), + .axi_rready ( r_ready ), + .axi_bresp ( b_resp ), + .axi_bvalid ( b_valid ), + .axi_bready ( b_ready ), + .w_reqbuf_size ( aw_size ), + .r_reqbuf_size ( ar_size ), + + // clint axi lite signals + .clint_axi_awaddr ( clint_aw_addr ), + .clint_axi_awvalid ( clint_aw_valid ), + .clint_axi_awready ( clint_aw_ready ), + .clint_axi_wdata ( clint_w_data ), + .clint_axi_wstrb ( clint_w_strb ), + .clint_axi_wvalid ( clint_w_valid ), + .clint_axi_wready ( clint_w_ready ), + .clint_axi_araddr ( clint_ar_addr ), + .clint_axi_arvalid ( clint_ar_valid ), + .clint_axi_arready ( clint_ar_ready ), + .clint_axi_rdata ( clint_r_data ), + .clint_axi_rresp ( clint_r_resp ), + .clint_axi_rvalid ( clint_r_valid ), + .clint_axi_rready ( clint_r_ready ), + .clint_axi_bresp ( clint_b_resp ), + .clint_axi_bvalid ( clint_b_valid ), + .clint_axi_bready ( clint_b_ready ), + + .irq_sources_i ( irq_sources[NUM_SOURCES:1] ), // already synchronized + .irq_le_i ( lev_or_edge_next[NUM_SOURCES:1] ), // 0:level 1:edge, bypass from reg + .irq_o ( irq_targets ), + + .testmode_i ( 1'b0 ), // Not Sure: tie this to 1'b0 for using clint + + .rtc_i ( rtc_i ), // Real-time clock in (usually 32.768 kHz) + .timer_irq_o ( timer_irq_o ), // Timer interrupts + .ipi_o ( ipi_o ) // software interrupt (a.k.a inter-process-interrupt) +); + + + ///////////////////////////// + // Debug module and JTAG + ///////////////////////////// + localparam AxiIdWidth = 1; + localparam AxiAddrWidth = 64; + localparam AxiDataWidth = 64; + localparam AxiUserWidth = 1; + + wire debug_req_valid; + wire debug_req_ready; + wire debug_resp_valid; + wire debug_resp_ready; + + dm::dmi_req_t debug_req; + dm::dmi_resp_t debug_resp; + +`ifdef RISCV_FESVR_SIM + + initial begin + $display("[INFO] instantiating FESVR DTM in simulation."); + end + + // SiFive's SimDTM Module + // Converts to DPI calls + wire [31:0] sim_exit; // TODO: wire this up in the testbench + wire [1:0] debug_req_bits_op; + assign dmi_req.op = dm::dtm_op_t'(debug_req_bits_op); + + SimDTM i_SimDTM ( + .clk ( clk_i ), + .reset ( ~rst_ni ), + .debug_req_valid ( debug_req_valid ), + .debug_req_ready ( debug_req_ready ), + .debug_req_bits_addr ( debug_req.addr ), + .debug_req_bits_op ( debug_req_bits_op ), + .debug_req_bits_data ( debug_req.data ), + .debug_resp_valid ( debug_resp_valid ), + .debug_resp_ready ( debug_resp_ready ), + .debug_resp_bits_resp ( debug_resp.resp ), + .debug_resp_bits_data ( debug_resp.data ), + .exit ( sim_exit ) + ); + +`else // RISCV_FESVR_SIM + + wire tck, tms, trst_n, tdi, tdo, tdo_oe; + + dmi_jtag i_dmi_jtag ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .testmode_i ( 1'b0 ), + .dmi_req_o ( debug_req ), + .dmi_req_valid_o ( debug_req_valid ), + .dmi_req_ready_i ( debug_req_ready ), + .dmi_resp_i ( debug_resp ), + .dmi_resp_ready_o ( debug_resp_ready ), + .dmi_resp_valid_i ( debug_resp_valid ), + .dmi_rst_no ( ), // not connected + .tck_i ( tck ), + .tms_i ( tms ), + .trst_ni ( trst_n ), + .td_i ( tdi ), + .td_o ( tdo ), + .tdo_oe_o ( tdo_oe ) + ); + +`ifdef RISCV_JTAG_SIM + + initial begin + $display("[INFO] instantiating JTAG DTM in simulation."); + end + + // SiFive's SimJTAG Module + // Converts to DPI calls + wire [31:0] sim_exit; // TODO: wire this up in the testbench + SimJTAG i_SimJTAG ( + .clock ( clk_i ), + .reset ( ~rst_ni ), + .enable ( jtag_enable[0] ), + .init_done ( init_done ), + .jtag_TCK ( tck ), + .jtag_TMS ( tms ), + .jtag_TDI ( trst_n ), + .jtag_TRSTn ( td ), + .jtag_TDO_data ( td ), + .jtag_TDO_driven ( tdo_oe ), + .exit ( sim_exit ) + ); + + assign td_o = 1'b0 ; + assign tdo_oe_o = 1'b0 ; + +`else // RISCV_JTAG_SIM + + assign tck = tck_i ; + assign tms = tms_i ; + assign trst_n = trst_ni ; + assign tdi = td_i ; + assign td_o = tdo ; + assign tdo_oe_o = tdo_oe ; + +`endif // RISCV_JTAG_SIM +`endif // RISCV_FESVR_SIM + + wire dm_slave_req; + wire dm_slave_we; + wire [64-1:0] dm_slave_addr; + wire [64/8-1:0] dm_slave_be; + wire [64-1:0] dm_slave_wdata; + wire [64-1:0] dm_slave_rdata; + + wire dm_master_req; + wire [64-1:0] dm_master_add; + wire dm_master_we; + wire [64-1:0] dm_master_wdata; + wire [64/8-1:0] dm_master_be; + wire dm_master_gnt; + wire dm_master_r_valid; + wire [64-1:0] dm_master_r_rdata; + + // debug module + dm_top #( + .NrHarts ( NUM_HARTS ), + .BusWidth ( AxiDataWidth ), + .SelectableHarts ( {NUM_HARTS{1'b1}} ) + ) i_dm_top ( + .clk_i ( clk ), + .rst_ni ( rst_n ), // PoR + .testmode_i ( 1'b0 ), + .ndmreset_o ( ), + .dmactive_o ( ), // active debug session + .debug_req_o ( debug_req_o ), + .unavailable_i ( unavailable_i ), + .hartinfo_i ( {NUM_HARTS{ariane_pkg::DebugHartInfo}} ), + .slave_req_i ( dm_slave_req ), + .slave_we_i ( dm_slave_we ), + .slave_addr_i ( dm_slave_addr ), + .slave_be_i ( dm_slave_be ), + .slave_wdata_i ( dm_slave_wdata ), + .slave_rdata_o ( dm_slave_rdata ), + .master_req_o ( dm_master_req ), + .master_add_o ( dm_master_add ), + .master_we_o ( dm_master_we ), + .master_wdata_o ( dm_master_wdata ), + .master_be_o ( dm_master_be ), + .master_gnt_i ( dm_master_gnt ), + .master_r_valid_i ( dm_master_r_valid ), + .master_r_rdata_i ( dm_master_r_rdata ), + .dmi_rst_ni ( rst_ni ), + .dmi_req_valid_i ( debug_req_valid ), + .dmi_req_ready_o ( debug_req_ready ), + .dmi_req_i ( debug_req ), + .dmi_resp_valid_o ( debug_resp_valid ), + .dmi_resp_ready_i ( debug_resp_ready ), + .dmi_resp_o ( debug_resp ) + ); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) dm_master(); + + axi2mem #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) i_dm_axi2mem ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slave ( dm_master ), + .req_o ( dm_slave_req ), + .we_o ( dm_slave_we ), + .addr_o ( dm_slave_addr ), + .be_o ( dm_slave_be ), + .data_o ( dm_slave_wdata ), + .data_i ( dm_slave_rdata ) + ); + + noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 8 ), + .SWAP_ENDIANESS ( SWAP_ENDIANESS ) + ) i_debug_axilite_bridge ( + .clk ( clk_i ), + .rst ( ~rst_ni ), + // to/from NOC + .splitter_bridge_val ( src_debug_vr_noc1_val ), + .splitter_bridge_data ( src_debug_vr_noc1_dat ), + .bridge_splitter_rdy ( src_debug_vr_noc1_rdy ), + .bridge_splitter_val ( debug_dst_vr_noc2_val ), + .bridge_splitter_data ( debug_dst_vr_noc2_dat ), + .splitter_bridge_rdy ( debug_dst_vr_noc2_rdy ), + //axi lite signals + //write address channel + .m_axi_awaddr ( dm_master.aw_addr ), + .m_axi_awvalid ( dm_master.aw_valid ), + .m_axi_awready ( dm_master.aw_ready ), + //write data channel + .m_axi_wdata ( dm_master.w_data ), + .m_axi_wstrb ( dm_master.w_strb ), + .m_axi_wvalid ( dm_master.w_valid ), + .m_axi_wready ( dm_master.w_ready ), + //read address channel + .m_axi_araddr ( dm_master.ar_addr ), + .m_axi_arvalid ( dm_master.ar_valid ), + .m_axi_arready ( dm_master.ar_ready ), + //read data channel + .m_axi_rdata ( dm_master.r_data ), + .m_axi_rresp ( dm_master.r_resp ), + .m_axi_rvalid ( dm_master.r_valid ), + .m_axi_rready ( dm_master.r_ready ), + //write response channel + .m_axi_bresp ( dm_master.b_resp ), + .m_axi_bvalid ( dm_master.b_valid ), + .m_axi_bready ( dm_master.b_ready ), + // non-axi-lite signals + .w_reqbuf_size ( ), + .r_reqbuf_size ( ) + ); + + // tie off system bus accesses (not supported yet due to + // missing AXI-lite br_master <-> NOC converter) + assign dm_master_gnt = '0; + assign dm_master_r_valid = '0; + assign dm_master_r_rdata = '0; + + // tie off signals not used by AXI-lite + assign dm_master.aw_id = '0; + assign dm_master.aw_len = '0; + assign dm_master.aw_size = 3'b11;// 8byte + assign dm_master.aw_burst = '0; + assign dm_master.aw_lock = '0; + assign dm_master.aw_cache = '0; + assign dm_master.aw_prot = '0; + assign dm_master.aw_qos = '0; + assign dm_master.aw_region = '0; + assign dm_master.aw_atop = '0; + assign dm_master.w_last = 1'b1; + assign dm_master.ar_id = '0; + assign dm_master.ar_len = '0; + assign dm_master.ar_size = 3'b11;// 8byte + assign dm_master.ar_burst = '0; + assign dm_master.ar_lock = '0; + assign dm_master.ar_cache = '0; + assign dm_master.ar_prot = '0; + assign dm_master.ar_qos = '0; + assign dm_master.ar_region = '0; + +endmodule diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 4f536db67..4666210b2 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -24,6 +24,23 @@ -model=manycore -toplevel=cmp_top + //-config_rtl=SYNTHESIZABLE_BRAM + -config_rtl=USE_GENERIC_SRAM_IMPLEMENTATION + //-config_rtl=PITON_ASIC_RTL + -config_rtl=__ICARUS__ + -config_rtl=USE_FLL + // -config_rtl=SYNC_MUX + //-config_rtl=CIOP_REAL_IOB + //-config_rtl=MINIMAL_MONITORING + + -config_rtl=L2_SEND_NC_REQ + + // Multi-core + //-vcs_build_args=-full64 + //-vcs_build_args=-fgp + //-vcs_build_args=-j32 + //-sim_run_args=-fgp=num_threads:2 + -flist=$DV_ROOT/design/include/Flist.include -flist=$DV_ROOT/design/common/rtl/Flist.common -flist=$DV_ROOT/design/chipset/include/Flist.include @@ -60,9 +77,17 @@ #endif #ifdef FLIST_ARIANE -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ara +<<<<<<< HEAD -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi" +======= + -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic + -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform + -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane + -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic + -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" +>>>>>>> c4b8f67 (Integrating PLIC CLINT and Debug unit) -vcs_build_args=-timescale=1ps/1ps -rv64 -rv64_platform diff --git a/piton/verif/diag/c/riscv/ariane/clint_plic_access.c b/piton/verif/diag/c/riscv/ariane/clint_plic_access.c index 00d55c9cb..2fbfed384 100644 --- a/piton/verif/diag/c/riscv/ariane/clint_plic_access.c +++ b/piton/verif/diag/c/riscv/ariane/clint_plic_access.c @@ -14,19 +14,19 @@ // #include +#include +#include "util.h" - -#define NHARTS 1 -#define PLIC_SOURCES 2 -#define CLINT_BASE 0xfff1020000ULL -#define PLIC_BASE 0xfff1030000ULL +#define NHARTS 4 +#define PLIC_SOURCES 16 +#define CLINT_BASE 0xe110500000ULL +#define PLIC_BASE 0xe200000000ULL int main(int argc, char ** argv) { - printf("Reading CLINT registers...\n"); - // only use core 0 to perform test if(argv[0][0] == 0) { + printf("Reading CLINT registers...\n"); uint64_t *addr; // misp registers @@ -39,7 +39,7 @@ int main(int argc, char ** argv) { for (uint64_t k = 0; k < NHARTS; k++) { addr = (uint64_t*)(CLINT_BASE + 0x4000 + k*8); printf("CLINT: mtimecmp %d = addr 0x%08x 0x%08x\n",k,((uint64_t)addr)>>32,((uint64_t)addr) & 0xFFFFFFFF); - printf("CLINT: result = 0x%016x\n",*addr); + printf("CLINT: result = 0x%016x\n",*addr); } // mtime registers for (uint64_t k = 0; k < NHARTS; k++) { @@ -48,29 +48,28 @@ int main(int argc, char ** argv) { printf("CLINT: result = 0x%016x\n",*addr); } - // printf("Reading PLIC registers...\n"); - // - // volatile uint32_t val2; - // // priorities - // for (uint64_t k = 0; k < 128; k++) { - // val2 = *(uint32_t*)((PLIC_BASE + 0x4)>>2 + k); - // printf("PLIC: source prio %d = 0x%08x\n",k,val2); - // } - // // pending - // for (uint64_t k = 0; k < 5; k++) { - // val2 = *(uint32_t*)((PLIC_BASE + 0x1000)>>2 + k); - // printf("PLIC: pending %d = 0x%08x\n",k,val2); - // } - // // pending - // for (uint64_t i = 0; i < NHARTS; i++) { - // for (uint64_t k = 0; k < 5; k++) { - // val2 = *(uint32_t*)((PLIC_BASE + 0x2000)>>2 + k); - // printf("PLIC: hart %d m-mode enable %d = 0x%08x\n",k,val2); - // } - // } + printf("Reading PLIC registers...\n"); + volatile uint32_t val2; + // priorities + for (uint64_t k = 0; k < PLIC_SOURCES; k++) { + val2 = *(uint32_t*)(PLIC_BASE + 0x4 + k * 4); + printf("PLIC: source prio %d = 0x%08x\n",k,val2); + } + // pending + for (uint64_t k = 0; k < 5; k++) { + val2 = *(uint32_t*)(PLIC_BASE + 0x1000 + k * 4); + printf("PLIC: pending %d = 0x%08x\n",k,val2); + } + // enabling + for (uint64_t i = 0; i < NHARTS; i++) { + for (uint64_t k = 0; k < 1; k++) { + val2 = *(uint32_t*)(PLIC_BASE + 0x2000 + i * 0x100 + k * 4); + printf("PLIC: hart %d m-mode enable %d = 0x%08x\n", i, k, val2); + } + } printf("Done!\n"); } - + return 0; } From bfc0755a70566afce967249ded669d4a726a7c90 Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Tue, 28 Nov 2023 21:51:36 -0500 Subject: [PATCH 016/144] Fixed PLIC bug --- .../chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv | 2 +- .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv | 28 +++++++++++++++++-- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv b/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv index eed51240c..ed1839be2 100644 --- a/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv +++ b/piton/design/chip/tile/l2/rtl/l2_pipe1_dpath.v.pyv @@ -2040,7 +2040,7 @@ begin msg_send_dst_chipid_S4 = my_nodeid_chipid_S4; msg_send_dst_x_S4 = my_nodeid_x_S4; msg_send_dst_y_S4 = my_nodeid_y_S4; - msg_send_dst_fbits_S4 = `NOC_FBITS_L1; + msg_send_dst_fbits_S4 = msg_data_S4_f[37:34]; // Fetch fbits from data packet end default: begin diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv index e5c89b8df..0aace9a3c 100644 --- a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv +++ b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv @@ -236,8 +236,8 @@ simplenocbuffer simplenocbuffer( .msg_val(noc2_data_val) ); -wire l15_noc2decoder_ack; -wire l15_noc2decoder_header_ack; +reg l15_noc2decoder_ack; +reg l15_noc2decoder_header_ack; wire noc2decoder_l15_val; wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; wire noc2decoder_l15_l2miss; @@ -291,6 +291,30 @@ noc2decoder noc2decoder( .l15_dmbr_l2responseIn() ); +// Mimic l15 behaviour for the l15 ACK signals +reg l15_noc2decoder_ack_next; +reg l15_noc2decoder_header_ack_next; + +always @(posedge clk) begin + if (~rst_n) begin + l15_noc2decoder_ack <= 1'b0; + l15_noc2decoder_header_ack <= 1'b0; + end else begin + l15_noc2decoder_ack <= l15_noc2decoder_ack_next; + l15_noc2decoder_header_ack <= l15_noc2decoder_header_ack_next; + end +end + +always @* begin + if (noc2_data_val) begin + l15_noc2decoder_ack_next = 1'b1; + l15_noc2decoder_header_ack_next = 1'b1; + end else begin + l15_noc2decoder_ack_next = 1'b0; + l15_noc2decoder_header_ack_next = 1'b0; + end +end + reg new_edge_irq; reg new_edge_irq_next; From 234ccb54c46a25e2a988b71da49f306a3a3c4a70 Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Mon, 27 Nov 2023 16:41:51 -0500 Subject: [PATCH 017/144] Fix merge conflicts PLIC CLINT --- piton/design/chip/rtl/chip.v.pyv | 49 +- .../chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic | 2 +- .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv | 28 +- .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.v | 572 ------------------ piton/tools/src/sims/manycore.config | 5 - 5 files changed, 39 insertions(+), 617 deletions(-) delete mode 100644 piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.v diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index eacbdcc72..5e2f685ae 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -336,7 +336,7 @@ module chip( `ifdef PITON_RV64_CLINT // CLINT - wire [`PITON_NUM_TILES-1:0] timer_irq; // Timer interrupts + wire [`PITON_NUM_TILES-1:0] timer_irq; // Timer interrupts wire [`PITON_NUM_TILES-1:0] ipi; // software interrupt (a.k.a inter-process-interrupt) `endif // ifdef PITON_RV64_CLINT @@ -440,7 +440,7 @@ module chip( // make some PLIC, CLINT, debug unit signals wire [`DATA_WIDTH-1:0] rvic_out_S_noc1_data = `DATA_WIDTH'b0; wire rvic_out_S_noc1_valid = 1'b0; - wire rvic_out_S_noc1_yummy = 1'b0; + wire rvic_out_S_noc1_yummy; wire [`DATA_WIDTH-1:0] rvic_out_S_noc2_data; wire rvic_out_S_noc2_valid; wire rvic_out_S_noc2_yummy; @@ -449,20 +449,20 @@ module chip( wire rvic_out_S_noc3_yummy = 1'b0; wire [`DATA_WIDTH-1:0] clint_out_S_noc1_data = `DATA_WIDTH'b0; wire clint_out_S_noc1_valid = 1'b0; - wire clint_out_S_noc1_yummy = 1'b0; + wire clint_out_S_noc1_yummy; wire [`DATA_WIDTH-1:0] clint_out_S_noc2_data; wire clint_out_S_noc2_valid; wire clint_out_S_noc2_yummy; wire [`DATA_WIDTH-1:0] clint_out_S_noc3_data = `DATA_WIDTH'b0; wire clint_out_S_noc3_valid = 1'b0; wire clint_out_S_noc3_yummy = 1'b0; - wire [`DATA_WIDTH-1:0] debug_out_S_noc1_data = `DATA_WIDTH'b0; + wire [`DATA_WIDTH-1:0] debug_out_W_noc1_data = `DATA_WIDTH'b0; wire debug_out_S_noc1_valid = 1'b0; wire debug_out_S_noc1_yummy = 1'b0; - wire [`DATA_WIDTH-1:0] debug_out_S_noc2_data; + wire [`DATA_WIDTH-1:0] debug_out_W_noc2_data; wire debug_out_S_noc2_valid; wire debug_out_S_noc2_yummy; - wire [`DATA_WIDTH-1:0] debug_out_S_noc3_data = `DATA_WIDTH'b0; + wire [`DATA_WIDTH-1:0] debug_out_W_noc3_data = `DATA_WIDTH'b0; wire debug_out_S_noc3_valid = 1'b0; wire debug_out_S_noc3_yummy = 1'b0; @@ -1203,8 +1203,8 @@ module chip( # special case for core 1 if i == 1 and j == 0: - idE = "debug" idN = "clint" + # idE = "debug" currenttile = currenttile.replace("in_N", idN + "_out_S"); currenttile = currenttile.replace("in_S", idS + "_out_N"); @@ -1216,6 +1216,18 @@ module chip( # print "`endif" %> +// RTC generator +reg [13:0] rtc_divider = 14'b00000000000000; + +always @(posedge clk_muxed) begin + rtc_divider <= rtc_divider + 1; + if (rtc_divider == 16384) begin + rtc_divider <= 0; + end +end +assign rtc = rtc_divider[13]; + + pmesh_rvic pmesh_rvic ( .clk ( clk_muxed ), .rst_n ( rst_n_inter_sync ), @@ -1223,17 +1235,17 @@ pmesh_rvic pmesh_rvic ( // Interrupt status is received from noc2 .src_rvic_cr_noc2_val ( tile_0_0_out_N_noc2_valid ), .src_rvic_cr_noc2_dat ( tile_0_0_out_N_noc2_data ), - .src_rvic_cr_noc2_yum ( tile_0_0_out_N_noc2_yummy ), + .src_rvic_cr_noc2_yum ( rvic_out_S_noc2_yummy ), // input from noc1 (load/store to RVIC) .src_rvic_cr_noc1_val ( tile_0_0_out_N_noc1_valid ), .src_rvic_cr_noc1_dat ( tile_0_0_out_N_noc1_data ), - .src_rvic_cr_noc1_yum ( tile_0_0_out_N_noc1_yummy ), + .src_rvic_cr_noc1_yum ( rvic_out_S_noc1_yummy ), // output to noc2 (load/store response) .rvic_dst_cr_noc2_val ( rvic_out_S_noc2_valid ), .rvic_dst_cr_noc2_dat ( rvic_out_S_noc2_data ), - .rvic_dst_cr_noc2_yum ( rvic_out_S_noc2_yummy ), + .rvic_dst_cr_noc2_yum ( tile_0_0_out_N_noc2_yummy ), // Interrupt targets go to core .irq_targets ( irq ), @@ -1241,11 +1253,11 @@ pmesh_rvic pmesh_rvic ( // CLINT .src_clint_cr_noc1_val ( tile_0_1_out_N_noc1_valid ), .src_clint_cr_noc1_dat ( tile_0_1_out_N_noc1_data ), - .src_clint_cr_noc1_yum ( tile_0_1_out_N_noc1_yummy ), + .src_clint_cr_noc1_yum ( clint_out_S_noc1_yummy ), .clint_dst_cr_noc2_val ( clint_out_S_noc2_valid ), .clint_dst_cr_noc2_dat ( clint_out_S_noc2_data ), - .clint_dst_cr_noc2_yum ( clint_out_S_noc2_yummy ), + .clint_dst_cr_noc2_yum ( tile_0_1_out_N_noc2_yummy ), .rtc_i ( rtc ), // Real-time clock in (usually 32.768 kHz) .timer_irq_o ( timer_irq ), // Timer interrupts @@ -1258,7 +1270,18 @@ pmesh_rvic pmesh_rvic ( .debug_dst_cr_noc2_val ( debug_out_W_noc2_valid ), .debug_dst_cr_noc2_dat ( debug_out_W_noc2_data ), - .debug_dst_cr_noc2_yum ( debug_out_W_noc2_yummy ) + .debug_dst_cr_noc2_yum ( debug_out_W_noc2_yummy ), + + .ndmreset_o ( ), // not used + .dmactive_o ( ), // not used + .debug_req_o ( debug_req ), + .unavailable_i ( unavailable ), + .tck_i ( jtag_clk_inter ), + .tms_i ( jtag_rst_l_inter ), + .trst_ni ( jtag_modesel_inter ), + .td_i ( jtag_datain_inter ), + .td_o ( jtag_dataout_inter ), + .tdo_oe_o ( ) // not used ); endmodule diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic b/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic index 279151230..dd6bc1924 100644 --- a/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic +++ b/piton/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic @@ -1,2 +1,2 @@ -pmesh_rvic.v +pmesh_rvic.sv rvic_wrap.sv diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv index 0aace9a3c..e5c89b8df 100644 --- a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv +++ b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv @@ -236,8 +236,8 @@ simplenocbuffer simplenocbuffer( .msg_val(noc2_data_val) ); -reg l15_noc2decoder_ack; -reg l15_noc2decoder_header_ack; +wire l15_noc2decoder_ack; +wire l15_noc2decoder_header_ack; wire noc2decoder_l15_val; wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; wire noc2decoder_l15_l2miss; @@ -291,30 +291,6 @@ noc2decoder noc2decoder( .l15_dmbr_l2responseIn() ); -// Mimic l15 behaviour for the l15 ACK signals -reg l15_noc2decoder_ack_next; -reg l15_noc2decoder_header_ack_next; - -always @(posedge clk) begin - if (~rst_n) begin - l15_noc2decoder_ack <= 1'b0; - l15_noc2decoder_header_ack <= 1'b0; - end else begin - l15_noc2decoder_ack <= l15_noc2decoder_ack_next; - l15_noc2decoder_header_ack <= l15_noc2decoder_header_ack_next; - end -end - -always @* begin - if (noc2_data_val) begin - l15_noc2decoder_ack_next = 1'b1; - l15_noc2decoder_header_ack_next = 1'b1; - end else begin - l15_noc2decoder_ack_next = 1'b0; - l15_noc2decoder_header_ack_next = 1'b0; - end -end - reg new_edge_irq; reg new_edge_irq_next; diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.v b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.v deleted file mode 100644 index c7e9198d1..000000000 --- a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.v +++ /dev/null @@ -1,572 +0,0 @@ -// Copyright (c) 2020 Princeton University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// * Neither the name of Princeton University nor the -// names of its contributors may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY -// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -`include "l15.tmp.h" -`include "define.tmp.h" - -module pmesh_rvic #( - parameter integer NUM_SOURCES = 16, - parameter integer NUM_HARTS = 4, - parameter integer MAX_PRIORITY = 7, - parameter CLINT_BASE = 64'he110500000, // north of the northeast tile - parameter PLIC_BASE = 64'he200000000, // north of the northwest tile - parameter DEBUG_BASE = 64'he110400000, // east of the northeast tile - parameter SWAP_ENDIANESS = 1 -) ( - input clk, - input rst_n, - - // PLIC - - // Interrupt status is received from noc2 - input src_rvic_cr_noc2_val, - input [`NOC_DATA_WIDTH-1:0] src_rvic_cr_noc2_dat, - output src_rvic_cr_noc2_yum, - - // input from noc1 (load/store to PLIC) - input src_rvic_cr_noc1_val, - input [`NOC_DATA_WIDTH-1:0] src_rvic_cr_noc1_dat, - output src_rvic_cr_noc1_yum, - - // output to noc2 (load/store PLIC response) - output rvic_dst_cr_noc2_val, - output [`NOC_DATA_WIDTH-1:0] rvic_dst_cr_noc2_dat, - input rvic_dst_cr_noc2_yum, - - // Interrupt targets go to core - output [NUM_HARTS*2-1:0] irq_targets, - - // CLINT - // input from noc1 (load/store to CLINT) - input src_clint_cr_noc1_val, - input [`NOC_DATA_WIDTH-1:0] src_clint_cr_noc1_dat, - output src_clint_cr_noc1_yum, - - // output to noc2 (load/store CLINT response) - output clint_dst_cr_noc2_val, - output [`NOC_DATA_WIDTH-1:0] clint_dst_cr_noc2_dat, - input clint_dst_cr_noc2_yum, - - input rtc_i, // Real-time clock in (usually 32.768 kHz) - output [NUM_HARTS-1:0] timer_irq_o, // Timer interrupts - output [NUM_HARTS-1:0] ipi_o, // software interrupt (a.k.a inter-process-interrupt) - - // Debug unit - // input from noc1 (load/store to debug unit) - input src_debug_cr_noc1_val, - input [`NOC_DATA_WIDTH-1:0] src_debug_cr_noc1_dat, - output src_debug_cr_noc1_yum, - - // output to noc2 (load/store debug unit response) - output debug_dst_cr_noc2_val, - output [`NOC_DATA_WIDTH-1:0] debug_dst_cr_noc2_dat, - input debug_dst_cr_noc2_yum, - - // Debug sigs to cores - output ndmreset_o, // non-debug module reset - output dmactive_o, // debug module is active - output [NUM_HARTS-1:0] debug_req_o, // async debug request - input [NUM_HARTS-1:0] unavailable_i, // communicate whether the hart is unavailable (e.g.: power down) - - // JTAG - input tck_i, - input tms_i, - input trst_ni, - input td_i, - output td_o, - output tdo_oe_o -); - -// Interrupt status is received from noc2 -wire src_rvic_vr_noc2_val; -wire [`NOC_DATA_WIDTH-1:0] src_rvic_vr_noc2_dat; -wire src_rvic_vr_noc2_rdy; - -// input from noc1 (load/store to PLIC) -wire src_rvic_vr_noc1_val; -wire [`NOC_DATA_WIDTH-1:0] src_rvic_vr_noc1_dat; -wire src_rvic_vr_noc1_rdy; - -// output to noc2 (load/store PLIC response) -wire rvic_dst_vr_noc2_val; -wire [`NOC_DATA_WIDTH-1:0] rvic_dst_vr_noc2_dat; -wire rvic_dst_vr_noc2_rdy; - -// CLINT -// input from noc1 (load/store to CLINT) -wire src_clint_vr_noc1_val; -wire [`NOC_DATA_WIDTH-1:0] src_clint_vr_noc1_dat; -wire src_clint_vr_noc1_rdy; - -// output to noc2 (load/store CLINT response) -wire clint_dst_vr_noc2_val; -wire [`NOC_DATA_WIDTH-1:0] clint_dst_vr_noc2_dat; -wire clint_dst_vr_noc2_rdy; - -// Debug unit -// input from noc1 (load/store to debug unit) -wire src_debug_vr_noc1_val; -wire [`NOC_DATA_WIDTH-1:0] src_debug_vr_noc1_dat; -wire src_debug_vr_noc1_rdy; - -// output to noc2 (load/store debug unit response) -wire debug_dst_vr_noc2_val; -wire [`NOC_DATA_WIDTH-1:0] debug_dst_vr_noc2_dat; -wire debug_dst_vr_noc2_rdy; - -credit_to_valrdy src_rvic_noc2_c2v( - .clk (clk), - .reset (~rst_n), - .data_in (src_rvic_cr_noc2_dat), - .valid_in (src_rvic_cr_noc2_val), - .yummy_in (src_rvic_cr_noc2_yum), - - .data_out (src_rvic_vr_noc2_dat), - .valid_out (src_rvic_vr_noc2_val), - .ready_out (src_rvic_vr_noc2_rdy) -); - -credit_to_valrdy src_rvic_noc1_c2v( - .clk (clk), - .reset (~rst_n), - .data_in (src_rvic_cr_noc1_dat), - .valid_in (src_rvic_cr_noc1_val), - .yummy_in (src_rvic_cr_noc1_yum), - - .data_out (src_rvic_vr_noc1_dat), - .valid_out (src_rvic_vr_noc1_val), - .ready_out (src_rvic_vr_noc1_rdy) -); - -valrdy_to_credit #(4, 3) rvic_dst_noc2_v2c( - .clk (clk), - .reset (~rst_n), - .data_in (rvic_dst_vr_noc2_dat), - .valid_in (rvic_dst_vr_noc2_val), - .ready_in (rvic_dst_vr_noc2_rdy), - - .data_out (rvic_dst_cr_noc2_dat), - .valid_out (rvic_dst_cr_noc2_val), - .yummy_out (rvic_dst_cr_noc2_yum) -); - -credit_to_valrdy src_clint_noc1_c2v( - .clk (clk), - .reset (~rst_n), - .data_in (src_clint_cr_noc1_dat), - .valid_in (src_clint_cr_noc1_val), - .yummy_in (src_clint_cr_noc1_yum), - - .data_out (src_clint_vr_noc1_dat), - .valid_out (src_clint_vr_noc1_val), - .ready_out (src_clint_vr_noc1_rdy) -); - -valrdy_to_credit #(4, 3) clint_dst_noc2_v2c( - .clk (clk), - .reset (~rst_n), - .data_in (clint_dst_vr_noc2_dat), - .valid_in (clint_dst_vr_noc2_val), - .ready_in (clint_dst_vr_noc2_rdy), - - .data_out (clint_dst_cr_noc2_dat), - .valid_out (clint_dst_cr_noc2_val), - .yummy_out (clint_dst_cr_noc2_yum) -); - -credit_to_valrdy src_debug_noc1_c2v( - .clk (clk), - .reset (~rst_n), - .data_in (src_debug_cr_noc1_dat), - .valid_in (src_debug_cr_noc1_val), - .yummy_in (src_debug_cr_noc1_yum), - - .data_out (src_debug_vr_noc1_dat), - .valid_out (src_debug_vr_noc1_val), - .ready_out (src_debug_vr_noc1_rdy) -); - -valrdy_to_credit #(4, 3) debug_dst_noc2_v2c( - .clk (clk), - .reset (~rst_n), - .data_in (debug_dst_vr_noc2_dat), - .valid_in (debug_dst_vr_noc2_val), - .ready_in (debug_dst_vr_noc2_rdy), - - .data_out (debug_dst_cr_noc2_dat), - .valid_out (debug_dst_cr_noc2_val), - .yummy_out (debug_dst_cr_noc2_yum) -); - - -wire [511:0] noc2_data; -wire noc2_data_val; -wire noc2_data_ack; - -simplenocbuffer simplenocbuffer( - .clk(clk), - .rst_n(rst_n), - .noc_in_val(src_rvic_vr_noc2_val), - .noc_in_data(src_rvic_vr_noc2_dat), - .msg_ack(noc2_data_ack), - .noc_in_rdy(src_rvic_vr_noc2_rdy), - .msg(noc2_data), - .msg_val(noc2_data_val) -); - -wire l15_noc2decoder_ack; -wire l15_noc2decoder_header_ack; -wire noc2decoder_l15_val; -wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; -wire noc2decoder_l15_l2miss; -wire noc2decoder_l15_icache_type; -wire noc2decoder_l15_f4b; -wire [`MSG_TYPE_WIDTH-1:0] noc2decoder_l15_reqtype; -wire [`L15_MESI_STATE_WIDTH-1:0] noc2decoder_l15_ack_state; -wire [63:0] noc2decoder_l15_data_0; -wire [63:0] noc2decoder_l15_data_1; -wire [63:0] noc2decoder_l15_data_2; -wire [63:0] noc2decoder_l15_data_3; -wire [`L15_PADDR_HI:0] noc2decoder_l15_address; -wire [3:0] noc2decoder_l15_fwd_subcacheline_vector; -wire [`PACKET_HOME_ID_WIDTH-1:0] noc2decoder_l15_src_homeid; - -wire [`L15_CSM_NUM_TICKETS_LOG2-1:0] noc2decoder_l15_csm_mshrid; -wire [`L15_THREADID_MASK] noc2decoder_l15_threadid; -wire noc2decoder_l15_hmc_fill; - -/* - noc2decoder takes the data from the buffer and decode it to meaningful signals - to the l15 -*/ -noc2decoder noc2decoder( - .clk(clk), - .rst_n(rst_n), - .noc2_data(noc2_data), - .noc2_data_val(noc2_data_val), - .l15_noc2decoder_ack(l15_noc2decoder_ack), - .l15_noc2decoder_header_ack(l15_noc2decoder_header_ack), - .noc2_data_ack(noc2_data_ack), - .noc2decoder_l15_val(noc2decoder_l15_val), - .noc2decoder_l15_mshrid(noc2decoder_l15_mshrid), - .noc2decoder_l15_l2miss(noc2decoder_l15_l2miss), - .noc2decoder_l15_icache_type(noc2decoder_l15_icache_type), - .noc2decoder_l15_f4b(noc2decoder_l15_f4b), - .noc2decoder_l15_reqtype(noc2decoder_l15_reqtype), - .noc2decoder_l15_ack_state(noc2decoder_l15_ack_state), - .noc2decoder_l15_data_0(noc2decoder_l15_data_0), - .noc2decoder_l15_data_1(noc2decoder_l15_data_1), - .noc2decoder_l15_data_2(noc2decoder_l15_data_2), - .noc2decoder_l15_data_3(noc2decoder_l15_data_3), - .noc2decoder_l15_address(noc2decoder_l15_address), - .noc2decoder_l15_fwd_subcacheline_vector(noc2decoder_l15_fwd_subcacheline_vector), - .noc2decoder_l15_src_homeid(noc2decoder_l15_src_homeid), - .noc2decoder_l15_csm_mshrid(noc2decoder_l15_csm_mshrid), - .noc2decoder_l15_threadid(noc2decoder_l15_threadid), - .noc2decoder_l15_hmc_fill(noc2decoder_l15_hmc_fill), - .l15_dmbr_l2missIn(l15_dmbr_l2missIn), - .l15_dmbr_l2missTag(l15_dmbr_l2missTag), - .l15_dmbr_l2responseIn(l15_dmbr_l2responseIn) -); - -reg new_edge_irq; -reg new_edge_irq_next; - -reg [NUM_SOURCES:0] lev_or_edge; -reg [NUM_SOURCES:0] lev_or_edge_next; -reg [NUM_SOURCES:0] irq_sources; -reg [NUM_SOURCES:0] irq_sources_next; - -reg [6:0] most_recent_source; -reg [6:0] most_recent_source_next; - -reg [9:0] source_id_field; - -// flit2: -// 63 1 -// 59:56 source id bit [9:6], for decades, only use bit[6:0] -// 33:26 ypos -// 25:18 xpos -// 17:16 type -// 15:9 0 -// 8 threadid -// 7 0:level, 1:edge -// 6 0:rising, 1:falling -// 5:0 source id bit [5:0] -// Read from the l15 message -// for edge-sensitive or rising edge of level-sensitive, -// the next cycle of that interrupt should be high. -// The edge sensitive interrupt will automatically return to 0 after 1 cycle -always @* begin - new_edge_irq_next = 1'b0; - most_recent_source_next = most_recent_source; - irq_sources_next = irq_sources; - lev_or_edge_next = lev_or_edge; - source_id_field = 10'b0; - if (noc2decoder_l15_val && (noc2decoder_l15_reqtype == `MSG_TYPE_INTERRUPT) && ~new_edge_irq && (noc2decoder_l15_data_0[17:16] == 2'b0)) begin - // Comebine the source id together - source_id_field = {noc2decoder_l15_data_0[59:56], noc2decoder_l15_data_0[5:0]}; - // Either level sensitive edge or rising edge of edge sensitive pulse - new_edge_irq_next = noc2decoder_l15_data_0[7]; - most_recent_source_next = source_id_field[6:0]; - irq_sources_next[source_id_field[6:0]] = noc2decoder_l15_data_0[7] | (~noc2decoder_l15_data_0[7] & ~noc2decoder_l15_data_0[6]); // edge-sensitive or rising edge of level-sensitive - lev_or_edge_next[source_id_field[6:0]] = noc2decoder_l15_data_0[7]; - end else if (new_edge_irq) begin - // Edge sensitive automatic falling edge of pulse - most_recent_source_next = 7'b0; - irq_sources_next[most_recent_source] = 1'b0; - end -end - -always @(posedge clk) begin - if (~rst_n) begin - new_edge_irq <= 1'b0; - most_recent_source <= 7'b0; - end else begin - new_edge_irq <= new_edge_irq_next; - most_recent_source <= most_recent_source_next; - end -end - -always @(posedge clk) begin - if (~rst_n) begin - irq_sources <= {NUM_SOURCES+1{1'b0}}; - lev_or_edge <= {NUM_SOURCES+1{1'b0}}; - end else begin - irq_sources <= irq_sources_next; - lev_or_edge <= lev_or_edge_next; - end -end - -wire [63:0] aw_addr; -wire aw_valid; -wire aw_ready; -wire [63:0] w_data; -wire [7:0] w_strb; -wire w_valid; -wire w_ready; -wire [63:0] ar_addr; -wire ar_valid; -wire ar_ready; -wire [63:0] r_data; -wire [1:0] r_resp; -wire r_valid; -wire r_ready; -wire [1:0] b_resp; -wire b_valid; -wire b_ready; -wire [2:0] aw_size; -wire [2:0] ar_size; - -wire [63:0] clint_aw_addr; -wire clint_aw_valid; -wire clint_aw_ready; -wire [63:0] clint_w_data; -wire [7:0] clint_w_strb; -wire clint_w_valid; -wire clint_w_ready; -wire [63:0] clint_ar_addr; -wire clint_ar_valid; -wire clint_ar_ready; -wire [63:0] clint_r_data; -wire [1:0] clint_r_resp; -wire clint_r_valid; -wire clint_r_ready; -wire [1:0] clint_b_resp; -wire clint_b_valid; -wire clint_b_ready; - -// Fake int for testing -// parameter OK_INT_CNT = 40000; -// reg [63:0] int_cnt; -// wire int_sent; -// reg fake_int; -// assign int_sent = int_cnt == OK_INT_CNT; -// -// always @(posedge clk) begin -// if (~rst_n) begin -// int_cnt <= 32'b0; -// fake_int <= 1'b0; -// end -// else begin -// int_cnt <= int_sent ? int_cnt : int_cnt + 1'b1 ; -// //fake_int <= ( (int_cnt == OK_INT_CNT-2) || (int_cnt == OK_INT_CNT-1) ) ? ~fake_int : fake_int; -// fake_int <= (int_cnt == OK_INT_CNT-1) ? ~fake_int : fake_int; -// end -// end - - - -noc_axilite_bridge #( - // this enables variable width accesses - // note that the accesses are still 64bit, but the - // write-enables are generated according to the access size - .SLAVE_RESP_BYTEWIDTH ( 0 ), - .SWAP_ENDIANESS ( SWAP_ENDIANESS ), - // this disables shifting of unaligned read data - .ALIGN_RDATA ( 0 ) -) rvic_axilite_bridge ( - .clk ( clk ), - .rst ( ~rst_n ), - // to/from NOC - .splitter_bridge_val ( src_rvic_vr_noc1_val ), - .splitter_bridge_data ( src_rvic_vr_noc1_dat ), - .bridge_splitter_rdy ( src_rvic_vr_noc1_rdy ), - .bridge_splitter_val ( rvic_dst_vr_noc2_val ), - .bridge_splitter_data ( rvic_dst_vr_noc2_dat ), - .splitter_bridge_rdy ( rvic_dst_vr_noc2_rdy ), - //axi lite signals - //write address channel - .m_axi_awaddr ( aw_addr ), - .m_axi_awvalid ( aw_valid ), - .m_axi_awready ( aw_ready ), - //write data channel - .m_axi_wdata ( w_data ), - .m_axi_wstrb ( w_strb ), - .m_axi_wvalid ( w_valid ), - .m_axi_wready ( w_ready ), - //read address channel - .m_axi_araddr ( ar_addr ), - .m_axi_arvalid ( ar_valid ), - .m_axi_arready ( ar_ready ), - //read data channel - .m_axi_rdata ( r_data ), - .m_axi_rresp ( r_resp ), - .m_axi_rvalid ( r_valid ), - .m_axi_rready ( r_ready ), - //write response channel - .m_axi_bresp ( b_resp ), - .m_axi_bvalid ( b_valid ), - .m_axi_bready ( b_ready ), - // non-axi-lite signals - .w_reqbuf_size ( aw_size ), - .r_reqbuf_size ( ar_size ) -); - -// CLINT -noc_axilite_bridge #( - .SLAVE_RESP_BYTEWIDTH ( 8 ), - .SWAP_ENDIANESS ( SWAP_ENDIANESS ) -) i_clint_axilite_bridge ( - .clk ( clk ), - .rst ( ~rst_n ), - // to/from NOC - .splitter_bridge_val ( src_clint_vr_noc1_val ), - .splitter_bridge_data ( src_clint_vr_noc1_dat ), - .bridge_splitter_rdy ( src_clint_vr_noc1_rdy ), - .bridge_splitter_val ( clint_dst_vr_noc2_val ), - .bridge_splitter_data ( clint_dst_vr_noc2_dat ), - .splitter_bridge_rdy ( clint_dst_vr_noc2_rdy ), - //axi lite signals - //write address channel - .m_axi_awaddr ( clint_aw_addr ), - .m_axi_awvalid ( clint_aw_valid ), - .m_axi_awready ( clint_aw_ready ), - //write data channel - .m_axi_wdata ( clint_w_data ), - .m_axi_wstrb ( clint_w_strb ), - .m_axi_wvalid ( clint_w_valid ), - .m_axi_wready ( clint_w_ready ), - //read address channel - .m_axi_araddr ( clint_ar_addr ), - .m_axi_arvalid ( clint_ar_valid ), - .m_axi_arready ( clint_ar_ready ), - //read data channel - .m_axi_rdata ( clint_r_data ), - .m_axi_rresp ( clint_r_resp ), - .m_axi_rvalid ( clint_r_valid ), - .m_axi_rready ( clint_r_ready ), - //write response channel - .m_axi_bresp ( clint_b_resp ), - .m_axi_bvalid ( clint_b_valid ), - .m_axi_bready ( clint_b_ready ), - // non-axi-lite signals - .w_reqbuf_size ( ), - .r_reqbuf_size ( ) - ); - - -rvic_wrap #( - .NumSources ( NUM_SOURCES ), - .NumHarts ( NUM_HARTS ), - .PlicMaxPriority ( MAX_PRIORITY ), - .ClintBase ( CLINT_BASE ), - .PlicBase ( PLIC_BASE ), - .DmBase ( DEBUG_BASE ) -) rvic_wrap ( - .clk ( clk ), - .rst_n ( rst_n ), - //axi lite signals - .axi_awaddr ( aw_addr ), - .axi_awvalid ( aw_valid ), - .axi_awready ( aw_ready ), - .axi_wdata ( w_data ), - .axi_wstrb ( w_strb ), - .axi_wvalid ( w_valid ), - .axi_wready ( w_ready ), - .axi_araddr ( ar_addr ), - .axi_arvalid ( ar_valid ), - .axi_arready ( ar_ready ), - .axi_rdata ( r_data ), - .axi_rresp ( r_resp ), - .axi_rvalid ( r_valid ), - .axi_rready ( r_ready ), - .axi_bresp ( b_resp ), - .axi_bvalid ( b_valid ), - .axi_bready ( b_ready ), - .w_reqbuf_size ( aw_size ), - .r_reqbuf_size ( ar_size ), - - // clint axi lite signals - .clint_axi_awaddr ( clint_aw_addr ), - .clint_axi_awvalid ( clint_aw_valid ), - .clint_axi_awready ( clint_aw_ready ), - .clint_axi_wdata ( clint_w_data ), - .clint_axi_wstrb ( clint_w_strb ), - .clint_axi_wvalid ( clint_w_valid ), - .clint_axi_wready ( clint_w_ready ), - .clint_axi_araddr ( clint_ar_addr ), - .clint_axi_arvalid ( clint_ar_valid ), - .clint_axi_arready ( clint_ar_ready ), - .clint_axi_rdata ( clint_r_data ), - .clint_axi_rresp ( clint_r_resp ), - .clint_axi_rvalid ( clint_r_valid ), - .clint_axi_rready ( clint_r_ready ), - .clint_axi_bresp ( clint_b_resp ), - .clint_axi_bvalid ( clint_b_valid ), - .clint_axi_bready ( clint_b_ready ), - - .irq_sources_i ( irq_sources[NUM_SOURCES:1] ), // already synchronized - .irq_le_i ( lev_or_edge_next[NUM_SOURCES:1] ), // 0:level 1:edge, bypass from reg - .irq_o ( irq_targets ), - - .testmode_i ( 1'b0 ), // Not Sure: tie this to 1'b0 for using clint - - .rtc_i ( rtc_i ), // Real-time clock in (usually 32.768 kHz) - .timer_irq_o ( timer_irq_o ), // Timer interrupts - .ipi_o ( ipi_o ) // software interrupt (a.k.a inter-process-interrupt) -); - -endmodule diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 91e763a50..977ea2d29 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -77,16 +77,11 @@ #endif #ifdef FLIST_ARIANE -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ara - -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane - -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic - -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -flist=$DV_ROOT/design/chip/tile/pmesh_rvic_rtl/Flist.pmesh_rvic -flist=$DV_ROOT/design/chipset/rv64_platform/Flist.rv64_platform -flist=$DV_ROOT/design/chip/tile/ara/openpiton/Flist.ariane -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" - -flist=$DV_ROOT/design/chipset/rv64_platform/rv_plic_rtl/rtl/Flist.rv_plic - -vcs_build_args="-sverilog +systemverilogext+.sv -ntb_opts uvm-1.1 +vpi -assert svaext" -vcs_build_args=-timescale=1ps/1ps -rv64 -rv64_platform From 0c584d9636c9b4e32b551b366122eb4e5515094a Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Tue, 28 Nov 2023 21:51:36 -0500 Subject: [PATCH 018/144] Fixed PLIC bug --- .../chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv index e5c89b8df..0aace9a3c 100644 --- a/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv +++ b/piton/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv @@ -236,8 +236,8 @@ simplenocbuffer simplenocbuffer( .msg_val(noc2_data_val) ); -wire l15_noc2decoder_ack; -wire l15_noc2decoder_header_ack; +reg l15_noc2decoder_ack; +reg l15_noc2decoder_header_ack; wire noc2decoder_l15_val; wire [`L15_MSHR_ID_WIDTH-1:0] noc2decoder_l15_mshrid; wire noc2decoder_l15_l2miss; @@ -291,6 +291,30 @@ noc2decoder noc2decoder( .l15_dmbr_l2responseIn() ); +// Mimic l15 behaviour for the l15 ACK signals +reg l15_noc2decoder_ack_next; +reg l15_noc2decoder_header_ack_next; + +always @(posedge clk) begin + if (~rst_n) begin + l15_noc2decoder_ack <= 1'b0; + l15_noc2decoder_header_ack <= 1'b0; + end else begin + l15_noc2decoder_ack <= l15_noc2decoder_ack_next; + l15_noc2decoder_header_ack <= l15_noc2decoder_header_ack_next; + end +end + +always @* begin + if (noc2_data_val) begin + l15_noc2decoder_ack_next = 1'b1; + l15_noc2decoder_header_ack_next = 1'b1; + end else begin + l15_noc2decoder_ack_next = 1'b0; + l15_noc2decoder_header_ack_next = 1'b0; + end +end + reg new_edge_irq; reg new_edge_irq_next; From 050688835d17d6c6bee64704962edaa42f55ae83 Mon Sep 17 00:00:00 2001 From: Yoan Fournier Date: Fri, 1 Dec 2023 12:05:10 -0500 Subject: [PATCH 019/144] Adding polara_bootrom --- .../chipset/rv64_platform/bootrom/.gitignore | 3 +- .../rv64_platform/bootrom/polara_bootrom.sv | 169 ++++++++++++++++++ 2 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 piton/design/chipset/rv64_platform/bootrom/polara_bootrom.sv diff --git a/piton/design/chipset/rv64_platform/bootrom/.gitignore b/piton/design/chipset/rv64_platform/bootrom/.gitignore index e3ead7481..1b04629af 100644 --- a/piton/design/chipset/rv64_platform/bootrom/.gitignore +++ b/piton/design/chipset/rv64_platform/bootrom/.gitignore @@ -1,6 +1,7 @@ *.elf *.img *.dtb -*.sv +linux/*.sv +baremetal/*.sv info.h rv64_platform.dts diff --git a/piton/design/chipset/rv64_platform/bootrom/polara_bootrom.sv b/piton/design/chipset/rv64_platform/bootrom/polara_bootrom.sv new file mode 100644 index 000000000..44fe1a01d --- /dev/null +++ b/piton/design/chipset/rv64_platform/bootrom/polara_bootrom.sv @@ -0,0 +1,169 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 14.11.2018 +// Description: Ariane chipset for OpenPiton that includes two bootroms +// (linux, baremetal, both with DTB), debug module, clint and plic. +// +// Note that direct system bus accesses are not yet possible due to a missing +// AXI-lite br_master <-> NOC converter module. +// +// The address bases for the individual peripherals are defined in the +// devices.xml file in OpenPiton, and should be set to +// +// Debug 0xfff1000000 +// Boot Rom 0xfff1010000 +// CLINT 0xfff1020000 +// PLIC 0xfff1100000 +// +`include "register_interface/assign.svh" +`include "register_interface/typedef.svh" + +module polara_bootrom #( + parameter int unsigned DataWidth = 64, + // parameter int unsigned NumHarts = 1, + // parameter int unsigned NumSources = 1, + parameter bit SwapEndianess = 0, + parameter logic [63:0] RomBase = 64'hfff1010000 +) ( + input clk_i, + input rst_ni, + // connections to OpenPiton NoC filters + // Bootrom + input [DataWidth-1:0] buf_ariane_bootrom_noc2_data_i, + input buf_ariane_bootrom_noc2_valid_i, + output ariane_bootrom_buf_noc2_ready_o, + output [DataWidth-1:0] ariane_bootrom_buf_noc3_data_o, + output ariane_bootrom_buf_noc3_valid_o, + input buf_ariane_bootrom_noc3_ready_i, + // This selects either the BM or linux bootrom + input ariane_boot_sel_i +); + + localparam int unsigned AxiIdWidth = 1; + localparam int unsigned AxiAddrWidth = 64; + localparam int unsigned AxiDataWidth = 64; + localparam int unsigned AxiUserWidth = 1; + + ///////////////////////////// + // Bootrom + ///////////////////////////// + + logic rom_req; + logic [AxiAddrWidth-1:0] rom_addr; + logic [AxiDataWidth-1:0] rom_rdata, rom_rdata_bm, rom_rdata_linux; + + AXI_BUS #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) br_master(); + + axi2mem #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) i_axi2rom ( + .clk_i , + .rst_ni , + .slave ( br_master ), + .req_o ( rom_req ), + .we_o ( ), + .addr_o ( rom_addr ), + .be_o ( ), + .data_o ( ), + .data_i ( rom_rdata ) + ); + + bootrom i_bootrom_bm ( + .clk_i , + .req_i ( rom_req ), + .addr_i ( rom_addr ), + .rdata_o ( rom_rdata_bm ) + ); + + bootrom_linux i_bootrom_linux ( + .clk_i , + .req_i ( rom_req ), + .addr_i ( rom_addr ), + .rdata_o ( rom_rdata_linux ) + ); + + // we want to run in baremetal mode when using pitonstream + assign rom_rdata = (ariane_boot_sel_i) ? rom_rdata_bm : rom_rdata_linux; + + noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 0 ), + .SWAP_ENDIANESS ( SwapEndianess ) + ) i_bootrom_axilite_bridge ( + .clk ( clk_i ), + .rst ( ~rst_ni ), + // to/from NOC + .splitter_bridge_val ( buf_ariane_bootrom_noc2_valid_i ), + .splitter_bridge_data ( buf_ariane_bootrom_noc2_data_i ), + .bridge_splitter_rdy ( ariane_bootrom_buf_noc2_ready_o ), + .bridge_splitter_val ( ariane_bootrom_buf_noc3_valid_o ), + .bridge_splitter_data ( ariane_bootrom_buf_noc3_data_o ), + .splitter_bridge_rdy ( buf_ariane_bootrom_noc3_ready_i ), + //axi lite signals + //write address channel + .m_axi_awaddr ( br_master.aw_addr ), + .m_axi_awvalid ( br_master.aw_valid ), + .m_axi_awready ( br_master.aw_ready ), + //write data channel + .m_axi_wdata ( br_master.w_data ), + .m_axi_wstrb ( br_master.w_strb ), + .m_axi_wvalid ( br_master.w_valid ), + .m_axi_wready ( br_master.w_ready ), + //read address channel + .m_axi_araddr ( br_master.ar_addr ), + .m_axi_arvalid ( br_master.ar_valid ), + .m_axi_arready ( br_master.ar_ready ), + //read data channel + .m_axi_rdata ( br_master.r_data ), + .m_axi_rresp ( br_master.r_resp ), + .m_axi_rvalid ( br_master.r_valid ), + .m_axi_rready ( br_master.r_ready ), + //write response channel + .m_axi_bresp ( br_master.b_resp ), + .m_axi_bvalid ( br_master.b_valid ), + .m_axi_bready ( br_master.b_ready ), + // non-axi-lite signals + .w_reqbuf_size ( ), + .r_reqbuf_size ( ) + ); + + // tie off signals not used by AXI-lite + assign br_master.aw_id = '0; + assign br_master.aw_len = '0; + assign br_master.aw_size = 3'b11;// 8byte + assign br_master.aw_burst = '0; + assign br_master.aw_lock = '0; + assign br_master.aw_cache = '0; + assign br_master.aw_prot = '0; + assign br_master.aw_qos = '0; + assign br_master.aw_region = '0; + assign br_master.aw_atop = '0; + assign br_master.w_last = 1'b1; + assign br_master.ar_id = '0; + assign br_master.ar_len = '0; + assign br_master.ar_size = 3'b11;// 8byte + assign br_master.ar_burst = '0; + assign br_master.ar_lock = '0; + assign br_master.ar_cache = '0; + assign br_master.ar_prot = '0; + assign br_master.ar_qos = '0; + assign br_master.ar_region = '0; + +endmodule // riscv_peripherals + From e23f2167db284872c2d907a6ab398dafb3905a96 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Wed, 6 Dec 2023 08:22:37 -0500 Subject: [PATCH 020/144] [FPGA] PLIC/CLINT Integration --- .../design/chipset/io_ctrl/rtl/int_pkt_gen.v | 2 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 43 +++++++++++++++++-- .../xilinx/alveou280/devices_ariane.xml | 21 --------- piton/tools/bin/riscvlib.py | 4 +- piton/tools/src/proto/common/rtl_setup.tcl | 17 +++++++- piton/tools/src/proto/common/setup.tcl | 2 +- 6 files changed, 60 insertions(+), 29 deletions(-) diff --git a/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v b/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v index ae747e8c0..08dad8596 100644 --- a/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v +++ b/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v @@ -178,7 +178,7 @@ always @(*) begin pkt_flit1[63:50] = chip_id; pkt_flit1[49:42] = x_pos; pkt_flit1[41:34] = y_pos; - pkt_flit1[33:30] = 4'b0; // processor + pkt_flit1[33:30] = 4'h5; // processor pkt_flit1[29:22] = 8'b1; if (NOC_ID == 1) begin pkt_flit1[21:14] = `MSG_TYPE_INTERRUPT_FWD; // interrupt forward diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index dca64ae8e..42ee3eb98 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -342,6 +342,14 @@ wire chip_filter_noc3_ready; wire test_good_end; wire test_bad_end; +wire int_pkt_filter_noc2_valid; +wire [`NOC_DATA_WIDTH-1:0] int_pkt_filter_noc2_data; +wire filter_int_pkt_noc2_ready; + +wire uart_merger_filter_noc2_valid; +wire [`NOC_DATA_WIDTH-1:0] uart_merger_filter_noc2_data; +wire filter_uart_merger_noc2_ready; + <% for i in range(len(devices)): if devices[i]["virtual"]: @@ -1040,9 +1048,9 @@ uart_top uart_top ( .xbar_uart_noc3_ready ( buf_uart_noc3_ready ), // output to noc2 - .uart_xbar_noc2_valid ( uart_filter_noc2_valid ), - .uart_xbar_noc2_data ( uart_filter_noc2_data ), - .xbar_uart_noc2_ready ( filter_uart_noc2_ready ), + .uart_xbar_noc2_valid ( uart_merger_filter_noc2_valid ), + .uart_xbar_noc2_data ( uart_merger_filter_noc2_data ), + .xbar_uart_noc2_ready ( filter_uart_merger_noc2_ready ), // input from noc3 .xbar_uart_noc3_valid ( filter_uart_noc3_valid ), @@ -1055,6 +1063,35 @@ uart_top uart_top ( assign test_start = 1'b1; `endif // endif PITONSYS_UART +int_pkt_gen int_pkt_gen ( + .fpga_clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .noc_out_val ( int_pkt_filter_noc2_valid ), + .noc_out_data ( int_pkt_filter_noc2_data ), + .noc_out_rdy ( filter_int_pkt_noc2_ready ), + .interrupt ( uart_interrupt ), + .chip_id ( {(`NOC_CHIPID_WIDTH){1'b0}} ), + .x_pos ( `NOC_X_WIDTH'd0 ), + .y_pos ( `NOC_Y_WIDTH'd0 ), + .irq_le ( 1'b0 ), //0: level, 1: edge + .device_id ( 7'b1 ) // 32 devices +); + +noc_simple_merger uart_int_pkt_noc_simple_merger ( + .clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .src0_merger_vr_noc_val ( int_pkt_filter_noc2_valid ), + .src0_merger_vr_noc_dat ( int_pkt_filter_noc2_data ), + .src0_merger_vr_noc_rdy ( filter_int_pkt_noc2_ready ), + .src1_merger_vr_noc_val ( uart_merger_filter_noc2_valid ), + .src1_merger_vr_noc_dat ( uart_merger_filter_noc2_data ), + .src1_merger_vr_noc_rdy ( filter_uart_merger_noc2_ready ), + .merger_dst_vr_noc_val ( uart_filter_noc2_valid ), + .merger_dst_vr_noc_dat ( uart_filter_noc2_data ), + .merger_dst_vr_noc_rdy ( filter_uart_noc2_ready ) +); + + // SPI interface `ifdef PITONSYS_SPI `ifdef PITON_FPGA_SD_BOOT diff --git a/piton/design/xilinx/alveou280/devices_ariane.xml b/piton/design/xilinx/alveou280/devices_ariane.xml index e3f99d675..67e4a6948 100644 --- a/piton/design/xilinx/alveou280/devices_ariane.xml +++ b/piton/design/xilinx/alveou280/devices_ariane.xml @@ -45,13 +45,6 @@ Description: Peripheral address map for OpenPiton+Ariane configurations. 0x100000 --> - - - ariane_debug - 0xfff1000000 - 0x1000 - - ariane_bootrom @@ -59,19 +52,5 @@ Description: Peripheral address map for OpenPiton+Ariane configurations. 0x10000 - - - ariane_clint - 0xfff1020000 - 0xc0000 - - - - - ariane_plic - 0xfff1100000 - 0x4000000 - - diff --git a/piton/tools/bin/riscvlib.py b/piton/tools/bin/riscvlib.py index cc20337be..47b678a81 100644 --- a/piton/tools/bin/riscvlib.py +++ b/piton/tools/bin/riscvlib.py @@ -321,8 +321,8 @@ def main(): sysFreq = int(os.environ['CONFIG_SYS_FREQ']) timeStamp = time.strftime("%b %d %Y %H:%M:%S", time.localtime()) - gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) - get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) + gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/16384, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) + get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/16384, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) if __name__ == "__main__": main() diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 37b714ee9..9d7578c48 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -397,8 +397,11 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1d_tag.v" \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_data.v" \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_tag.v" \ + "${DV_ROOT}/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv" \ + "${DV_ROOT}/design/chip/tile/pmesh_rvic_rtl/rvic_wrap.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/polara_bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ @@ -516,7 +519,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ @@ -545,6 +547,18 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/reg_intf_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/top_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/tlul_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_reg_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_top.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/prim_subreg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/prim_subreg_ext.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_gateway.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_reg_top.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_target.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ @@ -807,6 +821,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/uart_reseter.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/fake_boot_ctrl.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ + "${DV_ROOT}/design/chipset/io_ctrl/rtl/int_pkt_gen.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.sv" \ diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 3d101e877..4b9b11300 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -99,7 +99,7 @@ if {[info exists ::env(PITON_PICO_HET)]} { } if {[info exists ::env(PITON_ARIANE)]} { - append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT" + append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT L2_SEND_NC_REQ" } for {set k 0} {$k < $::env(PITON_NUM_TILES)} {incr k} { From 1eaa43f2be5e82c301e9fc01468d699a5e12bc5b Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Sun, 10 Dec 2023 22:44:05 -0500 Subject: [PATCH 021/144] [FPGA] Update ariane wrapper --- piton/tools/src/proto/common/rtl_setup.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 37b714ee9..59acd4577 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -441,7 +441,7 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/axi_adapter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/ariane.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ariane.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ From 8547743f0ccc7b6e8dcf9e7cddaf8ce77d80aaf6 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Thu, 14 Dec 2023 09:55:02 -0500 Subject: [PATCH 022/144] [FPGA] Fix plic flist and latch --- .../chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv | 1 + piton/tools/src/proto/common/rtl_setup.tcl | 7 +------ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv b/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv index 88b0b97d5..4c8d3bb40 100644 --- a/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv +++ b/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv @@ -129,6 +129,7 @@ always_comb begin ie_new = '0; ie_we = '0; ie_re_o = '0; + ip_re_o = '0; threshold_new = '0; threshold_we = '0; threshold_re_o = '0; diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 9d7578c48..2b757fd25 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -419,7 +419,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/core/include/instr_tracer_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/include/cvxif_instr_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/acc_dispatcher.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv" \ @@ -444,7 +443,7 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/axi_adapter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/ariane.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ariane.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ @@ -502,10 +501,6 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ From 1881ea499d096527a1fcdf6a154782db660fa906 Mon Sep 17 00:00:00 2001 From: elisabethumblet Date: Thu, 4 Jan 2024 03:42:09 -0500 Subject: [PATCH 023/144] [FPGA] Add register to interrupt signals in chip, better timing --- piton/design/chip/rtl/chip.v.pyv | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 5e2f685ae..dbba0fe3f 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -346,6 +346,9 @@ module chip( `endif // ifdef PITON_RV64_PLIC `endif // ifdef PITON_RV64_PLATFORM + reg [`PITON_NUM_TILES-1:0] timer_irq_reg_i; + reg [`PITON_NUM_TILES*2-1:0] irq_reg_i; + // Tiles JTAG interface wire jtag_tiles_ucb_val; wire [`UCB_BUS_WIDTH-1:0] jtag_tiles_ucb_data; @@ -1084,11 +1087,11 @@ module chip( ,.unavailable_o ( unavailable[_FLAT_ID_] ) `endif // ifdef PITON_RV64_DEBUGUNIT `ifdef PITON_RV64_CLINT - ,.timer_irq_i ( timer_irq[_FLAT_ID_] ) + ,.timer_irq_i ( timer_irq_reg_i[_FLAT_ID_] ) ,.ipi_i ( ipi[_FLAT_ID_] ) `endif // ifdef PITON_RV64_CLINT `ifdef PITON_RV64_PLIC - ,.irq_i ( irq[_FLAT_ID_*2 +: 2] ) + ,.irq_i ( irq_reg_i[_FLAT_ID_*2 +: 2] ) `endif // ifdef PITON_RV64_PLIC `endif // ifdef PITON_RV64_PLATFORM , @@ -1284,6 +1287,11 @@ pmesh_rvic pmesh_rvic ( .tdo_oe_o ( ) // not used ); +always @(posedge clk_muxed) begin + timer_irq_reg_i <= timer_irq; + irq_reg_i <= irq; +end + endmodule `endif From 86ba143eb0e507e5bf9bd06e53e787a7f77ab1c0 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 17 May 2024 15:57:57 -0400 Subject: [PATCH 024/144] Only alveo board had block design defines. --- piton/tools/src/proto/common/setup.tcl | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 4b9b11300..f47dc956d 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -63,8 +63,11 @@ foreach ip_file ${ALL_IP_FILE_PREFIXES} { } set ALL_BD_FILES [list ] -foreach bd_file ${DESIGN_BD_FILES} { - lappend ALL_BD_FILES "${bd_file}.bd" +# Use block design only for alveou280 fpga emulation. +if { ${BOARD} == "alveou280" } { + foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" + } } set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] From a52cbfc351781544d5966782d20c0c20f52c23eb Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 17 May 2024 15:58:38 -0400 Subject: [PATCH 025/144] Added files necessary for chipset generation. --- piton/tools/src/proto/common/rtl_setup.tcl | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 2b757fd25..1b8838ea5 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -774,6 +774,13 @@ set PASSTHRU_PRJ_IP_FILES [list \ ] set CHIPSET_RTL_IMPL_FILES [list \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/axi_intf.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/polara_bootrom.sv" \ + "${DV_ROOT}/design/common/rtl/noc_simple_merger.v" \ "${DV_ROOT}/design/common/rtl/bram_sdp_wrapper.v" \ "${DV_ROOT}/design/chipset/rtl/chipset.v" \ "${DV_ROOT}/design/chipset/rtl/chipset_impl.v" \ From 6256798143d65be8045718addb3f209ae3b6f8f1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 21 May 2024 15:43:56 -0400 Subject: [PATCH 026/144] Modified constraints to pass implementation for command: protosyn --board genesys2 --design chipset --core ariane --jobs 32. --- .../chipset/xilinx/genesys2/constraints.xdc | 757 +++++++++++------- 1 file changed, 456 insertions(+), 301 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 79d4a823a..8df0066be 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -32,11 +32,14 @@ set_property IOSTANDARD LVDS [get_ports clk_osc_n] set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_mmcm] # Non-MMCM clock constraints -create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] +#create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] create_clock -period 5.000 -name passthru_chipset_clk_n -waveform {2.500 5.000} [get_ports passthru_chipset_clk_n] create_clock -period 5.000 -name passthru_chipset_clk -waveform {0.000 2.500} [get_pins passthru_chipset_clk_ibufgds/O] create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] +# Assuming that io_clk has to be created like chipset_passthru_clk_p (RR 2024/05/21) +create_clock -period 5.000 -name io_clk -waveform {0.000 2.500} [get_ports io_clk] +create_clock -period 5.000 -name core_ref_clk -waveform {0.000 2.500} [get_ports core_ref_clk] # Constraint RGMII interface create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] @@ -68,6 +71,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports uart_tx] set_property PACKAGE_PIN Y23 [get_ports uart_tx] # Switches +# sw[7] and sw[6] powered by 3.3V, the rest by VADJ set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] set_property PACKAGE_PIN P27 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] @@ -188,320 +192,471 @@ set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] # FMC Clocks -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_n] -set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_p] -set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_n] -set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_p] +#set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_n] +#set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_p] +#set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_n] +#set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_p] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports core_ref_clk] +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports io_clk] # FMC Signals -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] -set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] -set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] -set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] -set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] -set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] -set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] -set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] +#set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] +#set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[11]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] +#set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] +#set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[0]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] +#set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] +#set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[16]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] +#set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] +#set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[12]] + set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[2]}] -set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[2]}] +#set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] +#set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[2]] set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[0]}] -set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] -set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] -set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] -set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] -set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] -set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] -set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] -set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] -set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] -set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] -set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] -set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] -set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] -set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] -set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] -set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] -set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] -set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] -set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] -set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] -set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] -set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] -set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] -set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] -set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] -set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] -set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] -set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] -set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] -set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] -set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] -set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] -set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] -set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] -set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] -set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] -set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] -set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] -set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] -set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] -set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] -set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] -set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] -set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] -set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] -set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] -set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] -set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] -set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] -set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] -set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] -set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] -set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] -set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] -set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] -set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] -set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] -set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] -set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] -set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] -set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] -set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] -set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] -set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] -set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] -set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] -set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] -set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] -set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] -set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] -set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] -set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] -set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] -set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] -set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] -set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] -set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] -set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] -set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[0]}] +#set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] +#set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS25} [get_ports intf_chip_channel[0]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] +#set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] +#set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[29]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] +#set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] +#set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] +set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[0]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] +#set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] +#set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[30]] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] +#set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] +#set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[31]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] +#set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] +#set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[9]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] +#set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] +#set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[20]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] +#set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] +#set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[25]] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] +#set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] +#set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] +set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[25]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] +#set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] +#set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[15]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] +#set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] +#set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[16]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] +#set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] +#set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[21]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] +#set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] +#set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] +set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[14]] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] +#set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] +#set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[6]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] +#set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] +#set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[11]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] +#set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] +#set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[7]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] +#set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] +#set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[13]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] +#set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] +#set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[8]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] +#set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] +#set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[9]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] +#set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] +#set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[18]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] +#set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] +#set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[22]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] +#set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] +#set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[31]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] +#set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] +#set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[2]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] +#set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] +#set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[0]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] +#set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] +#set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[6]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] +#set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] +#set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[10]] + + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] +#set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] +#set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[1]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] +#set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] +#set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] +set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[15]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] +#set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] +#set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[13]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] +#set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] +#set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[24]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] +#set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] +#set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] +set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[26]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] +#set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] +#set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] +set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[18]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] +#set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] +#set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[17]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] +#set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] +#set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[19]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] +#set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] +#set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] +set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[1]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] +#set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] +#set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] +set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[10]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] +#set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] +#set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[14]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] +#set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] +#set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] +set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[28]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] +#set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] +#set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[30]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] +#set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] +#set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] +set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[22]] + set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] set_property PULLUP true [get_ports piton_prsnt_n] set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] -set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] -set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] -set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] -set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] -set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] -set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] -set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] -set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] -set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] -set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] -set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] -set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] -set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] -set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] -set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] -set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] -set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] -set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] -set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] +#set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] +#set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[29]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] +#set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] +#set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[1]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] +#set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] +#set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports intf_chip_channel[1]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] +#set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] +#set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] +set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[20]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] +#set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] +#set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[28]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] +#set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] +#set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[3]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] +#set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] +#set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[5]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] +#set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] +#set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] +set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[21]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] +#set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] +#set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[23]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] +#set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] +#set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[27]] + set_property PACKAGE_PIN F13 [get_ports piton_ready_n] set_property IOSTANDARD LVCMOS25 [get_ports piton_ready_n] set_property PULLUP true [get_ports piton_ready_n] set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS25} [get_ports chipset_prsnt_n] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[7]}] -set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] -set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] -set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] -set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] -set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] -set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] -set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] -set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] -set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] -set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] -set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] -set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] -set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] -set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] -set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] -set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] -set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] -set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] -set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] -set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] -set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] -set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] -set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] -set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] -set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] -set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] -set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] -set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] -set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] -set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] -set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] -set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] -set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] -set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] -set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] -set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] -set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[7]}] +#set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] +#set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[7]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] +#set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] +#set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[8]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] +#set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] +#set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[4]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] +#set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] +#set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[23]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] +#set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] +#set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[27]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] +#set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] +#set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[17]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] +#set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] +#set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[24]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] +#set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] +#set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[26]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] +#set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] +#set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[19]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] +#set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] +#set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[1]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] +#set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] +#set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[12]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] +#set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] +#set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[2]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] +#set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] +#set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[4]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] +#set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] +#set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS25} [get_ports chip_intf_channel[1]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] +#set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] +#set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[3]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] +#set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] +#set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[0]] + + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] +#set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] +#set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] +set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS25} [get_ports chip_intf_channel[0]] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] +#set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] +#set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] +set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[5]] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] +#set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] +#set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[2]] + set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS25 } [get_ports { F79_N }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] From 2074658326ced5837ee8a00be3acee7dc48167ff Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 21 May 2024 15:52:23 -0400 Subject: [PATCH 027/144] Added prints and support for case of genesys2 chipset generation. --- piton/tools/src/proto/protosyn,2.5 | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 2fd0e35b2..9921854d2 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -333,11 +333,23 @@ def runImplFlow(board, design_data, work_dir, log_dir, def_list, slurm, dep_list #os.chdir(dname) print_info("Running FPGA implementation down to bitstream generation") design_board_dir = os.path.join(design_data["PATH"], board) + # Debugging (RR 2024/05) + print("design_board_dir is: ", design_board_dir) impl_log = os.path.join(log_dir, PROJECT_IMPL_LOG) + print("impl_log is: ", impl_log) impl_flow = os.path.join(DV_ROOT, "tools/src/proto/" + tool + "/impl_flow.tcl") + print("impl_flow is: ", impl_flow) jname = "protosyn_impl_%s_%s" % (board, design_data["ID"]) + print("jname is: ", jname) jid = None if (tool == "vivado"): + print("run_vivado called with: ") + print("impl_log, impl_flow") + print("design_data[PATH] is: ", design_data["PATH"]) + print("board is: ", board) + print("slurm is: ", slurm) + print("jname") + print("dep_list is: ", dep_list) jid = run_vivado(impl_log, impl_flow, design_data["PATH"], board, \ slurm, 8, 64000, "6:00:00", jname, dep_list) elif (tool == "ise"): @@ -577,6 +589,9 @@ def makeDefList(options): if options.design == "chipset": if options.board == "piton_board": defines.append("PITON_BOARD_CHIPSET") + # TEST for genesys2 chipset only synthesis + elif options.board == "genesys2": + defines.append("PITON_BOARD_CHIPSET") else: defines.append("PITON_ASIC_CHIPSET") From 2bdda8071be3a6496373fcc59eee8e2ddbb98517 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 23 May 2024 12:32:32 -0400 Subject: [PATCH 028/144] Debugging OLED wrapper to get it to display --- piton/design/chipset/oled/rtl/oled_wrapper.v | 36 +++++++++++++++++--- piton/design/chipset/rtl/chipset.v | 4 +-- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/piton/design/chipset/oled/rtl/oled_wrapper.v b/piton/design/chipset/oled/rtl/oled_wrapper.v index 879ec3993..fcc15d0b6 100644 --- a/piton/design/chipset/oled/rtl/oled_wrapper.v +++ b/piton/design/chipset/oled/rtl/oled_wrapper.v @@ -24,13 +24,16 @@ // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. module oled_wrapper ( - input sys_clk, + //input sys_clk, input sys_rst_n, input btnl, input btnr, input btnu, input btnd, + + input clk_osc_p, + input clk_osc_n, output spi_sclk, output spi_dc, @@ -73,11 +76,14 @@ wire btnd_pulse; wire last_char; +// If used alone +reg chipset_rst_n_f; +reg chipset_rst_n_ff; assign last_char = char_cnt == (STRING_LEN - 1); always @(posedge sys_clk) begin - if (~sys_rst_n) begin + if (~chipset_rst_n_ff) begin oled_state <= IDLE; char_cnt <= 8'b0; oled_val <= 1'b0; @@ -118,7 +124,7 @@ ssd1306_top #( .SPI_CLK_FREQ_KHZ (OLED_SPI_CLK_KHZ ) ) ssd1306_top ( .sys_clk (sys_clk ), - .sys_rst_n (sys_rst_n ), + .sys_rst_n (chipset_rst_n_ff ), .init_done (init_done ), @@ -151,14 +157,14 @@ assign btnd_pulse = btnd & ~btnd_r; assign btnu_pulse = btnu & ~btnu_r; always @(posedge sys_clk) begin - disp_string <= `OLED_STRING; + disp_string <= "Hello"; end generate begin genvar i; for (i = 0; i < 64; i = i + 1) begin: disp_buf_change always @(posedge sys_clk) begin - if (~sys_rst_n) begin + if (~chipset_rst_n_ff) begin disp_buf[i] <= disp_string[8*i:8*(i+1)-1]; end else begin @@ -172,4 +178,24 @@ generate begin end endgenerate +// If running oled_wrapper alone +always @ (posedge sys_clk) +begin + chipset_rst_n_f <= sys_rst_n; + chipset_rst_n_ff <= chipset_rst_n_f; +end + +clk_wiz_0 inst + ( + // Clock out ports + .chipset_clk(sys_clk), + // Status and control signals + .resetn(chipset_rst_n_ff), + .locked(locked), + // Clock in ports + .clk_in1_p(clk_osc_p), + .clk_in1_n(clk_osc_n) + ); + + endmodule \ No newline at end of file diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index c963ef52c..b668c1dec 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1584,8 +1584,8 @@ chipset_impl_noc_power_test chipset_impl ( `ifdef GENESYS2_BOARD oled_wrapper #( - .OLED_SYS_CLK_KHZ (50000), - .OLED_SPI_CLK_KHZ (5000) + .OLED_SYS_CLK_KHZ (66667), + .OLED_SPI_CLK_KHZ (10000) ) oled_wrapper ( .sys_clk (chipset_clk ), .sys_rst_n (chipset_rst_n_ff ), From 05c1be9f6fb95f9381d4d1b7561b33ca34508025 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 23 May 2024 12:34:15 -0400 Subject: [PATCH 029/144] Start of work on getting UART boot to work with Genesys2 board. --- piton/tools/src/proto/protosyn,2.5 | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 9921854d2..2b6bbf55b 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -531,7 +531,8 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}): + # do not use SD controller if using UART boot with genesys2 board + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}) or ((options.board == "genesys2") and (options.uart_dmw == "ddr")): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") @@ -623,7 +624,8 @@ def makeDefList(options): else: print_warning("--oled option is ignored for %s" % options.board) elif options.design == "chipset" and (options.board == "genesys2" or options.board == "nexysVideo"): - disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" +# disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" + disp_string = "Hello" defines.append("{OLED_STRING=\\\"%s\\\"}" % disp_string) return defines From b498231495a152a685fb872d797f0c49c94af25d Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 23 May 2024 14:53:03 -0400 Subject: [PATCH 030/144] oled_wrapper back to original configuration. --- piton/design/chipset/oled/rtl/oled_wrapper.v | 25 +++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/piton/design/chipset/oled/rtl/oled_wrapper.v b/piton/design/chipset/oled/rtl/oled_wrapper.v index fcc15d0b6..0c596dd22 100644 --- a/piton/design/chipset/oled/rtl/oled_wrapper.v +++ b/piton/design/chipset/oled/rtl/oled_wrapper.v @@ -24,7 +24,7 @@ // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. module oled_wrapper ( - //input sys_clk, + input sys_clk, input sys_rst_n, input btnl, @@ -32,8 +32,8 @@ module oled_wrapper ( input btnu, input btnd, - input clk_osc_p, - input clk_osc_n, + //input clk_osc_p, + //input clk_osc_n, output spi_sclk, output spi_dc, @@ -77,13 +77,13 @@ wire btnd_pulse; wire last_char; // If used alone -reg chipset_rst_n_f; -reg chipset_rst_n_ff; +//reg chipset_rst_n_f; +//reg chipset_rst_n_ff; assign last_char = char_cnt == (STRING_LEN - 1); always @(posedge sys_clk) begin - if (~chipset_rst_n_ff) begin + if (~sys_rst_n) begin oled_state <= IDLE; char_cnt <= 8'b0; oled_val <= 1'b0; @@ -124,7 +124,7 @@ ssd1306_top #( .SPI_CLK_FREQ_KHZ (OLED_SPI_CLK_KHZ ) ) ssd1306_top ( .sys_clk (sys_clk ), - .sys_rst_n (chipset_rst_n_ff ), + .sys_rst_n (sys_rst_n ), .init_done (init_done ), @@ -157,14 +157,16 @@ assign btnd_pulse = btnd & ~btnd_r; assign btnu_pulse = btnu & ~btnu_r; always @(posedge sys_clk) begin - disp_string <= "Hello"; + // Debug + //disp_string <= "0123456789012345678901234567890123456789012345678901234567891234"; + disp_string <= `OLED_STRING; end generate begin genvar i; for (i = 0; i < 64; i = i + 1) begin: disp_buf_change always @(posedge sys_clk) begin - if (~chipset_rst_n_ff) begin + if (~sys_rst_n) begin disp_buf[i] <= disp_string[8*i:8*(i+1)-1]; end else begin @@ -178,6 +180,7 @@ generate begin end endgenerate +/* // If running oled_wrapper alone always @ (posedge sys_clk) begin @@ -195,7 +198,7 @@ clk_wiz_0 inst // Clock in ports .clk_in1_p(clk_osc_p), .clk_in1_n(clk_osc_n) - ); + );*/ -endmodule \ No newline at end of file +endmodule From 89750e341d29e5430768cdfb9143889c988cc13b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 23 May 2024 14:57:58 -0400 Subject: [PATCH 031/144] Revert of oled_wrapper back to 2074658326ced5837ee8a00be3acee7dc48167ff --- piton/design/chipset/oled/rtl/oled_wrapper.v | 33 ++------------------ 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/piton/design/chipset/oled/rtl/oled_wrapper.v b/piton/design/chipset/oled/rtl/oled_wrapper.v index 0c596dd22..879ec3993 100644 --- a/piton/design/chipset/oled/rtl/oled_wrapper.v +++ b/piton/design/chipset/oled/rtl/oled_wrapper.v @@ -31,9 +31,6 @@ module oled_wrapper ( input btnr, input btnu, input btnd, - - //input clk_osc_p, - //input clk_osc_n, output spi_sclk, output spi_dc, @@ -76,9 +73,6 @@ wire btnd_pulse; wire last_char; -// If used alone -//reg chipset_rst_n_f; -//reg chipset_rst_n_ff; assign last_char = char_cnt == (STRING_LEN - 1); @@ -157,9 +151,7 @@ assign btnd_pulse = btnd & ~btnd_r; assign btnu_pulse = btnu & ~btnu_r; always @(posedge sys_clk) begin - // Debug - //disp_string <= "0123456789012345678901234567890123456789012345678901234567891234"; - disp_string <= `OLED_STRING; + disp_string <= `OLED_STRING; end generate begin @@ -180,25 +172,4 @@ generate begin end endgenerate -/* -// If running oled_wrapper alone -always @ (posedge sys_clk) -begin - chipset_rst_n_f <= sys_rst_n; - chipset_rst_n_ff <= chipset_rst_n_f; -end - -clk_wiz_0 inst - ( - // Clock out ports - .chipset_clk(sys_clk), - // Status and control signals - .resetn(chipset_rst_n_ff), - .locked(locked), - // Clock in ports - .clk_in1_p(clk_osc_p), - .clk_in1_n(clk_osc_n) - );*/ - - -endmodule +endmodule \ No newline at end of file From e7258148021affd1d1306b2cb609a3a4d5024431 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 29 May 2024 10:51:15 -0400 Subject: [PATCH 032/144] Modifications to permit bitstream generation on genesys2 for: protosyn --board genesys2 --design chipset --core ariane --jobs 64 --uart-dmw ddr --- piton/design/chipset/oled/rtl/oled_wrapper.v | 3 +- piton/design/chipset/rtl/chipset.v | 6 +- .../chipset/xilinx/genesys2/constraints.xdc | 123 +++++++++--------- 3 files changed, 68 insertions(+), 64 deletions(-) diff --git a/piton/design/chipset/oled/rtl/oled_wrapper.v b/piton/design/chipset/oled/rtl/oled_wrapper.v index 879ec3993..dd5c9943e 100644 --- a/piton/design/chipset/oled/rtl/oled_wrapper.v +++ b/piton/design/chipset/oled/rtl/oled_wrapper.v @@ -152,6 +152,7 @@ assign btnu_pulse = btnu & ~btnu_r; always @(posedge sys_clk) begin disp_string <= `OLED_STRING; + //disp_string <= "0123456789012345678901234567890123456789012345678901234567891234"; end generate begin @@ -172,4 +173,4 @@ generate begin end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index b668c1dec..9f362320d 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -804,9 +804,9 @@ end assign leds[0] = clk_locked; assign leds[1] = ~piton_ready_n; assign leds[2] = init_calib_complete; - assign leds[3] = processor_offchip_noc2_valid; - assign leds[4] = offchip_processor_noc3_valid; - assign leds[5] = 1'b0; + assign leds[3] = 1'b0; + assign leds[4] = piton_prsnt_n; + assign leds[5] = chipset_rst_n_ff; assign leds[6] = invalid_access; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 8df0066be..6db533c99 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -33,10 +33,10 @@ set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_ # Non-MMCM clock constraints #create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] -create_clock -period 5.000 -name passthru_chipset_clk_n -waveform {2.500 5.000} [get_ports passthru_chipset_clk_n] -create_clock -period 5.000 -name passthru_chipset_clk -waveform {0.000 2.500} [get_pins passthru_chipset_clk_ibufgds/O] -create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] -create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] +#create_clock -period 5.000 -name passthru_chipset_clk_n -waveform {2.500 5.000} [get_ports passthru_chipset_clk_n] +#create_clock -period 5.000 -name passthru_chipset_clk -waveform {0.000 2.500} [get_pins passthru_chipset_clk_ibufgds/O] +#create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] +#create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] # Assuming that io_clk has to be created like chipset_passthru_clk_p (RR 2024/05/21) create_clock -period 5.000 -name io_clk -waveform {0.000 2.500} [get_ports io_clk] create_clock -period 5.000 -name core_ref_clk -waveform {0.000 2.500} [get_ports core_ref_clk] @@ -98,22 +98,22 @@ set_property PACKAGE_PIN G19 [get_ports {sw[0]}] #set_property PACKAGE_PIN E18 [get_ports pin_soft_rst] # SD -set_property IOSTANDARD LVCMOS33 [get_ports sd_clk_out] -set_property PACKAGE_PIN R28 [get_ports sd_clk_out] -set_property IOSTANDARD LVCMOS33 [get_ports sd_cmd] -set_property PACKAGE_PIN R29 [get_ports sd_cmd] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[0]}] -set_property PACKAGE_PIN R26 [get_ports {sd_dat[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[1]}] -set_property PACKAGE_PIN R30 [get_ports {sd_dat[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[2]}] -set_property PACKAGE_PIN P29 [get_ports {sd_dat[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[3]}] -set_property PACKAGE_PIN T30 [get_ports {sd_dat[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports sd_reset] -set_property PACKAGE_PIN AE24 [get_ports sd_reset] -set_property IOSTANDARD LVCMOS33 [get_ports sd_cd] -set_property PACKAGE_PIN P28 [get_ports sd_cd] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_clk_out] +#set_property PACKAGE_PIN R28 [get_ports sd_clk_out] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_cmd] +#set_property PACKAGE_PIN R29 [get_ports sd_cmd] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[0]}] +#set_property PACKAGE_PIN R26 [get_ports {sd_dat[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[1]}] +#set_property PACKAGE_PIN R30 [get_ports {sd_dat[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[2]}] +#set_property PACKAGE_PIN P29 [get_ports {sd_dat[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[3]}] +#set_property PACKAGE_PIN T30 [get_ports {sd_dat[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_reset] +#set_property PACKAGE_PIN AE24 [get_ports sd_reset] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_cd] +#set_property PACKAGE_PIN P28 [get_ports sd_cd] ## LEDs @@ -153,6 +153,9 @@ set_property PACKAGE_PIN M19 [get_ports btnd] set_property IOSTANDARD LVCMOS25 [get_ports btnd] set_property PACKAGE_PIN B19 [get_ports btnu] set_property IOSTANDARD LVCMOS25 [get_ports btnu] +# piton_prsnt_n for Genesys2 chipset target (RR 2024/05/28) +set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] +set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] ## Ethernet @@ -224,15 +227,15 @@ set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS25} [get_ports intf_chip_da #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[12]] -set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] -set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] +#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] +#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[2]}] #set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] #set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[2]] -set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] -set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] +#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] +#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[0]}] #set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] @@ -472,10 +475,10 @@ set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports intf_chip_da #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[22]] -set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] -set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] -set_property PULLUP true [get_ports piton_prsnt_n] -set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] +#set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] +#set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] +#set_property PULLUP true [get_ports piton_prsnt_n] +#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] #set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] @@ -657,16 +660,16 @@ set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS25} [get_ports chip_intf_da #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[2]] -set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] -set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] -set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS25 } [get_ports { F79_N }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] -set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS25 } [get_ports { F79_P }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS25 } [get_ports { F79_N }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS25 } [get_ports { F79_P }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] ### False paths -set_clock_groups -name sync_gr1 -logically_exclusive -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] -set_false_path -from [get_clocks clk_osc_p] -to [get_clocks clk_osc_n] -set_false_path -from [get_clocks clk_osc_n] -to [get_clocks clk_osc_p] +#set_clock_groups -name sync_gr1 -logically_exclusive -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] +#set_false_path -from [get_clocks clk_osc_p] -to [get_clocks clk_osc_n] +#set_false_path -from [get_clocks clk_osc_n] -to [get_clocks clk_osc_p] #set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks chipset_clk_mmcm_1] #set_false_path -from [get_clocks chipset_clk_clk_mmcm_1] -to [get_clocks chipset_clk_clk_mmcm] #set_false_path -from [get_clocks clk_pll_i_1] -to [get_clocks clk_pll_i] @@ -697,28 +700,28 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] ############################################# # SD Card Constraints for 25MHz ############################################# -create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] -create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] -create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] -create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] -create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000} -create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000} -set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd] -set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd] -set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd] -set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd] -set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] -set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] -set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] +#create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] +#create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] +#create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] +#create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] +#create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000} +#create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000} +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd] +#set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] +#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] +#set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] From 0a9adf2ff3ff168437dddd602e9829ce9e1c2d03 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 29 May 2024 14:42:03 -0400 Subject: [PATCH 033/144] Initial revision --- .../design/chip/xilinx/vc707/constraints.xdc | 162 ++++++++++++++++++ piton/design/chip/xilinx/vc707/devices.xml | 66 +++++++ .../chip/xilinx/vc707/devices_ariane.xml | 84 +++++++++ 3 files changed, 312 insertions(+) create mode 100644 piton/design/chip/xilinx/vc707/constraints.xdc create mode 100644 piton/design/chip/xilinx/vc707/devices.xml create mode 100644 piton/design/chip/xilinx/vc707/devices_ariane.xml diff --git a/piton/design/chip/xilinx/vc707/constraints.xdc b/piton/design/chip/xilinx/vc707/constraints.xdc new file mode 100644 index 000000000..db5d30706 --- /dev/null +++ b/piton/design/chip/xilinx/vc707/constraints.xdc @@ -0,0 +1,162 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Clock signals +set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN E19 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN E18 [get_ports chipset_clk_osc_n] +set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_n] + +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clk_in1_clk_mmcm] + +# Reset +set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] +set_property PACKAGE_PIN AV40 [get_ports sys_rst_n] + +# False paths +set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] +set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*] +set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*] +set_false_path -to [get_cells -hierarchical *init_calib_complete_f*] +set_false_path -to [get_cells -hierarchical *chipset_rst_n*] +set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] + +set_clock_groups -name sync_gr1 -logically_exclusive -group chipset_clk_clk_mmcm -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] + +# UART +#IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +set_property IOSTANDARD LVCMOS18 [get_ports uart_tx] +set_property PACKAGE_PIN AU36 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_rx] +set_property PACKAGE_PIN AU33 [get_ports uart_rx] + +# Switches +set_property PACKAGE_PIN AV30 [get_ports sw[0]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[0]] +set_property PACKAGE_PIN AY33 [get_ports sw[1]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[1]] +set_property PACKAGE_PIN BA31 [get_ports sw[2]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[2]] +set_property PACKAGE_PIN BA32 [get_ports sw[3]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[3]] +set_property PACKAGE_PIN AW30 [get_ports sw[4]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[4]] +set_property PACKAGE_PIN AY30 [get_ports sw[5]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[5]] +set_property PACKAGE_PIN BA30 [get_ports sw[6]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[6]] +set_property PACKAGE_PIN BB31 [get_ports sw[7]] +set_property IOSTANDARD LVCMOS18 [get_ports sw[7]] + +# SD +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AN30 DRIVE 16 SLEW FAST} [get_ports sd_clk_out] +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AP30} [get_ports sd_cmd] +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AR30} [get_ports {sd_dat[0]}] +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AU31} [get_ports {sd_dat[1]}] +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AV31} [get_ports {sd_dat[2]}] +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AT30} [get_ports {sd_dat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports sd_cd] +# set_property PACKAGE_PIN AP32 [get_ports sd_cd] + +#set_property PACKAGE_PIN AV30 [get_ports uart_lb_sw] +#set_property IOSTANDARD LVCMOS18 [get_ports uart_lb_sw] + +## LEDs + +set_property PACKAGE_PIN AM39 [get_ports leds[0]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[0]] +set_property PACKAGE_PIN AN39 [get_ports leds[1]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[1]] +set_property PACKAGE_PIN AR37 [get_ports leds[2]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[2]] +set_property PACKAGE_PIN AT37 [get_ports leds[3]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[3]] +set_property PACKAGE_PIN AR35 [get_ports leds[4]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[4]] +set_property PACKAGE_PIN AP41 [get_ports leds[5]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[5]] +set_property PACKAGE_PIN AP42 [get_ports leds[6]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[6]] +set_property PACKAGE_PIN AU39 [get_ports leds[7]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[7]] + +############################################# +# SD Card Constraints for 25MHz +############################################# +create_generated_clock -name sd_fast_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] +create_generated_clock -name sd_slow_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] +create_generated_clock -name sd_clk_out -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] +create_generated_clock -name sd_clk_out_1 -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] + +# compensate for board trace uncertainty +set_clock_uncertainty 0.500 [get_clocks sd_clk_out] +set_clock_uncertainty 0.500 [get_clocks sd_clk_out_1] + +################# +# FPGA out / card in +# data is aligned with clock (source synchronous) + +# hold fast (spec requires minimum 2ns), note that data is launched on falling edge, so 0.0 is ok here +set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports {sd_dat[*]}] +set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports sd_cmd] + +# setup fast (spec requires minimum 6ns) +set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports {sd_dat[*]}] +set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports sd_cmd] + +# hold slow (spec requires minimum 5ns), note that data is launched on falling edge, so 0.0 is ok here +set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports {sd_dat[*]}] +set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports sd_cmd] + +# setup slow (spec requires minimum 5ns) +set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports {sd_dat[*]}] +set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports sd_cmd] + +################# +# card out / FPGA in +# data is launched on negative clock edge here + +# propdelay fast +set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] +set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] + +# contamination delay fast +set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] +set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] + +# propdelay slow +set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] +set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] + +# contamination slow +set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] +set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] + +################# +# clock groups + +set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] +set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks sd_fast_clk] -group [get_clocks -include_generated_clocks sd_slow_clk] +set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] -group [get_clocks -filter { NAME =~ "*sd*" }] diff --git a/piton/design/chip/xilinx/vc707/devices.xml b/piton/design/chip/xilinx/vc707/devices.xml new file mode 100644 index 000000000..f0e70024c --- /dev/null +++ b/piton/design/chip/xilinx/vc707/devices.xml @@ -0,0 +1,66 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + sd + 0xf000000000 + + 0xff0300000 + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + diff --git a/piton/design/chip/xilinx/vc707/devices_ariane.xml b/piton/design/chip/xilinx/vc707/devices_ariane.xml new file mode 100644 index 000000000..b86978353 --- /dev/null +++ b/piton/design/chip/xilinx/vc707/devices_ariane.xml @@ -0,0 +1,84 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + sd + 0xf000000000 + + 0xff0300000 + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + + From 1a2a4d52d2ed884dd7672da77b578933c53d1b38 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 29 May 2024 15:58:33 -0400 Subject: [PATCH 034/144] Added ip_cores to synthesize chip on VC707 --- .../ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci | 713 ++++++++++++++++++ 1 file changed, 713 insertions(+) create mode 100644 piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci diff --git a/piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci b/piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci new file mode 100644 index 000000000..6e96ea80e --- /dev/null +++ b/piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci @@ -0,0 +1,713 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm_chip + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 100.0 + 0000 + 0000 + 66.66667 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 66.66667 + 0.000 + 50.000 + 66.666 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + core_ref_clk + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________200____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 3.000 + 0.000 + FALSE + 5.0 + 10.0 + 9.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 1 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + core_ref_clk__66.66667______0.000______50.0______117.498____105.563 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 200 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1440.000 + 600.000 + clk_mmcm_chip + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + BUFG + 117.498 + false + 105.563 + 50.000 + 66.666 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + core_ref_clk + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_mmcm_chip + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 3.000 + 0.000 + false + 5.0 + 10.0 + 9.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 200 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtex7 + xilinx.com:vc707:part0:1.1 + + xc7vx485t + ffg1761 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 8 + TRUE + ../../../../vc707_chip.gen/sources_1/ip/clk_mmcm_chip + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 9e4a1820b36ecfe7b7e70c83ae7ca02f485956b6 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 29 May 2024 15:59:13 -0400 Subject: [PATCH 035/144] Adding option to generate chip for VC707 --- piton/tools/src/proto/block.list | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 056f6862c..b38eb662f 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -29,7 +29,7 @@ system . chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 -chip chip genesys2,66.667,1024 +chip chip genesys2,66.667,1024;vc707,66.667,1024 chip_bridge_test_fpga fpga_tests/chip_bridge_test/chip_bridge_test_fpga genesys2,66.667,1024;piton_board,50,0 chip_bridge_test_chip fpga_tests/chip_bridge_test/chip_bridge_test_chip genesys2,66.667,1024;piton_board,50,0 memctrl_test fpga_tests/memio_unit_tests/memctrl_test genesys2,100,1024 From c56595ef474e5f0e312051889c99af234e48028d Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 29 May 2024 15:59:46 -0400 Subject: [PATCH 036/144] Clearer error message. --- piton/tools/src/proto/pitonstream,1.0 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/pitonstream,1.0 b/piton/tools/src/proto/pitonstream,1.0 index 18db5b434..7b4f5566a 100755 --- a/piton/tools/src/proto/pitonstream,1.0 +++ b/piton/tools/src/proto/pitonstream,1.0 @@ -172,7 +172,8 @@ def configureUART(port): stopbits=serial.STOPBITS_ONE, timeout=0 ) - except: + except Exception as error: + print("An exception occurred:", error) print_error("Can not open serial device %s" % port_full) print_error("Provide correct device name using -p option") return None From cd8ccbf1105e82b41b49ab4d8f3dadaf6504902c Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 30 May 2024 10:12:12 -0400 Subject: [PATCH 037/144] noc_axilite_bridge.v necessary for vc707 chip targetting. --- piton/tools/src/proto/common/rtl_setup.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 1b8838ea5..aa0c08c61 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -702,6 +702,7 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_err_slv.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_cdc.sv" \ "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ + "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ ] From bed7aec8dcf5ae023dac41a0a1bd33fb004d4974 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 4 Jun 2024 13:40:17 -0400 Subject: [PATCH 038/144] Copied from piton/design/chip/chip_bridge/xilinx/genesys2 allows to pass synthesis on genesys2 with chip bridge. --- .../ip_cores/afifo_w3_d16/afifo_w3_d16.xci | 584 ++++++++++++++++++ .../ip_cores/afifo_w64_d16/afifo_w64_d16.xci | 584 ++++++++++++++++++ .../ip_cores/fifo_w3_d16/fifo_w3_d16.xci | 580 +++++++++++++++++ .../ip_cores/fifo_w64_d16/fifo_w64_d16.xci | 580 +++++++++++++++++ 4 files changed, 2328 insertions(+) create mode 100644 piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w3_d16/afifo_w3_d16.xci create mode 100644 piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w64_d16/afifo_w64_d16.xci create mode 100644 piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/fifo_w3_d16/fifo_w3_d16.xci create mode 100644 piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/fifo_w64_d16/fifo_w64_d16.xci diff --git a/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w3_d16/afifo_w3_d16.xci b/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w3_d16/afifo_w3_d16.xci new file mode 100644 index 000000000..e53491c71 --- /dev/null +++ b/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w3_d16/afifo_w3_d16.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w3_d16 + + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 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xilinx.com:vc707:part0:1.1 + + xc7vx485t + ffg1761 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w64_d16/afifo_w64_d16.xci b/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w64_d16/afifo_w64_d16.xci new file mode 100644 index 000000000..09f328690 --- /dev/null +++ b/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/afifo_w64_d16/afifo_w64_d16.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w64_d16 + + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 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false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtex7 + xilinx.com:vc707:part0:1.1 + + xc7vx485t + ffg1761 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/fifo_w3_d16/fifo_w3_d16.xci b/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/fifo_w3_d16/fifo_w3_d16.xci new file mode 100644 index 000000000..c2b44416c --- /dev/null +++ b/piton/design/chip/chip_bridge/xilinx/vc707/ip_cores/fifo_w3_d16/fifo_w3_d16.xci @@ -0,0 +1,580 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_w3_d16 + + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + 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0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 14 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 5 + 16 + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 5 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 4 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_w64_d16 + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + 0 + 15 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 14 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 64 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 64 + 16 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 5 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + false + 5 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtex7 + xilinx.com:vc707:part0:1.1 + + xc7vx485t + ffg1761 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 03bfd2b88022ee9b2de2a047ebdfdb4bc734e063 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 4 Jun 2024 13:43:32 -0400 Subject: [PATCH 039/144] Added comment for clarity. --- piton/tools/src/proto/pitonstream,1.0 | 1 + 1 file changed, 1 insertion(+) diff --git a/piton/tools/src/proto/pitonstream,1.0 b/piton/tools/src/proto/pitonstream,1.0 index 7b4f5566a..f3d38d2be 100755 --- a/piton/tools/src/proto/pitonstream,1.0 +++ b/piton/tools/src/proto/pitonstream,1.0 @@ -363,6 +363,7 @@ def main(): st_brd = StorageBoard("bram", options.board) if options.storage == "ddr": + print("Storage option selected is ddr.") st_brd = StorageBoard("dmw", options.board) # Get list of tests and board configuration From df3e9136be2579a1ee5b376fb3c47666e894c958 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 4 Jun 2024 13:54:15 -0400 Subject: [PATCH 040/144] Support of new RTL define POLARA_VC707_CHIP (not tested yet). --- piton/design/chip/rtl/chip.v.pyv | 26 ++++++++++++++++++++++---- piton/tools/src/proto/protosyn,2.5 | 18 +++++++++++++++--- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index dbba0fe3f..486df85ba 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -34,14 +34,17 @@ module chip( input impsel2, `endif // endif PITON_CHIP_FPGA -`ifdef PITON_FPGA_CLKS_GEN +`ifdef POLARA_VC707_CHIP + input core_ref_clk, + input io_clk, +`elsifdef PITON_FPGA_CLKS_GEN input clk_osc_p, input clk_osc_n, `else // ifndef PITON_FPGA_CLKS_GEN // Input clocks input core_ref_clk, input io_clk, -`endif // endif PITON_FPGA_CLKS_GEN +`endif // endif POLARA_VC707_CHIP, PITON_FPGA_CLKS_GEN // Resets // reset is assumed to be asynchronous @@ -88,7 +91,16 @@ module chip( `ifndef PITON_NO_CHIP_BRIDGE // For FPGA implementations, we convert to differential and source synchronous -`ifdef PITON_CHIP_FPGA +`ifdef POLARA_VC707_CHIP + // Virtual channel credit-based off-chip interface + input [31:0] intf_chip_data, + input [1:0] intf_chip_channel, + output [2:0] intf_chip_credit_back, + + output [31:0] chip_intf_data, + output [1:0] chip_intf_channel, + input [2:0] chip_intf_credit_back +`elsifdef PITON_CHIP_FPGA output chip_intf_clk_p, output chip_intf_clk_n, input intf_chip_clk_p, @@ -116,7 +128,7 @@ module chip( output [31:0] chip_intf_data, output [1:0] chip_intf_channel, input [2:0] chip_intf_credit_back -`endif // endif PITON_CHIP_FPGA +`endif // endif POLARA_VC707_CHIP, PITON_CHIP_FPGA `else // ifdef PITON_NO_CHIP_BRIDGE output processor_offchip_noc1_valid, output [`NOC_DATA_WIDTH-1:0] processor_offchip_noc1_data, @@ -180,6 +192,7 @@ module chip( wire oram_dummy_gen; `endif // endif PITON_CHIP_FPGA // Same for generating clocks +`ifndef POLARA_VC707_CHIP `ifdef PITON_FPGA_CLKS_GEN wire core_ref_clk; @@ -199,6 +212,7 @@ module chip( wire [2:0] chip_intf_credit_back; `endif // endif PITON_CHIP_FPGA `endif // endif PITON_NO_CHIP_BRIDGE +`endif // endif POLARA_VC707_CHIP // OCI internal wires @@ -670,6 +684,7 @@ module chip( ///////////////////////// // Need to generate clocks from MMCM for standalone chip FPGA synthesis +`ifndef POLARA_VC707_CHIP `ifdef PITON_FPGA_CLKS_GEN // Generate core_ref_clk clk_mmcm_chip clk_mmcm ( @@ -682,7 +697,9 @@ module chip( .core_ref_clk(core_ref_clk) ); `endif // endif PITON_FPGA_CLKS_GEN +`endif // endif POLARA_VC707_CHIP +`ifndef POLARA_VC707_CHIP `ifndef PITON_NO_CHIP_BRIDGE `ifdef PITON_CHIP_FPGA // Generate io_clk from input @@ -731,6 +748,7 @@ module chip( ); `endif // endif PITON_CHIP_FPGA `endif // endif PITON_NO_CHIP_BRIDGE +`endif // endif POLARA_VC707_CHIP // Off-Chip Interface Block diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 2b6bbf55b..e82411db8 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -143,6 +143,10 @@ def usage(): print(" Number of jobs to use in Vivado implementation flow", file=sys.stderr) print("\n --postroutephysopt", file=sys.stderr) print(" Use post-route physical optimisation in Vivado implementation flow (can improve timing, not recommended by default)", file=sys.stderr) +# parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) + print("\n --vc707chip", file=sys.stderr) + print(" Sets POLARA_VC707_CHIP rtl define used to recreate Polara chip on VC707 FPGA (False by default)", file=sys.stderr) + print(" Assumes vc707 board is chosen", file=sys.stderr) print("\n -h, --help", file=sys.stderr) print(" Display this help message and exit", file=sys.stderr) print("\n", file=sys.stderr) @@ -494,6 +498,7 @@ def setParserOptions(parser): parser.add_option("--axi4_mem", dest="axi4_mem", action="store_true", default=False) parser.add_option("--zeroer_off", dest="zeroer_off", action="store_true", default=False) parser.add_option("--postroutephysopt", dest="postroutephysopt", action="store_true", default=False) + parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) return parser @@ -532,7 +537,8 @@ def makeDefList(options): # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd # do not use SD controller if using UART boot with genesys2 board - if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}) or ((options.board == "genesys2") and (options.uart_dmw == "ddr")): + # do not use SD controller if targetting chip to vc707 board + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}) or ((options.board == "genesys2") and (options.uart_dmw == "ddr")) or ((options.design == "chip") and (options.board == "vc707")): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") @@ -559,6 +565,9 @@ def makeDefList(options): # --chip-bridge option if (options.board == "piton_board") and (options.design == "chipset"): pass + # VC707 chip emulation needs the chip bridge + elif (options.design == "chip") and (options.board == "vc707"): + pass # chip-bridge is used for chipset by default elif options.chip_bridge == False and options.design != "chipset": defines.append("PITON_NO_CHIP_BRIDGE") @@ -624,10 +633,13 @@ def makeDefList(options): else: print_warning("--oled option is ignored for %s" % options.board) elif options.design == "chipset" and (options.board == "genesys2" or options.board == "nexysVideo"): -# disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" - disp_string = "Hello" + disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" + #disp_string = "Hello" defines.append("{OLED_STRING=\\\"%s\\\"}" % disp_string) + if options.polara_vc707_chip_flag == True: + defines.append("POLARA_VC707_CHIP") + return defines def makeMemMapping(st_brd, work_dir, log_dir): From a1c7a8a8fbf0ae2f30184911b1cccaeada0be95d Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 4 Jun 2024 14:07:48 -0400 Subject: [PATCH 041/144] Corrected syntax. --- piton/design/chip/rtl/chip.v.pyv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 486df85ba..d5abf6f1a 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -37,7 +37,7 @@ module chip( `ifdef POLARA_VC707_CHIP input core_ref_clk, input io_clk, -`elsifdef PITON_FPGA_CLKS_GEN +`elsif PITON_FPGA_CLKS_GEN input clk_osc_p, input clk_osc_n, `else // ifndef PITON_FPGA_CLKS_GEN @@ -100,7 +100,7 @@ module chip( output [31:0] chip_intf_data, output [1:0] chip_intf_channel, input [2:0] chip_intf_credit_back -`elsifdef PITON_CHIP_FPGA +`elsif PITON_CHIP_FPGA output chip_intf_clk_p, output chip_intf_clk_n, input intf_chip_clk_p, From 89305cdbf8cd653904ecb44f85d3ced6ef60dc80 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 08:50:27 -0400 Subject: [PATCH 042/144] Added missing ifdef with POLARA_VC707_CHIP define. --- piton/design/chip/rtl/chip.v.pyv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index d5abf6f1a..8db9fcbf2 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -555,7 +555,9 @@ module chip( assign piton_ready_n = ~rst_n_inter_sync; `ifdef PITON_FPGA_CLKS_GEN +`ifndef POLARA_VC707_CHIP assign leds[0] = mmcm_locked; +`endif // endif POLARA_VC707_CHIP `else // ifndef PITON_FPGA_CLKS_GEN assign leds[0] = 1'b1; `endif // endif PITON_FPGA_CLKS_GEN From 686d1b6e5a55a9817ca0d574d3f378f996f507c4 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 08:54:36 -0400 Subject: [PATCH 043/144] Constraints for vc707 implementation of 1 core of polara without FP on ARA. --- .../design/chip/xilinx/vc707/constraints.xdc | 236 +++++++++++++----- 1 file changed, 171 insertions(+), 65 deletions(-) diff --git a/piton/design/chip/xilinx/vc707/constraints.xdc b/piton/design/chip/xilinx/vc707/constraints.xdc index db5d30706..831b693a0 100644 --- a/piton/design/chip/xilinx/vc707/constraints.xdc +++ b/piton/design/chip/xilinx/vc707/constraints.xdc @@ -24,59 +24,65 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # Clock signals -set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_p] -set_property PACKAGE_PIN E19 [get_ports chipset_clk_osc_p] -set_property PACKAGE_PIN E18 [get_ports chipset_clk_osc_n] -set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_p] +#set_property PACKAGE_PIN E19 [get_ports chipset_clk_osc_p] +#set_property PACKAGE_PIN E18 [get_ports chipset_clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports clk_osc_p] +#set_property PACKAGE_PIN E19 [get_ports clk_osc_p] +#set_property PACKAGE_PIN E18 [get_ports clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports clk_osc_n] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clk_in1_clk_mmcm] +#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clk_in1_clk_mmcm] # Reset -set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] -set_property PACKAGE_PIN AV40 [get_ports sys_rst_n] +#set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] +#set_property PACKAGE_PIN AV40 [get_ports sys_rst_n] +set_property IOSTANDARD LVCMOS18 [get_ports rst_n] +set_property PACKAGE_PIN AV40 [get_ports rst_n] # False paths -set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] -set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*] -set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*] -set_false_path -to [get_cells -hierarchical *init_calib_complete_f*] -set_false_path -to [get_cells -hierarchical *chipset_rst_n*] -set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] +#set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] +#set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*] +#set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*] +#set_false_path -to [get_cells -hierarchical *init_calib_complete_f*] +#set_false_path -to [get_cells -hierarchical *chipset_rst_n*] +#set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] -set_clock_groups -name sync_gr1 -logically_exclusive -group chipset_clk_clk_mmcm -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] +#set_clock_groups -name sync_gr1 -logically_exclusive -group chipset_clk_clk_mmcm -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] # UART #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -set_property IOSTANDARD LVCMOS18 [get_ports uart_tx] -set_property PACKAGE_PIN AU36 [get_ports uart_tx] -set_property IOSTANDARD LVCMOS18 [get_ports uart_rx] -set_property PACKAGE_PIN AU33 [get_ports uart_rx] +#set_property IOSTANDARD LVCMOS18 [get_ports uart_tx] +#set_property PACKAGE_PIN AU36 [get_ports uart_tx] +#set_property IOSTANDARD LVCMOS18 [get_ports uart_rx] +#set_property PACKAGE_PIN AU33 [get_ports uart_rx] # Switches -set_property PACKAGE_PIN AV30 [get_ports sw[0]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[0]] -set_property PACKAGE_PIN AY33 [get_ports sw[1]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[1]] -set_property PACKAGE_PIN BA31 [get_ports sw[2]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[2]] -set_property PACKAGE_PIN BA32 [get_ports sw[3]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[3]] -set_property PACKAGE_PIN AW30 [get_ports sw[4]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[4]] -set_property PACKAGE_PIN AY30 [get_ports sw[5]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[5]] -set_property PACKAGE_PIN BA30 [get_ports sw[6]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[6]] -set_property PACKAGE_PIN BB31 [get_ports sw[7]] -set_property IOSTANDARD LVCMOS18 [get_ports sw[7]] +#set_property PACKAGE_PIN AV30 [get_ports sw[0]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[0]] +#set_property PACKAGE_PIN AY33 [get_ports sw[1]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[1]] +#set_property PACKAGE_PIN BA31 [get_ports sw[2]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[2]] +#set_property PACKAGE_PIN BA32 [get_ports sw[3]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[3]] +#set_property PACKAGE_PIN AW30 [get_ports sw[4]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[4]] +#set_property PACKAGE_PIN AY30 [get_ports sw[5]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[5]] +#set_property PACKAGE_PIN BA30 [get_ports sw[6]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[6]] +#set_property PACKAGE_PIN BB31 [get_ports sw[7]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[7]] # SD -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AN30 DRIVE 16 SLEW FAST} [get_ports sd_clk_out] -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AP30} [get_ports sd_cmd] -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AR30} [get_ports {sd_dat[0]}] -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AU31} [get_ports {sd_dat[1]}] -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AV31} [get_ports {sd_dat[2]}] -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AT30} [get_ports {sd_dat[3]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AN30 DRIVE 16 SLEW FAST} [get_ports sd_clk_out] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AP30} [get_ports sd_cmd] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AR30} [get_ports {sd_dat[0]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AU31} [get_ports {sd_dat[1]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AV31} [get_ports {sd_dat[2]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AT30} [get_ports {sd_dat[3]}] # set_property IOSTANDARD LVCMOS18 [get_ports sd_cd] # set_property PACKAGE_PIN AP32 [get_ports sd_cd] @@ -105,58 +111,158 @@ set_property IOSTANDARD LVCMOS18 [get_ports leds[7]] ############################################# # SD Card Constraints for 25MHz ############################################# -create_generated_clock -name sd_fast_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] -create_generated_clock -name sd_slow_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] -create_generated_clock -name sd_clk_out -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] -create_generated_clock -name sd_clk_out_1 -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] +#create_generated_clock -name sd_fast_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] +#create_generated_clock -name sd_slow_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] +#create_generated_clock -name sd_clk_out -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] +#create_generated_clock -name sd_clk_out_1 -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] # compensate for board trace uncertainty -set_clock_uncertainty 0.500 [get_clocks sd_clk_out] -set_clock_uncertainty 0.500 [get_clocks sd_clk_out_1] +#set_clock_uncertainty 0.500 [get_clocks sd_clk_out] +#set_clock_uncertainty 0.500 [get_clocks sd_clk_out_1] ################# # FPGA out / card in # data is aligned with clock (source synchronous) # hold fast (spec requires minimum 2ns), note that data is launched on falling edge, so 0.0 is ok here -set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports sd_cmd] # setup fast (spec requires minimum 6ns) -set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports sd_cmd] # hold slow (spec requires minimum 5ns), note that data is launched on falling edge, so 0.0 is ok here -set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports sd_cmd] # setup slow (spec requires minimum 5ns) -set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports sd_cmd] ################# # card out / FPGA in # data is launched on negative clock edge here # propdelay fast -set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] # contamination delay fast -set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] # propdelay slow -set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] # contamination slow -set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] ################# # clock groups -set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] -set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks sd_fast_clk] -group [get_clocks -include_generated_clocks sd_slow_clk] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] -group [get_clocks -filter { NAME =~ "*sd*" }] +#set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] +#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks sd_fast_clk] -group [get_clocks -include_generated_clocks sd_slow_clk] +#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] -group [get_clocks -filter { NAME =~ "*sd*" }] + +############################################# +# FMC +############################################# +# Clock signals from chipset + +create_clock -period 14.9999993 -name io_clk -waveform {0.000 7.49999965} [get_ports io_clk] +create_clock -period 14.9999993 -name core_ref_clk -waveform {0.000 7.49999965} [get_ports core_ref_clk] + +set_property -dict {PACKAGE_PIN L39 IOSTANDARD LVCMOS18} [get_ports io_clk] +set_property -dict {PACKAGE_PIN L40 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] + +#[Place 30-876] Port 'core_ref_clk' is assigned to PACKAGE_PIN 'L40' which can only be used as the N side of a differential clock input. +#Please use the following constraint(s) to pass this DRC check: +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {core_ref_clk_IBUF}] + +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] + +set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] + +set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN C33 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] + +set_property -dict {PACKAGE_PIN B39 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] + +set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN J37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN E37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN H38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN A35 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN H33 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN E33 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN F36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN B37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN D37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN C35 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN G36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN F34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN G32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN E34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN E32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN D35 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN J36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN H28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN B34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN B32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN C38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] + +set_property -dict {PACKAGE_PIN A37 IOSTANDARD LVCMOS18} [get_ports piton_prsnt_n] +set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports piton_ready_n] + +set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN F39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN L31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[14]] +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN V30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] + +set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN U31 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] \ No newline at end of file From 23d616c0db793d23680f89ae293b431ed5d5b2f8 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 13:05:11 -0400 Subject: [PATCH 044/144] Generating chip on vc707 with 50MHz clock. --- piton/design/chip/xilinx/vc707/constraints.xdc | 8 ++++++-- piton/tools/src/proto/block.list | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/piton/design/chip/xilinx/vc707/constraints.xdc b/piton/design/chip/xilinx/vc707/constraints.xdc index 831b693a0..369ce1601 100644 --- a/piton/design/chip/xilinx/vc707/constraints.xdc +++ b/piton/design/chip/xilinx/vc707/constraints.xdc @@ -172,8 +172,12 @@ set_property IOSTANDARD LVCMOS18 [get_ports leds[7]] ############################################# # Clock signals from chipset -create_clock -period 14.9999993 -name io_clk -waveform {0.000 7.49999965} [get_ports io_clk] -create_clock -period 14.9999993 -name core_ref_clk -waveform {0.000 7.49999965} [get_ports core_ref_clk] +# 66.6667MHz +#create_clock -period 14.9999993 -name io_clk -waveform {0.000 7.49999965} [get_ports io_clk] +#create_clock -period 14.9999993 -name core_ref_clk -waveform {0.000 7.49999965} [get_ports core_ref_clk] +# 64MHz +create_clock -period 15.625 -name io_clk -waveform {0.000 7.8125} [get_ports io_clk] +create_clock -period 15.625 -name core_ref_clk -waveform {0.000 7.8125} [get_ports core_ref_clk] set_property -dict {PACKAGE_PIN L39 IOSTANDARD LVCMOS18} [get_ports io_clk] set_property -dict {PACKAGE_PIN L40 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index b38eb662f..cf6c34b4a 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -29,7 +29,7 @@ system . chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 -chip chip genesys2,66.667,1024;vc707,66.667,1024 +chip chip genesys2,66.667,1024;vc707,64,1024 chip_bridge_test_fpga fpga_tests/chip_bridge_test/chip_bridge_test_fpga genesys2,66.667,1024;piton_board,50,0 chip_bridge_test_chip fpga_tests/chip_bridge_test/chip_bridge_test_chip genesys2,66.667,1024;piton_board,50,0 memctrl_test fpga_tests/memio_unit_tests/memctrl_test genesys2,100,1024 From 53a7b3cee475579b6b85b03f90ac156126e843d1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 15:17:32 -0400 Subject: [PATCH 045/144] Modification so pitonstream can compile c code. --- piton/tools/bin/rv64_cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/piton/tools/bin/rv64_cc b/piton/tools/bin/rv64_cc index 3c6177555..7f4e4d481 100755 --- a/piton/tools/bin/rv64_cc +++ b/piton/tools/bin/rv64_cc @@ -32,17 +32,16 @@ RISCV_LDFLAGS="-static -nostartfiles -lm -Wl,--gc-sections -T ${DV_ROOT}/verif/d #---------------------------------------------------------- # Build #---------------------------------------------------------- -RISCV_V_LLVM="${RISCV_V_LLVM_PATH}/bin/clang" +RISCV_V_LLVM="${DV_ROOT}/design/chip/tile/ara/install/riscv-llvm/bin/clang" RISCV_LINK_OPTS="-nostdlib ${RISCV_LDFLAGS} ${LLVM_FLAGS} -DDEFINE_MALLOC -DDEFINE_REALLOC -DDEFINE_FREE -Werror-implicit-function-declaration -fno-math-errno -Wl,-Map=diag.map" - -RISCV_V_LLVM_OPTS="-DPREALLOCATE=1 -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf $2 -DPITON_NUMTILES=${PITON_NUM_TILES}" +RISCV_V_LLVM_OPTS="-DPREALLOCATE=1 -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf $2" INCS="-I${DV_ROOT}/verif/diag/assembly/include/riscv/ariane" ARA_INCS="-I${DV_ROOT}/design/chip/tile/ara/apps/riscv-tests/isa/macros/vector" -${RISCV_V_LLVM} ${INCS} ${ARA_INCS} ${RISCV_V_LLVM_OPTS} -o diag.exe $1 \ +${RISCV_V_LLVM} ${INCS} ${ARA_INCS} ${RISCV_V_LLVM_OPTS} -o diag.exe $1 \ ${DV_ROOT}/verif/diag/assembly/include/riscv/ariane/syscalls.c \ ${DV_ROOT}/verif/diag/assembly/include/riscv/ariane/crt.S \ ${RISCV_LINK_OPTS} -riscv64-unknown-elf-objdump -D diag.exe > diag.objdump \ No newline at end of file +riscv64-unknown-elf-objdump -D diag.exe > diag.objdump From 155af001088134362e8676c6e1d69a660a0f93b1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 15:19:47 -0400 Subject: [PATCH 046/144] For vc707 chip target. --- piton/design/chip/xilinx/design.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/piton/design/chip/xilinx/design.tcl b/piton/design/chip/xilinx/design.tcl index dec2006a6..9dd74eb55 100644 --- a/piton/design/chip/xilinx/design.tcl +++ b/piton/design/chip/xilinx/design.tcl @@ -32,7 +32,8 @@ set DESIGN_NAME "chip" set DESIGN_INCLUDE_DIRS "" -set DESIGN_DEFAULT_VERILOG_MACROS "PITON_CHIP_FPGA FPGA_SYN_1THREAD PITON_FPGA_NO_DMBR MERGE_L1_DCACHE CONFIG_DISABLE_BIST_CLEAR" +# set DESIGN_DEFAULT_VERILOG_MACROS "PITON_CHIP_FPGA FPGA_SYN_1THREAD PITON_FPGA_NO_DMBR MERGE_L1_DCACHE CONFIG_DISABLE_BIST_CLEAR" +set DESIGN_DEFAULT_VERILOG_MACROS "FPGA_SYN_1THREAD PITON_FPGA_NO_DMBR MERGE_L1_DCACHE CONFIG_DISABLE_BIST_CLEAR" set DESIGN_RTL_IMPL_FILES [concat \ ${CHIP_RTL_IMPL_FILES} \ From f10e5d1e719fdf9e6d792c9f43f0423edb6f8ede Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 15:20:48 -0400 Subject: [PATCH 047/144] back to original OLED string. --- piton/tools/src/proto/protosyn,2.5 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 2b6bbf55b..3bc16e7cf 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -624,8 +624,8 @@ def makeDefList(options): else: print_warning("--oled option is ignored for %s" % options.board) elif options.design == "chipset" and (options.board == "genesys2" or options.board == "nexysVideo"): -# disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" - disp_string = "Hello" + disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" +# disp_string = "Hello" defines.append("{OLED_STRING=\\\"%s\\\"}" % disp_string) return defines From 8f84599ce62d39c092f9c0f1faecb88a33ab79d2 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 6 Jun 2024 15:21:26 -0400 Subject: [PATCH 048/144] Genesys2 vadj to 1.8V to match vc707. --- .../chipset/xilinx/genesys2/constraints.xdc | 196 +++++++++--------- 1 file changed, 99 insertions(+), 97 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 6db533c99..46a9e6555 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -38,8 +38,8 @@ set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_ #create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] #create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] # Assuming that io_clk has to be created like chipset_passthru_clk_p (RR 2024/05/21) -create_clock -period 5.000 -name io_clk -waveform {0.000 2.500} [get_ports io_clk] -create_clock -period 5.000 -name core_ref_clk -waveform {0.000 2.500} [get_ports core_ref_clk] +create_clock -period 15.000 -name io_clk -waveform {0.000 7.500} [get_ports io_clk] +create_clock -period 15.000 -name core_ref_clk -waveform {0.000 7.500} [get_ports core_ref_clk] # Constraint RGMII interface create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] @@ -58,8 +58,8 @@ set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*] set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*] set_false_path -to [get_cells -hierarchical *init_calib_complete_f*] -set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] -set_false_path -from [get_clocks net_axi_clk_clk_mmcm] -to [get_clocks chipset_clk_clk_mmcm] +#set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] +#set_false_path -from [get_clocks net_axi_clk_clk_mmcm] -to [get_clocks chipset_clk_clk_mmcm] @@ -76,17 +76,17 @@ set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] set_property PACKAGE_PIN P27 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] set_property PACKAGE_PIN P26 [get_ports {sw[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[5]}] set_property PACKAGE_PIN P19 [get_ports {sw[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[4]}] set_property PACKAGE_PIN N19 [get_ports {sw[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[3]}] set_property PACKAGE_PIN K19 [get_ports {sw[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[2]}] set_property PACKAGE_PIN H24 [get_ports {sw[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[1]}] set_property PACKAGE_PIN G25 [get_ports {sw[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[0]}] set_property PACKAGE_PIN G19 [get_ports {sw[0]}] # Loopback control for UART @@ -145,17 +145,19 @@ set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS18} [get_ports oled_vdd_n] ## Buttons +# powered by VADJ set_property PACKAGE_PIN M20 [get_ports btnl] -set_property IOSTANDARD LVCMOS25 [get_ports btnl] +set_property IOSTANDARD LVCMOS18 [get_ports btnl] set_property PACKAGE_PIN C19 [get_ports btnr] -set_property IOSTANDARD LVCMOS25 [get_ports btnr] +set_property IOSTANDARD LVCMOS18 [get_ports btnr] set_property PACKAGE_PIN M19 [get_ports btnd] -set_property IOSTANDARD LVCMOS25 [get_ports btnd] +set_property IOSTANDARD LVCMOS18 [get_ports btnd] set_property PACKAGE_PIN B19 [get_ports btnu] -set_property IOSTANDARD LVCMOS25 [get_ports btnu] +set_property IOSTANDARD LVCMOS18 [get_ports btnu] +# btnc # piton_prsnt_n for Genesys2 chipset target (RR 2024/05/28) -set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] -set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] +#set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] +#set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] ## Ethernet @@ -199,33 +201,33 @@ set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] #set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_p] #set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_n] #set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_p] -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports core_ref_clk] -set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports io_clk] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS18} [get_ports io_clk] # FMC Signals #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] #set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] #set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] -set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] #set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[0]] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] #set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] #set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] -set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] #set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] #set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] -set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] #set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] #set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] @@ -233,7 +235,7 @@ set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports intf_chip_da #set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] #set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] #set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] #set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] @@ -241,424 +243,424 @@ set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports chip_intf_cr #set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] #set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] -set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS25} [get_ports intf_chip_channel[0]] +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] #set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] #set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] -set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] #set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] #set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] -set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[0]] +set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] #set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] #set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] -set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] #set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] #set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] -set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] #set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] #set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] -set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] #set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] #set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] -set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] #set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] #set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] -set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] #set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] #set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] -set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] #set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] #set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] #set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] #set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] #set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] #set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] -set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] #set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] #set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] -set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[14]] +set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[14]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] #set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] #set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] -set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] #set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] #set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] #set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] #set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] #set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] #set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] #set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] #set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] -set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] #set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] #set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] #set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] #set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] #set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] #set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] #set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] #set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] -set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] #set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] #set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] -set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] #set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] #set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[0]] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] #set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] #set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] #set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] #set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] #set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] #set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] #set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] -set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] #set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] #set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] -set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] #set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] #set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] #set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] #set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] -set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] #set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] #set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] -set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] #set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] #set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] -set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] #set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] #set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] -set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] #set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] #set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] -set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] #set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] #set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] -set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] #set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] #set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] -set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] #set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] #set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] -set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] #set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] #set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] -set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] #set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] #set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] -set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] -#set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] -#set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] -#set_property PULLUP true [get_ports piton_prsnt_n] +set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] +set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] +set_property PULLUP true [get_ports piton_prsnt_n] #set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] #set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] #set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] -set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] #set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] #set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] #set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] #set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] #set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] -set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] #set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] #set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] #set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] #set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] -set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] #set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] #set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] -set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] #set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] #set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] -set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] #set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] #set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] #set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] #set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] -set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] set_property PACKAGE_PIN F13 [get_ports piton_ready_n] -set_property IOSTANDARD LVCMOS25 [get_ports piton_ready_n] +set_property IOSTANDARD LVCMOS18 [get_ports piton_ready_n] set_property PULLUP true [get_ports piton_ready_n] -set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS25} [get_ports chipset_prsnt_n] +set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[7]}] #set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] #set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] -set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] #set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] #set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] -set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] #set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] #set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS25} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] #set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] #set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] #set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] #set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] -set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] #set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] #set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] -set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] #set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] #set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] -set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] #set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] #set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] -set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] #set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] #set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] -set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] #set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] #set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] -set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] #set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] #set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] -set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] #set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] #set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] -set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] #set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] #set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] -set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] #set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] #set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS25} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] #set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] #set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] -set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] #set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[0]] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] #set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] #set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS25} [get_ports chip_intf_channel[0]] +set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] #set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] #set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] -set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS25} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS25} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] #set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] From f737f157c1c7f2890cc7f9e47f4378aedb4026cd Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 10 Jun 2024 09:14:45 -0400 Subject: [PATCH 049/144] Added comments for debugging. --- piton/tools/src/proto/fpga_lib.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index a223f1536..e4663798f 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -196,9 +196,15 @@ def find_design_block(design_block): # Output: div - int - uart divider latch ############################################################################ def calcUARTLatch(design_data, board): + print("design_data[Boards]=", design_data["BOARDS"]) + print("design_data[Boards][board]=", design_data["BOARDS"][board]) + print("design_data[Boards][board][FREQ]=", design_data["BOARDS"][board]["FREQ"]) + print("Calculating (float(design_data[BOARDS][board][FREQ]) * 10**6) / (16 * UART_BAUD_RATE)") + div = (float(design_data["BOARDS"][board]["FREQ"]) * 10**6) / (16 * UART_BAUD_RATE); + print("Result float=", div) div = int(round(div)) - + print("Result int=", div) return div @@ -255,6 +261,8 @@ def getTestList(fname, flog, ustr_files=False): test_list = list() suff = "ustr" if ustr_files else "([s|S|c]|riscv)" + dbg.print_info("suff is: ", suff) + dbg.print_info("Test found:") for line in f: mstr = "([0-9a-zA-Z_-]+\.%s)" % suff m = re.search(mstr, line) From 7d07b27e273a2b9f5c8c24f5bf222d6fb5fa6d5d Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 10 Jun 2024 09:15:27 -0400 Subject: [PATCH 050/144] Chipset frequency changed for genesys2. --- piton/tools/src/proto/block.list | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index cf6c34b4a..ed97be326 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -26,7 +26,7 @@ # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 -chipset chipset genesys2,66.667,1024;piton_board,50,0 +chipset chipset genesys2,64,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 chip chip genesys2,66.667,1024;vc707,64,1024 From 50e28a983ab95f113481a33289f120b82caef8ec Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 11 Jun 2024 15:32:14 -0400 Subject: [PATCH 051/144] Needed if want axi4 mem for genesys2 chipset. --- piton/tools/src/proto/common/rtl_setup.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index aa0c08c61..5828a4fe2 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -776,6 +776,7 @@ set PASSTHRU_PRJ_IP_FILES [list \ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ + "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ From ab07852f89944487caada5194f3d566902cf4d33 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 12 Jun 2024 11:58:16 -0400 Subject: [PATCH 052/144] Added --gen2chipset option. Will be for specific features for the chipset on genesys2 board to interact with polara asic. --- piton/tools/src/proto/protosyn,2.5 | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index e82411db8..c8d4226b9 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -143,10 +143,13 @@ def usage(): print(" Number of jobs to use in Vivado implementation flow", file=sys.stderr) print("\n --postroutephysopt", file=sys.stderr) print(" Use post-route physical optimisation in Vivado implementation flow (can improve timing, not recommended by default)", file=sys.stderr) -# parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) print("\n --vc707chip", file=sys.stderr) print(" Sets POLARA_VC707_CHIP rtl define used to recreate Polara chip on VC707 FPGA (False by default)", file=sys.stderr) print(" Assumes vc707 board is chosen", file=sys.stderr) +# parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) + print("\n --gen2chipset", file=sys.stderr) + print(" Sets POLARA_GEN2_CHIPSET define.", file=sys.stderr) + print(" Assumes genesys2 board is chosen", file=sys.stderr) print("\n -h, --help", file=sys.stderr) print(" Display this help message and exit", file=sys.stderr) print("\n", file=sys.stderr) @@ -499,6 +502,7 @@ def setParserOptions(parser): parser.add_option("--zeroer_off", dest="zeroer_off", action="store_true", default=False) parser.add_option("--postroutephysopt", dest="postroutephysopt", action="store_true", default=False) parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) + parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) return parser @@ -637,9 +641,14 @@ def makeDefList(options): #disp_string = "Hello" defines.append("{OLED_STRING=\\\"%s\\\"}" % disp_string) + # --vc707chip option if options.polara_vc707_chip_flag == True: defines.append("POLARA_VC707_CHIP") + # --gen2chipset option + if options.gen2_chipset == True: + defines.append("POLARA_GEN2_CHIPSET") + return defines def makeMemMapping(st_brd, work_dir, log_dir): From 620d06cf60716cc40c964be981091777508e0a26 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 12 Jun 2024 12:01:01 -0400 Subject: [PATCH 053/144] Support for POLARA_GEN2_CHIPSET define. --- piton/design/chipset/rtl/chipset_impl.v.pyv | 14 ++++++++++++++ piton/tools/src/proto/common/rtl_setup.tcl | 1 + 2 files changed, 15 insertions(+) diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 42ee3eb98..2099b8792 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -62,6 +62,8 @@ // purposes // NEXYS4DDR_BOARD NEXYSVIDEO_BOARD Used to indicate which board this code is // being synthesized for. There are more than just these +// POLARA_GEN2_CHIPSET Uses specific memory controller for the chipset being implemented +// on a genesys2 board for the Polara project. <% import os import sys @@ -902,6 +904,18 @@ credit_to_valrdy noc3_xbar_to_%s( ); `endif // F1_BOARD + `ifdef POLARA_GEN2_CHIPSET + gen2_polara_top gen2_polara_top_i( + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_rdy(buf_mem_noc3_ready) + ); + `endif // POLARA_GEN2_CHIPSET + `else `include "cross_module.tmp.h" diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 5828a4fe2..45bdd995b 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -777,6 +777,7 @@ set PASSTHRU_PRJ_IP_FILES [list \ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ From 29e5a773c2c97e4b11d9f53800fe5ce157efb62e Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 12 Jun 2024 12:01:14 -0400 Subject: [PATCH 054/144] Initial revision. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 piton/design/chipset/mc/rtl/gen2_polara_top.sv diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv new file mode 100644 index 000000000..5b5cf54b0 --- /dev/null +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -0,0 +1,24 @@ +// ------------------------------------------------------------------------------- +// Project: core-v-polara-apu +// File: gen2_polara_top.sv +// Author: Raphael Rowley +// Creation Date: 2024/06/12 +// +// Description: +// Memory controller top level for chipset on the genesys2 to communicate with +// the Polara ASIC. +// +// ------------------------------------------------------------------------------- + +`include "mc_define.h" +`include "noc_axi4_bridge_define.vh" + +module gen2_polara_top( + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , + + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy +); From 5ecbc62ec055de8ed6670121a19ada058564602c Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 12 Jun 2024 15:03:42 -0400 Subject: [PATCH 055/144] Fixed whitespace bug. --- piton/tools/src/proto/common/rtl_setup.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 45bdd995b..b17359664 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -776,8 +776,8 @@ set PASSTHRU_PRJ_IP_FILES [list \ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ - "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv" \ + "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv"\ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ From bd64ab3a12870585f053f352b97effa2236694a1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 12 Jun 2024 15:05:11 -0400 Subject: [PATCH 056/144] Started to add mig_afifo and noc_axi4_bridge. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 125 +++++++++++++++++- 1 file changed, 119 insertions(+), 6 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index 5b5cf54b0..dab4e38c0 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -14,11 +14,124 @@ `include "noc_axi4_bridge_define.vh" module gen2_polara_top( - input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , - input logic mem_flit_in_val , - output logic mem_flit_in_rdy , - output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , - output logic mem_flit_out_val , - input logic mem_flit_out_rdy + input chipset_clk, + + input [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input mem_flit_in_val , + output mem_flit_in_rdy , + + output [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output mem_flit_out_val , + input mem_flit_out_rdy , + + input uart_boot_en ); + +// Signal declarations +wire trans_fifo_val; +wire [`NOC_DATA_WIDTH-1:0] trans_fifo_data; +wire trans_fifo_rdy; + +wire fifo_trans_val; +wire [`NOC_DATA_WIDTH-1:0] fifo_trans_data; +wire fifo_trans_rdy; + +wire ui_clk; +wire noc_axi4_bridge_rst; +wire noc_axi4_bridge_init_done; + +// Behavioral + noc_bidir_afifo mig_afifo ( + .clk_1 (chipset_clk), + .rst_1 ( ), // for mc they do a complicated rst chain, Alveo comes from chipset_rst of chipset top level. Why this discrepency? + + .clk_2 ( ), // ddr ui_clk + .rst_2 ( ), // for mc they do a complicated rst chain, Alveo directly from c0_ddr4_ui_clk_sync_rst + + // CPU --> MIG + .flit_in_val_1 (mem_flit_in_val), + .flit_in_data_1 (mem_flit_in_data), + .flit_in_rdy_1 (mem_flit_in_rdy), + + .flit_out_val_2 (fifo_trans_val), + .flit_out_data_2 (fifo_trans_data), + .flit_out_rdy_2 (fifo_trans_rdy), + + // MIG --> CPU + .flit_in_val_2 (trans_fifo_val), + .flit_in_data_2 (trans_fifo_data), + .flit_in_rdy_2 (trans_fifo_rdyt), + + .flit_out_val_1 (mem_flit_out_val), + .flit_out_data_1 (mem_flit_out_data), + .flit_out_rdy_1 (mem_flit_out_rdy) + ); + + noc_axi4_bridge noc_axi4_bridge ( + .clk (ui_clk), + .rst_n (~noc_axi4_bridge_rst), // mc uses a bit of logic and depends on defines, Alveo just a not from ddr + .uart_boot_en (uart_boot_en), + .phy_init_done (noc_axi4_bridge_init_done), // idem + + .src_bridge_vr_noc2_val (fifo_trans_val), + .src_bridge_vr_noc2_dat (fifo_trans_data), + .src_bridge_vr_noc2_rdy (fifo_trans_rdy), + + .bridge_dst_vr_noc3_val (trans_fifo_val), + .bridge_dst_vr_noc3_dat (trans_fifo_data), + .bridge_dst_vr_noc3_rdy (trans_fifo_rdy), + + .m_axi_awid ( ), + .m_axi_awaddr ( ), + .m_axi_awlen ( ), + .m_axi_awsize ( ), + .m_axi_awburst ( ), + .m_axi_awlock ( ), + .m_axi_awcache ( ), + .m_axi_awprot ( ), + .m_axi_awqos ( ), + .m_axi_awregion ( ), + .m_axi_awuser ( ), + .m_axi_awvalid ( ), + .m_axi_awready ( ), + + .m_axi_wid ( ), + .m_axi_wdata ( ), + .m_axi_wstrb ( ), + .m_axi_wlast ( ), + .m_axi_wuser ( ), + .m_axi_wvalid ( ), + .m_axi_wready ( ), + + .m_axi_bid ( ), + .m_axi_bresp ( ), + .m_axi_buser ( ), + .m_axi_bvalid ( ), + .m_axi_bready ( ), + + .m_axi_arid ( ), + .m_axi_araddr ( ), + .m_axi_arlen ( ), + .m_axi_arsize ( ), + .m_axi_arburst ( ), + .m_axi_arlock ( ), + .m_axi_arcache ( ), + .m_axi_arprot ( ), + .m_axi_arqos ( ), + .m_axi_arregion ( ), + .m_axi_aruser ( ), + .m_axi_arvalid ( ), + .m_axi_arready ( ), + + .m_axi_rid ( ), + .m_axi_rdata ( ), + .m_axi_rresp ( ), + .m_axi_rlast ( ), + .m_axi_ruser ( ), + .m_axi_rvalid ( ), + .m_axi_rready ( ) + + ); + +endmodule From 7f6b2a718e0ae0def1d7c46016113e3c00ab7414 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 13 Jun 2024 14:01:41 -0400 Subject: [PATCH 057/144] Initial revision for adding automatic creation of block design for genesys2 polara chipset. --- piton/tools/src/proto/common/setup.tcl | 6 + piton/tools/src/proto/genesys2/board.tcl | 6 + .../src/proto/genesys2/gen2_polara_fpga.tcl | 301 ++++++++++++++++++ 3 files changed, 313 insertions(+) create mode 100644 piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index f47dc956d..81796d238 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -69,6 +69,12 @@ if { ${BOARD} == "alveou280" } { lappend ALL_BD_FILES "${bd_file}.bd" } } +# Use block design if using --gen2chipset protosyn option +#if { [ info exists ::env(POLARA_GEN2_CHIPSET) ] } { +# foreach bd_file ${DESIGN_BD_FILES} { +# lappend ALL_BD_FILES "${bd_file}.bd" +# } +#} set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] diff --git a/piton/tools/src/proto/genesys2/board.tcl b/piton/tools/src/proto/genesys2/board.tcl index 7ccbede14..afbcfabfd 100644 --- a/piton/tools/src/proto/genesys2/board.tcl +++ b/piton/tools/src/proto/genesys2/board.tcl @@ -32,3 +32,9 @@ set BOARD_PART "" set FPGA_PART "xc7k325tffg900-2" set VIVADO_FLOW_PERF_OPT 0 set BOARD_DEFAULT_VERILOG_MACROS "GENESYS2_BOARD" + + +# Create a block design containing a JTAG-AXI master using the FPGA_PART variable +# It will produce the "gen2_polara_fpga.bd" file + +source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga.tcl diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl new file mode 100644 index 000000000..b45c98cbb --- /dev/null +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl @@ -0,0 +1,301 @@ + +################################################################ +# This is a generated script based on design: gen2_polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source gen2_polara_fpga_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/genesys2/bd_gen2 +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part -part xc7k325tffg900-2 +# create_project project_1 myproj -part xc7k325tffg900-2 + set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name gen2_polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:jtag_axi:1.2\ +xilinx.com:ip:mig_7series:4.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:smartconnect:1.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr3_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ddr3_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {225022502} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $ddr3_axi + + set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] + + set mig_ddr3_sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mig_ddr3_sys_diff_clock ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $mig_ddr3_sys_diff_clock + + + # Create ports + set mig_ddr3_init_calib_complete [ create_bd_port -dir O mig_ddr3_init_calib_complete ] + set mig_ddr3_sys_rst_n [ create_bd_port -dir I -type rst mig_ddr3_sys_rst_n ] + set mig_ddr3_ui_clk [ create_bd_port -dir O -type clk mig_ddr3_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {ddr3_axi} \ + CONFIG.FREQ_HZ {225022502} \ + ] $mig_ddr3_ui_clk + set mig_ddr3_ui_clk_sync_rst [ create_bd_port -dir O -type rst mig_ddr3_ui_clk_sync_rst ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $mig_ddr3_ui_clk_sync_rst + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + set_property -dict [ list \ + CONFIG.M_AXI_DATA_WIDTH {32} \ + ] $jtag_axi_0 + + # Create instance: mig_7series_0, and set properties + set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0 ] + set_property -dict [ list \ + CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ + ] $mig_7series_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $smartconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net sys_diff_clock_1 [get_bd_intf_ports mig_ddr3_sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK] + + # Create port connections + connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] + connect_bd_net -net mig_7series_0_ui_clk [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + From a52e58f0772bfd7e6e9b8a68e5adf3bcc701f074 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 14 Jun 2024 14:50:51 -0400 Subject: [PATCH 058/144] Added bd instance and started connecting it to the rest of the mc unit. Clocks and rst signals are not completed. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 276 +++++++++++++----- 1 file changed, 206 insertions(+), 70 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index dab4e38c0..f73cee987 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -15,38 +15,105 @@ module gen2_polara_top( - input chipset_clk, + input logic chipset_clk, - input [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , - input mem_flit_in_val , - output mem_flit_in_rdy , + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , - output [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , - output mem_flit_out_val , - input mem_flit_out_rdy , + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy , - input uart_boot_en + input logic uart_boot_en ); + // ------------------------------------------------------------------------------- + // Signal declarations + // ------------------------------------------------------------------------------- + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; + + -// Signal declarations -wire trans_fifo_val; -wire [`NOC_DATA_WIDTH-1:0] trans_fifo_data; -wire trans_fifo_rdy; + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; + + logic ui_clk; + logic noc_axi4_bridge_rst; + logic noc_axi4_bridge_init_done; + -wire fifo_trans_val; -wire [`NOC_DATA_WIDTH-1:0] fifo_trans_data; -wire fifo_trans_rdy; + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_arid; + logic [`AXI4_ADDR_WIDTH -1:0] ddr3_axi_araddr; + logic [`AXI4_BURST_WIDTH -1:0] ddr3_axi_arburst; + logic [`AXI4_CACHE_WIDTH -1:0] ddr3_axi_arcache; + logic [`AXI4_LEN_WIDTH -1:0] ddr3_axi_arlen; + logic ddr3_axi_arlock; + logic [`AXI4_PROT_WIDTH -1:0] ddr3_axi_arprot; + logic [`AXI4_QOS_WIDTH -1:0] ddr3_axi_arqos; + logic ddr3_axi_arready; + logic [`AXI4_SIZE_WIDTH -1:0] ddr3_axi_arsize; + logic ddr3_axi_arvalid; + logic [`AXI4_QOS_WIDTH -1:0] ddr3_axi_arqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; // not used + logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; // not used + + + + logic [`AXI4_ADDR_WIDTH -1:0] ddr3_axi_awaddr; + logic [`AXI4_BURST_WIDTH -1:0] ddr3_axi_awburst; + logic [`AXI4_CACHE_WIDTH -1:0] ddr3_axi_awcache; + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_awid; + logic [`AXI4_LEN_WIDTH -1:0] ddr3_axi_awlen; + logic ddr3_axi_awlock; + logic [`AXI4_PROT_WIDTH -1:0] ddr3_axi_awprot; + logic [`AXI4_QOS_WIDTH -1:0] ddr3_axi_awqos; + logic ddr3_axi_awready; + logic [`AXI4_SIZE_WIDTH -1:0] ddr3_axi_awsize; + logic ddr3_axi_awvalid; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_awregion; // not used + logic [`AXI4_USER_WIDTH -1:0] m_axi_awuser; // not used + + + + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_bid; + logic ddr3_axi_bready; + logic [`AXI4_RESP_WIDTH -1:0] ddr3_axi_bresp; + logic ddr3_axi_bvalid; + logic [`AXI4_USER_WIDTH -1:0] m_axi_buser; // not used + -wire ui_clk; -wire noc_axi4_bridge_rst; -wire noc_axi4_bridge_init_done; + logic [`AXI4_DATA_WIDTH -1:0] ddr3_axi_rdata; + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_rid; + logic ddr3_axi_rlast; + logic ddr3_axi_rready; + logic [`AXI4_RESP_WIDTH -1:0] ddr3_axi_rresp; + logic ddr3_axi_rvalid; + logic [`AXI4_USER_WIDTH -1:0] m_axi_ruser; // not used + + + logic [`AXI4_DATA_WIDTH -1:0] ddr3_axi_wdata; + logic ddr3_axi_wlast; + logic ddr3_axi_wready; + logic [`AXI4_STRB_WIDTH -1:0] ddr3_axi_wstrb; + logic ddr3_axi_wvalid; + logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; // not used + logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; // not used -// Behavioral + logic mig_ddr3_ui_clk; + + + // ------------------------------------------------------------------------------- + // Behavioral + // ------------------------------------------------------------------------------- + noc_bidir_afifo mig_afifo ( .clk_1 (chipset_clk), .rst_1 ( ), // for mc they do a complicated rst chain, Alveo comes from chipset_rst of chipset top level. Why this discrepency? - .clk_2 ( ), // ddr ui_clk + .clk_2 (mig_ddr3_ui_clk), // ddr ui_clk .rst_2 ( ), // for mc they do a complicated rst chain, Alveo directly from c0_ddr4_ui_clk_sync_rst // CPU --> MIG @@ -69,7 +136,7 @@ wire noc_axi4_bridge_init_done; ); noc_axi4_bridge noc_axi4_bridge ( - .clk (ui_clk), + .clk (mig_ddr3_ui_clk), .rst_n (~noc_axi4_bridge_rst), // mc uses a bit of logic and depends on defines, Alveo just a not from ddr .uart_boot_en (uart_boot_en), .phy_init_done (noc_axi4_bridge_init_done), // idem @@ -82,56 +149,125 @@ wire noc_axi4_bridge_init_done; .bridge_dst_vr_noc3_dat (trans_fifo_data), .bridge_dst_vr_noc3_rdy (trans_fifo_rdy), - .m_axi_awid ( ), - .m_axi_awaddr ( ), - .m_axi_awlen ( ), - .m_axi_awsize ( ), - .m_axi_awburst ( ), - .m_axi_awlock ( ), - .m_axi_awcache ( ), - .m_axi_awprot ( ), - .m_axi_awqos ( ), - .m_axi_awregion ( ), - .m_axi_awuser ( ), - .m_axi_awvalid ( ), - .m_axi_awready ( ), - - .m_axi_wid ( ), - .m_axi_wdata ( ), - .m_axi_wstrb ( ), - .m_axi_wlast ( ), - .m_axi_wuser ( ), - .m_axi_wvalid ( ), - .m_axi_wready ( ), - - .m_axi_bid ( ), - .m_axi_bresp ( ), - .m_axi_buser ( ), - .m_axi_bvalid ( ), - .m_axi_bready ( ), - - .m_axi_arid ( ), - .m_axi_araddr ( ), - .m_axi_arlen ( ), - .m_axi_arsize ( ), - .m_axi_arburst ( ), - .m_axi_arlock ( ), - .m_axi_arcache ( ), - .m_axi_arprot ( ), - .m_axi_arqos ( ), - .m_axi_arregion ( ), - .m_axi_aruser ( ), - .m_axi_arvalid ( ), - .m_axi_arready ( ), - - .m_axi_rid ( ), - .m_axi_rdata ( ), - .m_axi_rresp ( ), - .m_axi_rlast ( ), - .m_axi_ruser ( ), - .m_axi_rvalid ( ), - .m_axi_rready ( ) + .m_axi_awid (ddr3_axi_awid), + .m_axi_awaddr (ddr3_axi_awaddr), + .m_axi_awlen (ddr3_axi_awlen), + .m_axi_awsize (ddr3_axi_awsize), + .m_axi_awburst (ddr3_axi_awburst), + .m_axi_awlock (ddr3_axi_awlock), + .m_axi_awcache (ddr3_axi_awcache), + .m_axi_awprot (ddr3_axi_awprot), + .m_axi_awqos (ddr3_axi_awqos), + .m_axi_awregion (m_axi_awregion), // not used + .m_axi_awuser (m_axi_awuser), // not used + .m_axi_awvalid (ddr3_axi_awvalid), + .m_axi_awready (ddr3_axi_awready), + + .m_axi_wid (m_axi_wid), // not used + .m_axi_wdata (ddr3_axi_wdata), + .m_axi_wstrb (ddr3_axi_wstrb), + .m_axi_wlast (ddr3_axi_wlast), + .m_axi_wuser (m_axi_wuser), // not used + .m_axi_wvalid (ddr3_axi_wvalid), + .m_axi_wready (ddr3_axi_wready), + + .m_axi_bid (ddr3_axi_bid), + .m_axi_bresp (ddr3_axi_bresp), + .m_axi_buser (m_axi_buser), // not used + .m_axi_bvalid (ddr3_axi_bvalid), + .m_axi_bready (ddr3_axi_bready), + + .m_axi_arid (ddr3_axi_arid), + .m_axi_araddr (ddr3_axi_araddr), + .m_axi_arlen (ddr3_axi_arlen), + .m_axi_arsize (ddr3_axi_arsize), + .m_axi_arburst (ddr3_axi_arburst), + .m_axi_arlock (ddr3_axi_arlock), + .m_axi_arcache (ddr3_axi_arcache), + .m_axi_arprot (ddr3_axi_arprot), + .m_axi_arqos (ddr3_axi_arqos), + .m_axi_arregion (m_axi_arregion), // not used + .m_axi_aruser (m_axi_aruser), // not used + .m_axi_arvalid (ddr3_axi_arvalid), + .m_axi_arready (ddr3_axi_arready), + + .m_axi_rid (ddr3_axi_rid), + .m_axi_rdata (ddr3_axi_rdata), + .m_axi_rresp (ddr3_axi_rresp), + .m_axi_rlast (ddr3_axi_rlast), + .m_axi_ruser (m_axi_ruser), // not used + .m_axi_rvalid (ddr3_axi_rvalid), + .m_axi_rready (ddr3_axi_rready) ); + + gen2_polara_fpga gen2_polara_fpga_i( + // AXI Interface for NOC/Master + .ddr3_axi_araddr(ddr3_axi_araddr), + .ddr3_axi_arburst(ddr3_axi_arburst), + .ddr3_axi_arcache(ddr3_axi_arcache), + .ddr3_axi_arid(ddr3_axi_arid), + .ddr3_axi_arlen(ddr3_axi_arlen), + .ddr3_axi_arlock(ddr3_axi_arlock), + .ddr3_axi_arprot(ddr3_axi_arprot), + .ddr3_axi_arqos(ddr3_axi_arqos), + .ddr3_axi_arready(ddr3_axi_arready), + .ddr3_axi_arsize(ddr3_axi_arsize), + .ddr3_axi_arvalid(ddr3_axi_arvalid), + .ddr3_axi_awaddr(ddr3_axi_awaddr), + .ddr3_axi_awburst(ddr3_axi_awburst), + .ddr3_axi_awcache(ddr3_axi_awcache), + .ddr3_axi_awid(ddr3_axi_awid), + .ddr3_axi_awlen(ddr3_axi_awlen), + .ddr3_axi_awlock(ddr3_axi_awlock), + .ddr3_axi_awprot(ddr3_axi_awprot), + .ddr3_axi_awqos(ddr3_axi_awqos), + .ddr3_axi_awready(ddr3_axi_awready), + .ddr3_axi_awsize(ddr3_axi_awsize), + .ddr3_axi_awvalid(ddr3_axi_awvalid), + .ddr3_axi_bid(ddr3_axi_bid), + .ddr3_axi_bready(ddr3_axi_bready), + .ddr3_axi_bresp(ddr3_axi_bresp), + .ddr3_axi_bvalid(ddr3_axi_bvalid), + .ddr3_axi_rdata(ddr3_axi_rdata), + .ddr3_axi_rid(ddr3_axi_rid), + .ddr3_axi_rlast(ddr3_axi_rlast), + .ddr3_axi_rready(ddr3_axi_rready), + .ddr3_axi_rresp(ddr3_axi_rresp), + .ddr3_axi_rvalid(ddr3_axi_rvalid), + .ddr3_axi_wdata(ddr3_axi_wdata), + .ddr3_axi_wlast(ddr3_axi_wlast), + .ddr3_axi_wready(ddr3_axi_wready), + .ddr3_axi_wstrb(ddr3_axi_wstrb), + .ddr3_axi_wvalid(ddr3_axi_wvalid), + // DDR3 Physical Interface + .ddr3_sdram_addr(ddr3_sdram_addr), + .ddr3_sdram_ba(ddr3_sdram_ba), + .ddr3_sdram_cas_n(ddr3_sdram_cas_n), + .ddr3_sdram_ck_n(ddr3_sdram_ck_n), + .ddr3_sdram_ck_p(ddr3_sdram_ck_p), + .ddr3_sdram_cke(ddr3_sdram_cke), + .ddr3_sdram_cs_n(ddr3_sdram_cs_n), + .ddr3_sdram_dm(ddr3_sdram_dm), + .ddr3_sdram_dq(ddr3_sdram_dq), + .ddr3_sdram_dqs_n(ddr3_sdram_dqs_n), + .ddr3_sdram_dqs_p(ddr3_sdram_dqs_p), + .ddr3_sdram_odt(ddr3_sdram_odt), + .ddr3_sdram_ras_n(ddr3_sdram_ras_n), + .ddr3_sdram_reset_n(ddr3_sdram_reset_n), + .ddr3_sdram_we_n(ddr3_sdram_we_n), + // DDR3 memory ready + .mig_ddr3_init_calib_complete(mig_ddr3_init_calib_complete), + // Input Clock for MIG + // Xilinx recommends an external clock as the input clock (low jitter) + .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), + .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), + // Asynchronous reset for the MIG's sys_rst_n + // also used as reset for the AXI bus (synced with ui_clk) + .mig_ddr3_sys_rst_n(mig_ddr3_sys_rst_n), + // MIG generated ui_clk and synchronized reset + .mig_ddr3_ui_clk(mig_ddr3_ui_clk), + .mig_ddr3_ui_clk_sync_rst(mig_ddr3_ui_clk_sync_rst) + ); endmodule From 00aac526e7ee1689a6736403f5094860cc5772d8 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 14 Jun 2024 14:52:29 -0400 Subject: [PATCH 059/144] Finalized tcl scripts to regenerate block design for memory controller of genesys2 chipset. --- piton/tools/src/proto/genesys2/board.tcl | 3 + .../src/proto/genesys2/gen2_polara_fpga.tcl | 100 ++---------------- 2 files changed, 11 insertions(+), 92 deletions(-) diff --git a/piton/tools/src/proto/genesys2/board.tcl b/piton/tools/src/proto/genesys2/board.tcl index afbcfabfd..78fba9247 100644 --- a/piton/tools/src/proto/genesys2/board.tcl +++ b/piton/tools/src/proto/genesys2/board.tcl @@ -38,3 +38,6 @@ set BOARD_DEFAULT_VERILOG_MACROS "GENESYS2_BOARD" # It will produce the "gen2_polara_fpga.bd" file source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga.tcl + +# Grab the file from where the above tcl script has placed it +set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga/gen2_polara_fpga] diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl index b45c98cbb..56cc30cc5 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl @@ -38,7 +38,7 @@ file delete -force ${tmp_build_dir}/${tmp_prj} set list_projs [get_projects -quiet] if { $list_projs eq "" } { - create_project -force ${tmp_build_dir}/${tmp_prj} -part -part xc7k325tffg900-2 + create_project -force ${tmp_build_dir}/${tmp_prj} -part xc7k325tffg900-2 # create_project project_1 myproj -part xc7k325tffg900-2 set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] } @@ -59,101 +59,15 @@ set nRet 0 set cur_design [current_bd_design -quiet] set list_cells [get_bd_cells -quiet] -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/genesys2 +current_bd_design $design_name common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:jtag_axi:1.2\ -xilinx.com:ip:mig_7series:4.2\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:smartconnect:1.0\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - ################################################################## # DESIGN PROCs ################################################################## - - # Procedure to create entire design; Provide argument to make # procedure reusable. If parentCell is "", will use root. proc create_root_design { parentCell } { @@ -189,11 +103,11 @@ proc create_root_design { parentCell } { # Create interface ports set ddr3_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ddr3_axi ] set_property -dict [ list \ - CONFIG.ADDR_WIDTH {32} \ + CONFIG.ADDR_WIDTH {64} \ CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {32} \ + CONFIG.DATA_WIDTH {512} \ CONFIG.FREQ_HZ {225022502} \ CONFIG.HAS_BRESP {1} \ CONFIG.HAS_BURST {1} \ @@ -204,7 +118,7 @@ proc create_root_design { parentCell } { CONFIG.HAS_REGION {1} \ CONFIG.HAS_RRESP {1} \ CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {0} \ + CONFIG.ID_WIDTH {6} \ CONFIG.MAX_BURST_LENGTH {256} \ CONFIG.NUM_READ_OUTSTANDING {1} \ CONFIG.NUM_READ_THREADS {1} \ @@ -298,4 +212,6 @@ proc create_root_design { parentCell } { create_root_design "" +close_project +file delete -force ${tmp_build_dir}/${tmp_prj} From 51f852f661283ae22b36edce632f29c06f6febc9 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 17 Jun 2024 12:20:58 -0400 Subject: [PATCH 060/144] Fixes so that MIG in gen2 polara block design builds as expected. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 1 - piton/tools/src/proto/genesys2/board.tcl | 2 +- .../src/proto/genesys2/gen2_polara_fpga.tcl | 24 +++++++++---------- piton/tools/src/proto/protosyn,2.5 | 3 +++ 4 files changed, 16 insertions(+), 14 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index f73cee987..7e2949a29 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -56,7 +56,6 @@ module gen2_polara_top( logic ddr3_axi_arready; logic [`AXI4_SIZE_WIDTH -1:0] ddr3_axi_arsize; logic ddr3_axi_arvalid; - logic [`AXI4_QOS_WIDTH -1:0] ddr3_axi_arqos; logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; // not used logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; // not used diff --git a/piton/tools/src/proto/genesys2/board.tcl b/piton/tools/src/proto/genesys2/board.tcl index 78fba9247..180371f5c 100644 --- a/piton/tools/src/proto/genesys2/board.tcl +++ b/piton/tools/src/proto/genesys2/board.tcl @@ -28,7 +28,7 @@ # Not intended to be run standalone # -set BOARD_PART "" +set BOARD_PART "digilentinc.com:genesys2:part0:1.1" set FPGA_PART "xc7k325tffg900-2" set VIVADO_FLOW_PERF_OPT 0 set BOARD_DEFAULT_VERILOG_MACROS "GENESYS2_BOARD" diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl index 56cc30cc5..7d9520c3b 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl @@ -161,10 +161,10 @@ proc create_root_design { parentCell } { ] $jtag_axi_0 # Create instance: mig_7series_0, and set properties - set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0 ] + set mig_7series_0_gen2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0_gen2 ] set_property -dict [ list \ CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ - ] $mig_7series_0 + ] $mig_7series_0_gen2 # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] @@ -180,21 +180,21 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] - connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] - connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] - connect_bd_intf_net -intf_net sys_diff_clock_1 [get_bd_intf_ports mig_ddr3_sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK] + connect_bd_intf_net -intf_net mig_7series_0_gen2_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0_gen2/DDR3] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0_gen2/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net sys_diff_clock_1 [get_bd_intf_ports mig_ddr3_sys_diff_clock] [get_bd_intf_pins mig_7series_0_gen2/SYS_CLK] # Create port connections - connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] - connect_bd_net -net mig_7series_0_ui_clk [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] - connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] + connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0_gen2/init_calib_complete] + connect_bd_net -net mig_7series_0_ui_clk [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0_gen2/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0_gen2/ui_clk_sync_rst] connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] - connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0_gen2/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0_gen2/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] # Create address segments - assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force - assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0_gen2/memmap/memaddr] -force + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0_gen2/memmap/memaddr] -force # Restore current instance diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index c8d4226b9..c55a6046f 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -647,7 +647,10 @@ def makeDefList(options): # --gen2chipset option if options.gen2_chipset == True: + # Set RTL define defines.append("POLARA_GEN2_CHIPSET") + # Set environnment variable + os.environ["POLARA_GEN2_CHIPSET"] = "1" return defines From 50b6ee747704558374e9b4a83147148bca3908ea Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 18 Jun 2024 09:13:04 -0400 Subject: [PATCH 061/144] Completed internal connections. Added I/O ports. Added reset logic. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 112 +++++++++++++++--- 1 file changed, 95 insertions(+), 17 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index 7e2949a29..9e7667d8c 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -15,17 +15,40 @@ module gen2_polara_top( - input logic chipset_clk, + // DDR3 Physical Interface + output logic [`DDR3_ADDR_WIDTH-1:0] ddr3_sdram_addr, + output logic [`DDR3_BA_WIDTH-1:0] ddr3_sdram_ba, + output logic ddr3_sdram_cas_n, + output logic [`DDR3_CK_WIDTH-1:0] ddr3_sdram_ck_n, + output logic [`DDR3_CK_WIDTH-1:0] ddr3_sdram_ck_p, + output logic [`DDR3_CKE_WIDTH-1:0] ddr3_sdram_cke, + output logic [`DDR3_CS_WIDTH-1:0] ddr3_sdram_cs_n, + inout logic [`DDR3_DM_WIDTH-1:0] ddr3_sdram_dm, + inout logic [`DDR3_DQ_WIDTH-1:0] ddr3_sdram_dq, + inout logic [`DDR3_DQS_WIDTH-1:0] ddr3_sdram_dqs_n, + inout logic [`DDR3_DQS_WIDTH-1:0] ddr3_sdram_dqs_p, + output logic [`DDR3_ODT_WIDTH-1:0] ddr3_sdram_odt, + output logic ddr3_sdram_ras_n, + output logic ddr3_sdram_reset_n, + output logic ddr3_sdram_we_n, + + // Clocks and reset + input logic chipset_clk, + input logic mig_ddr3_sys_diff_clock_clk_n, + input logic mig_ddr3_sys_diff_clock_clk_p, + input logic sys_rst_n, - input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , - input logic mem_flit_in_val , - output logic mem_flit_in_rdy , + // NOC + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , - output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , - output logic mem_flit_out_val , - input logic mem_flit_out_rdy , + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy , - input logic uart_boot_en + // UART + input logic uart_boot_en ); // ------------------------------------------------------------------------------- // Signal declarations @@ -102,18 +125,73 @@ module gen2_polara_top( logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; // not used logic mig_ddr3_ui_clk; + + logic ui_clk_sync_rst_r; + logic ui_clk_sync_rst_r_r; + logic [31:0] delay_cnt; + logic core_ref_clk; + logic ui_clk_syn_rst_delayed; + logic ui_clk; + logic afifo_rst_1; + logic afifo_ui_rst_r; + logic afifo_ui_rst_r_r; + logic ui_clk_sync_rst; + logic afifo_rst_2; + // ------------------------------------------------------------------------------- // Behavioral // ------------------------------------------------------------------------------- + + // ------------------------------------------------------------------------------- + // rst logic taken from mc_top.v + // ------------------------------------------------------------------------------- + + // needed for correct rst of async fifo + + always @(posedge core_ref_clk) begin + ui_clk_sync_rst_r <= ui_clk_sync_rst; + ui_clk_sync_rst_r_r <= ui_clk_sync_rst_r; + end + + always @(posedge core_ref_clk) begin + if (~sys_rst_n) + delay_cnt <= 32'h1ff; + else begin + delay_cnt <= (delay_cnt != 0) & ~ui_clk_sync_rst_r_r ? delay_cnt - 1 : delay_cnt; + end + end + + assign core_ref_clk = chipset_clk; + always @(posedge core_ref_clk) begin + if (ui_clk_sync_rst) + ui_clk_syn_rst_delayed <= 1'b1; + else begin + ui_clk_syn_rst_delayed <= delay_cnt != 0; + end + end + + assign afifo_rst_1 = ui_clk_syn_rst_delayed; + + assign ui_clk = mig_ddr3_ui_clk; + always @(posedge ui_clk) begin + afifo_ui_rst_r <= afifo_rst_1; + afifo_ui_rst_r_r <= afifo_ui_rst_r; + end + + assign ui_clk_sync_rst = noc_axi4_bridge_rst; + assign afifo_rst_2 = afifo_ui_rst_r_r | ui_clk_sync_rst; + // ------------------------------------------------------------------------------- + // Instances + // ------------------------------------------------------------------------------- noc_bidir_afifo mig_afifo ( .clk_1 (chipset_clk), - .rst_1 ( ), // for mc they do a complicated rst chain, Alveo comes from chipset_rst of chipset top level. Why this discrepency? + .rst_1 (afifo_rst_1), - .clk_2 (mig_ddr3_ui_clk), // ddr ui_clk - .rst_2 ( ), // for mc they do a complicated rst chain, Alveo directly from c0_ddr4_ui_clk_sync_rst + .clk_2 (mig_ddr3_ui_clk), + .rst_2 (afifo_rst_2), // CPU --> MIG .flit_in_val_1 (mem_flit_in_val), @@ -127,7 +205,7 @@ module gen2_polara_top( // MIG --> CPU .flit_in_val_2 (trans_fifo_val), .flit_in_data_2 (trans_fifo_data), - .flit_in_rdy_2 (trans_fifo_rdyt), + .flit_in_rdy_2 (trans_fifo_rdy), .flit_out_val_1 (mem_flit_out_val), .flit_out_data_1 (mem_flit_out_data), @@ -136,9 +214,9 @@ module gen2_polara_top( noc_axi4_bridge noc_axi4_bridge ( .clk (mig_ddr3_ui_clk), - .rst_n (~noc_axi4_bridge_rst), // mc uses a bit of logic and depends on defines, Alveo just a not from ddr + .rst_n (~noc_axi4_bridge_rst), .uart_boot_en (uart_boot_en), - .phy_init_done (noc_axi4_bridge_init_done), // idem + .phy_init_done (noc_axi4_bridge_init_done), .src_bridge_vr_noc2_val (fifo_trans_val), .src_bridge_vr_noc2_dat (fifo_trans_data), @@ -256,17 +334,17 @@ module gen2_polara_top( .ddr3_sdram_reset_n(ddr3_sdram_reset_n), .ddr3_sdram_we_n(ddr3_sdram_we_n), // DDR3 memory ready - .mig_ddr3_init_calib_complete(mig_ddr3_init_calib_complete), + .mig_ddr3_init_calib_complete(noc_axi4_bridge_init_done), // Input Clock for MIG // Xilinx recommends an external clock as the input clock (low jitter) .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), // Asynchronous reset for the MIG's sys_rst_n // also used as reset for the AXI bus (synced with ui_clk) - .mig_ddr3_sys_rst_n(mig_ddr3_sys_rst_n), + .mig_ddr3_sys_rst_n(sys_rst_n), // MIG generated ui_clk and synchronized reset .mig_ddr3_ui_clk(mig_ddr3_ui_clk), - .mig_ddr3_ui_clk_sync_rst(mig_ddr3_ui_clk_sync_rst) + .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst) ); endmodule From 980df2662e6b97b4538e88551eb67d8e99332625 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 18 Jun 2024 09:14:03 -0400 Subject: [PATCH 062/144] DDR3 of gen2_polara_top connected to I/Os. --- piton/design/chipset/rtl/chipset_impl.v.pyv | 25 ++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 2099b8792..92e20e53e 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -906,13 +906,36 @@ credit_to_valrdy noc3_xbar_to_%s( `ifdef POLARA_GEN2_CHIPSET gen2_polara_top gen2_polara_top_i( + .ddr3_sdram_addr(ddr_addr), + .ddr3_sdram_ba(ddr_ba), + .ddr3_sdram_cas_n(ddr_cas_n), + .ddr3_sdram_ck_n(ddr_ck_n), + .ddr3_sdram_ck_p(ddr_ck_p), + .ddr3_sdram_cke(ddr_cke), + .ddr3_sdram_cs_n(ddr_cs_n), + .ddr3_sdram_dm(ddr_dm), + .ddr3_sdram_dq(ddr_dq), + .ddr3_sdram_dqs_n(ddr_dqs_n), + .ddr3_sdram_dqs_p(ddr_dqs_p), + .ddr3_sdram_odt(ddr_odt), + .ddr3_sdram_ras_n(ddr_ras_n), + .ddr3_sdram_reset_n(ddr_reset_n), + .ddr3_sdram_we_n(ddr_we_n), + + .chipset_clk(), + .mig_ddr3_sys_diff_clock_clk_n(), + .mig_ddr3_sys_diff_clock_clk_p(), + .sys_rst_n(), + .mem_flit_in_data(buf_mem_noc2_data), .mem_flit_in_val(buf_mem_noc2_valid), .mem_flit_in_rdy(mem_buf_noc2_ready), .mem_flit_out_data(mem_buf_noc3_data), .mem_flit_out_val(mem_buf_noc3_valid), - .mem_flit_out_rdy(buf_mem_noc3_ready) + .mem_flit_out_rdy(buf_mem_noc3_ready), + + .uart_boot_en() ); `endif // POLARA_GEN2_CHIPSET From 39ea5bfb0766b14a2462cdcff8f509ffcbe52d33 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 18 Jun 2024 09:15:06 -0400 Subject: [PATCH 063/144] Uncommented inclusion of gen2 chipset BD files. --- piton/tools/src/proto/common/setup.tcl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 81796d238..c2de9f5b5 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -70,11 +70,11 @@ if { ${BOARD} == "alveou280" } { } } # Use block design if using --gen2chipset protosyn option -#if { [ info exists ::env(POLARA_GEN2_CHIPSET) ] } { -# foreach bd_file ${DESIGN_BD_FILES} { -# lappend ALL_BD_FILES "${bd_file}.bd" -# } -#} +if { [ info exists ::env(POLARA_GEN2_CHIPSET) ] } { + foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" + } +} set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] From 5de80667475cef549572220c7b2a7635abb0d0db Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 18 Jun 2024 14:55:46 -0400 Subject: [PATCH 064/144] Added missing I/Os. --- piton/design/chipset/mc/rtl/gen2_polara_top.sv | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index 9e7667d8c..d5327cbcc 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -47,6 +47,10 @@ module gen2_polara_top( output logic mem_flit_out_val , input logic mem_flit_out_rdy , + // Others + output logic init_calib_complete_out, + output logic mem_ui_clk_sync_rst, + // UART input logic uart_boot_en ); @@ -131,19 +135,23 @@ module gen2_polara_top( logic [31:0] delay_cnt; logic core_ref_clk; logic ui_clk_syn_rst_delayed; - logic ui_clk; + logic afifo_rst_1; logic afifo_ui_rst_r; logic afifo_ui_rst_r_r; logic ui_clk_sync_rst; logic afifo_rst_2; - - + + logic init_calib_complete; // ------------------------------------------------------------------------------- // Behavioral // ------------------------------------------------------------------------------- + // from mc_top.v + assign init_calib_complete = noc_axi4_bridge_init_done; + assign init_calib_complete_out = init_calib_complete & ~ui_clk_syn_rst_delayed; + // ------------------------------------------------------------------------------- // rst logic taken from mc_top.v // ------------------------------------------------------------------------------- @@ -173,6 +181,7 @@ module gen2_polara_top( end assign afifo_rst_1 = ui_clk_syn_rst_delayed; + assign mem_ui_clk_sync_rst = ui_clk_syn_rst_delayed; assign ui_clk = mig_ddr3_ui_clk; always @(posedge ui_clk) begin From 8c71ec8b7848e9f623b940a8ca90f5ceced2090f Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 18 Jun 2024 14:57:05 -0400 Subject: [PATCH 065/144] Adding I/Os for POLARA GEN2 CHIPSET. --- piton/design/chipset/rtl/chipset.v | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 9f362320d..ce9327aef 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -82,6 +82,8 @@ // PITON_NOC_POWER_CHIPSET_TEST This indicates to use a completely different // chipset that just sends dummy network packets // into the chip for testing NoC power +// POLARA_GEN2_CHIPSET Uses specific memory controller for the chipset being implemented +// on a genesys2 board for the Polara project. module chipset( @@ -806,8 +808,8 @@ end assign leds[2] = init_calib_complete; assign leds[3] = 1'b0; assign leds[4] = piton_prsnt_n; - assign leds[5] = chipset_rst_n_ff; - assign leds[6] = invalid_access; + assign leds[5] = test_start; + assign leds[6] = chipset_prsnt_n; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART `ifdef PITONSYS_UART_BOOT @@ -1231,6 +1233,11 @@ chipset_impl_noc_power_test chipset_impl ( .noc_power_test_hop_count (noc_power_test_hop_count), `endif + `ifdef POLARA_GEN2_CHIPSET + .mig_ddr3_sys_diff_clock_clk_n(clk_osc_n), + .mig_ddr3_sys_diff_clock_clk_p(clk_osc_p), + `endif + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD @@ -1361,7 +1368,7 @@ chipset_impl_noc_power_test chipset_impl ( `endif //ifndef F1_BOARD `endif // endif PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC - + `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART , @@ -1407,8 +1414,7 @@ chipset_impl_noc_power_test chipset_impl ( `endif // PITON_FPGA_ETHERNETLITE `endif // endif PITONSYS_IOCTRL - - + `ifdef ALVEO_BOARD , // PCIe .pci_express_x16_rxn(pci_express_x16_rxn), From 3e054f596f60d304c59843e88b0255c639708ed2 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 18 Jun 2024 14:57:37 -0400 Subject: [PATCH 066/144] Only use POLARA gen2 top if generating polara gen2 chipset. --- piton/design/chipset/rtl/chipset_impl.v.pyv | 76 +++++++++++---------- 1 file changed, 41 insertions(+), 35 deletions(-) diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 92e20e53e..3b5bafdf6 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -101,6 +101,11 @@ module chipset_impl( output chip_rstn , `endif +`ifdef POLARA_GEN2_CHIPSET + input wire mig_ddr3_sys_diff_clock_clk_n, + input wire mig_ddr3_sys_diff_clock_clk_p, +`endif + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD @@ -805,6 +810,42 @@ credit_to_valrdy noc3_xbar_to_%s( .m_axi_bready(m_axi_bready), .ddr_ready(ddr_ready) ); + `elsif POLARA_GEN2_CHIPSET + gen2_polara_top gen2_polara_top_i( + .ddr3_sdram_addr(ddr_addr), + .ddr3_sdram_ba(ddr_ba), + .ddr3_sdram_cas_n(ddr_cas_n), + .ddr3_sdram_ck_n(ddr_ck_n), + .ddr3_sdram_ck_p(ddr_ck_p), + .ddr3_sdram_cke(ddr_cke), + .ddr3_sdram_cs_n(ddr_cs_n), + .ddr3_sdram_dm(ddr_dm), + .ddr3_sdram_dq(ddr_dq), + .ddr3_sdram_dqs_n(ddr_dqs_n), + .ddr3_sdram_dqs_p(ddr_dqs_p), + .ddr3_sdram_odt(ddr_odt), + .ddr3_sdram_ras_n(ddr_ras_n), + .ddr3_sdram_reset_n(ddr_reset_n), + .ddr3_sdram_we_n(ddr_we_n), + + .chipset_clk(chipset_clk), + .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), + .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), + .sys_rst_n(chipset_rst_n), + + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_rdy(buf_mem_noc3_ready), + + .init_calib_complete_out(init_calib_complete), + .mem_ui_clk_sync_rst(mc_ui_clk_sync_rst), + + .uart_boot_en(uart_boot_en) + ); `elsif ALVEO_BOARD u280_polara_top u280_polara_i ( @@ -904,41 +945,6 @@ credit_to_valrdy noc3_xbar_to_%s( ); `endif // F1_BOARD - `ifdef POLARA_GEN2_CHIPSET - gen2_polara_top gen2_polara_top_i( - .ddr3_sdram_addr(ddr_addr), - .ddr3_sdram_ba(ddr_ba), - .ddr3_sdram_cas_n(ddr_cas_n), - .ddr3_sdram_ck_n(ddr_ck_n), - .ddr3_sdram_ck_p(ddr_ck_p), - .ddr3_sdram_cke(ddr_cke), - .ddr3_sdram_cs_n(ddr_cs_n), - .ddr3_sdram_dm(ddr_dm), - .ddr3_sdram_dq(ddr_dq), - .ddr3_sdram_dqs_n(ddr_dqs_n), - .ddr3_sdram_dqs_p(ddr_dqs_p), - .ddr3_sdram_odt(ddr_odt), - .ddr3_sdram_ras_n(ddr_ras_n), - .ddr3_sdram_reset_n(ddr_reset_n), - .ddr3_sdram_we_n(ddr_we_n), - - .chipset_clk(), - .mig_ddr3_sys_diff_clock_clk_n(), - .mig_ddr3_sys_diff_clock_clk_p(), - .sys_rst_n(), - - .mem_flit_in_data(buf_mem_noc2_data), - .mem_flit_in_val(buf_mem_noc2_valid), - .mem_flit_in_rdy(mem_buf_noc2_ready), - - .mem_flit_out_data(mem_buf_noc3_data), - .mem_flit_out_val(mem_buf_noc3_valid), - .mem_flit_out_rdy(buf_mem_noc3_ready), - - .uart_boot_en() - ); - `endif // POLARA_GEN2_CHIPSET - `else `include "cross_module.tmp.h" From 683373fecd15b0aa165efcc827bd25ad1fa12edd Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 21 Jun 2024 10:05:06 -0400 Subject: [PATCH 067/144] Added support for single ended clock of MIG. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 73 ++++++++++++++++++- piton/design/chipset/rtl/chipset.v | 12 ++- piton/design/chipset/rtl/chipset_impl.v.pyv | 9 +++ piton/tools/src/proto/genesys2/board.tcl | 21 ++++-- piton/tools/src/proto/protosyn,2.5 | 8 +- 5 files changed, 111 insertions(+), 12 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index d5327cbcc..407c1d9d3 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -34,9 +34,14 @@ module gen2_polara_top( // Clocks and reset input logic chipset_clk, + input logic sys_rst_n, +`ifndef POLARA_GEN2_CHIPSETSE input logic mig_ddr3_sys_diff_clock_clk_n, input logic mig_ddr3_sys_diff_clock_clk_p, - input logic sys_rst_n, +`else + input logic mig_ddr3_sys_se_clock_clk, +`endif + // NOC input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , @@ -143,6 +148,7 @@ module gen2_polara_top( logic afifo_rst_2; logic init_calib_complete; + // ------------------------------------------------------------------------------- // Behavioral @@ -286,7 +292,8 @@ module gen2_polara_top( .m_axi_rready (ddr3_axi_rready) ); - + + `ifndef POLARA_GEN2_CHIPSETSE gen2_polara_fpga gen2_polara_fpga_i( // AXI Interface for NOC/Master .ddr3_axi_araddr(ddr3_axi_araddr), @@ -355,5 +362,67 @@ module gen2_polara_top( .mig_ddr3_ui_clk(mig_ddr3_ui_clk), .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst) ); + `else // !`ifndef POLARA_GEN2_CHIPSETSE + gen2_polara_fpga_se_clk gen2_polara_fpga_se_clk_i + (.ddr3_axi_araddr(ddr3_axi_araddr), + .ddr3_axi_arburst(ddr3_axi_arburst), + .ddr3_axi_arcache(ddr3_axi_arcache), + .ddr3_axi_arid(ddr3_axi_arid), + .ddr3_axi_arlen(ddr3_axi_arlen), + .ddr3_axi_arlock(ddr3_axi_arlock), + .ddr3_axi_arprot(ddr3_axi_arprot), + .ddr3_axi_arqos(ddr3_axi_arqos), + .ddr3_axi_arready(ddr3_axi_arready), + .ddr3_axi_arsize(ddr3_axi_arsize), + .ddr3_axi_arvalid(ddr3_axi_arvalid), + .ddr3_axi_awaddr(ddr3_axi_awaddr), + .ddr3_axi_awburst(ddr3_axi_awburst), + .ddr3_axi_awcache(ddr3_axi_awcache), + .ddr3_axi_awid(ddr3_axi_awid), + .ddr3_axi_awlen(ddr3_axi_awlen), + .ddr3_axi_awlock(ddr3_axi_awlock), + .ddr3_axi_awprot(ddr3_axi_awprot), + .ddr3_axi_awqos(ddr3_axi_awqos), + .ddr3_axi_awready(ddr3_axi_awready), + .ddr3_axi_awsize(ddr3_axi_awsize), + .ddr3_axi_awvalid(ddr3_axi_awvalid), + .ddr3_axi_bid(ddr3_axi_bid), + .ddr3_axi_bready(ddr3_axi_bready), + .ddr3_axi_bresp(ddr3_axi_bresp), + .ddr3_axi_bvalid(ddr3_axi_bvalid), + .ddr3_axi_rdata(ddr3_axi_rdata), + .ddr3_axi_rid(ddr3_axi_rid), + .ddr3_axi_rlast(ddr3_axi_rlast), + .ddr3_axi_rready(ddr3_axi_rready), + .ddr3_axi_rresp(ddr3_axi_rresp), + .ddr3_axi_rvalid(ddr3_axi_rvalid), + .ddr3_axi_wdata(ddr3_axi_wdata), + .ddr3_axi_wlast(ddr3_axi_wlast), + .ddr3_axi_wready(ddr3_axi_wready), + .ddr3_axi_wstrb(ddr3_axi_wstrb), + .ddr3_axi_wvalid(ddr3_axi_wvalid), + .ddr3_sdram_addr(ddr3_sdram_addr), + .ddr3_sdram_ba(ddr3_sdram_ba), + .ddr3_sdram_cas_n(ddr3_sdram_cas_n), + .ddr3_sdram_ck_n(ddr3_sdram_ck_n), + .ddr3_sdram_ck_p(ddr3_sdram_ck_p), + .ddr3_sdram_cke(ddr3_sdram_cke), + .ddr3_sdram_cs_n(ddr3_sdram_cs_n), + .ddr3_sdram_dm(ddr3_sdram_dm), + .ddr3_sdram_dq(ddr3_sdram_dq), + .ddr3_sdram_dqs_n(ddr3_sdram_dqs_n), + .ddr3_sdram_dqs_p(ddr3_sdram_dqs_p), + .ddr3_sdram_odt(ddr3_sdram_odt), + .ddr3_sdram_ras_n(ddr3_sdram_ras_n), + .ddr3_sdram_reset_n(ddr3_sdram_reset_n), + .ddr3_sdram_we_n(ddr3_sdram_we_n), + .mig_ddr3_init_calib_complete(mig_ddr3_init_calib_complete), + .mig_ddr3_sys_rst_n(mig_ddr3_sys_rst_n), + .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), + .mig_ddr3_ui_clk(mig_ddr3_ui_clk), + .mig_ddr3_ui_clk_sync_rst(mig_ddr3_ui_clk_sync_rst) + ); + `endif // !`ifndef POLARA_GEN2_CHIPSETSE + endmodule diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index ce9327aef..9376c89c7 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -84,7 +84,7 @@ // into the chip for testing NoC power // POLARA_GEN2_CHIPSET Uses specific memory controller for the chipset being implemented // on a genesys2 board for the Polara project. - +// POLARA_GEN2_CHIPSETSE Uses a single ended clock for the MIG instead of differential. module chipset( @@ -1233,11 +1233,15 @@ chipset_impl_noc_power_test chipset_impl ( .noc_power_test_hop_count (noc_power_test_hop_count), `endif - `ifdef POLARA_GEN2_CHIPSET +`ifdef POLARA_GEN2_CHIPSET + `ifdef POLARA_GEN2_CHIPSETSE + .mig_ddr3_sys_se_clock_clk(mc_clk), + `else // POLARA_GEN2_CHIPSETSE .mig_ddr3_sys_diff_clock_clk_n(clk_osc_n), .mig_ddr3_sys_diff_clock_clk_p(clk_osc_p), - `endif - + `endif // POLARA_GEN2_CHIPSETSE +`endif // POLARA_GEN2_CHIPSET + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 3b5bafdf6..f9250d618 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -64,6 +64,7 @@ // being synthesized for. There are more than just these // POLARA_GEN2_CHIPSET Uses specific memory controller for the chipset being implemented // on a genesys2 board for the Polara project. +// POLARA_GEN2_CHIPSETSE Uses a single ended clock for the MIG instead of a differential clock. <% import os import sys @@ -102,9 +103,13 @@ module chipset_impl( `endif `ifdef POLARA_GEN2_CHIPSET +`ifdef POLARA_GEN2_CHIPSETSE + input wire mig_ddr3_sys_se_clock_clk, +`else input wire mig_ddr3_sys_diff_clock_clk_n, input wire mig_ddr3_sys_diff_clock_clk_p, `endif +`endif `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 @@ -829,8 +834,12 @@ credit_to_valrdy noc3_xbar_to_%s( .ddr3_sdram_we_n(ddr_we_n), .chipset_clk(chipset_clk), + `ifdef POLARA_GEN2_CHIPSETSE + .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), + `else .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), + `endif .sys_rst_n(chipset_rst_n), .mem_flit_in_data(buf_mem_noc2_data), diff --git a/piton/tools/src/proto/genesys2/board.tcl b/piton/tools/src/proto/genesys2/board.tcl index 180371f5c..a69f89002 100644 --- a/piton/tools/src/proto/genesys2/board.tcl +++ b/piton/tools/src/proto/genesys2/board.tcl @@ -33,11 +33,22 @@ set FPGA_PART "xc7k325tffg900-2" set VIVADO_FLOW_PERF_OPT 0 set BOARD_DEFAULT_VERILOG_MACROS "GENESYS2_BOARD" +# Single ended clock (for MIG input clock) has a specific block design +if { [ info exists ::env(POLARA_GEN2_CHIPSETSE) ] } { + # Create a block design containing a JTAG-AXI master using the FPGA_PART variable + # It will produce the "gen2_polara_fpga.bd" file -# Create a block design containing a JTAG-AXI master using the FPGA_PART variable -# It will produce the "gen2_polara_fpga.bd" file + source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga_se_clk.tcl -source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga.tcl + # Grab the file from where the above tcl script has placed it + set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga_se_clk/gen2_polara_fpga_se_clk] +} else { + # Create a block design containing a JTAG-AXI master using the FPGA_PART variable + # It will produce the "gen2_polara_fpga.bd" file -# Grab the file from where the above tcl script has placed it -set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga/gen2_polara_fpga] + source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga.tcl + + # Grab the file from where the above tcl script has placed it + set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga/gen2_polara_fpga] + +} diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index c55a6046f..9c41b5058 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -503,6 +503,7 @@ def setParserOptions(parser): parser.add_option("--postroutephysopt", dest="postroutephysopt", action="store_true", default=False) parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) + parser.add_option("--se", dest="se", action="store_true", default=False) return parser @@ -651,7 +652,12 @@ def makeDefList(options): defines.append("POLARA_GEN2_CHIPSET") # Set environnment variable os.environ["POLARA_GEN2_CHIPSET"] = "1" - + if options.se == True: + # Set RTL define + defines.append("POLARA_GEN2_CHIPSETSE") + # Set environnment variable + os.environ["POLARA_GEN2_CHIPSETSE"] = "1" + return defines def makeMemMapping(st_brd, work_dir, log_dir): From d56d7b3884c0d3ae06340ee71c478e57c981ee52 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 21 Jun 2024 10:07:01 -0400 Subject: [PATCH 068/144] BD script for SE clock of MIG. --- .../genesys2/gen2_polara_fpga_se_clk.tcl | 398 ++++++++++++++++++ 1 file changed, 398 insertions(+) create mode 100644 piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl new file mode 100644 index 000000000..e7702ba12 --- /dev/null +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -0,0 +1,398 @@ + +################################################################ +# This is a generated script based on design: gen2_polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source gen2_polara_fpga_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/genesys2/bd_gen2 +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xc7k325tffg900-2 +# create_project project_1 myproj -part xc7k325tffg900-2 + set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name gen2_polara_fpga_se_clk + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/genesys2 +current_bd_design $design_name + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +################################################################## +# MIG PRJ FILE TCL PROCs +################################################################## + +proc write_mig_file_gen2_polara_fpga_mig_7series_0_0 { str_mig_prj_filepath } { + + file mkdir [ file dirname "$str_mig_prj_filepath" ] + set mig_prj_file [open $str_mig_prj_filepath w+] + + puts $mig_prj_file {} + puts $mig_prj_file {} + puts $mig_prj_file { } + puts $mig_prj_file {} + puts $mig_prj_file { gen2_polara_fpga_mig_7series_0_0} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { OFF} + puts $mig_prj_file { 1024} + puts $mig_prj_file { ON} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { xc7k325t-ffg900/-2} + puts $mig_prj_file { 4.2} + puts $mig_prj_file { No Buffer} + puts $mig_prj_file { Use System Clock} + puts $mig_prj_file { ACTIVE LOW} + puts $mig_prj_file { FALSE} + puts $mig_prj_file { 0} + puts $mig_prj_file { 50 Ohms} + puts $mig_prj_file { 0} + puts $mig_prj_file { } + puts $mig_prj_file { DDR3_SDRAM/Components/MT41J256m16XX-107} + puts $mig_prj_file { 1250} + puts $mig_prj_file { 2.0V} + puts $mig_prj_file { 4:1} + puts $mig_prj_file { 200} + puts $mig_prj_file { 0} + puts $mig_prj_file { 800} + puts $mig_prj_file { 1.000} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 32} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { Normal} + puts $mig_prj_file { 4} + puts $mig_prj_file { FALSE} + puts $mig_prj_file { } + puts $mig_prj_file { 15} + puts $mig_prj_file { 10} + puts $mig_prj_file { 3} + puts $mig_prj_file { 1.5V} + puts $mig_prj_file { 1073741824} + puts $mig_prj_file { BANK_ROW_COLUMN} + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { 8 - Fixed} + puts $mig_prj_file { Sequential} + puts $mig_prj_file { 11} + puts $mig_prj_file { Normal} + puts $mig_prj_file { No} + puts $mig_prj_file { Slow Exit} + puts $mig_prj_file { Enable} + puts $mig_prj_file { RZQ/7} + puts $mig_prj_file { Disable} + puts $mig_prj_file { Enable} + puts $mig_prj_file { RZQ/6} + puts $mig_prj_file { 0} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { Output Buffer Enabled} + puts $mig_prj_file { Full Array} + puts $mig_prj_file { 8} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { Normal} + puts $mig_prj_file { Dynamic ODT off} + puts $mig_prj_file { AXI} + puts $mig_prj_file { } + puts $mig_prj_file { RD_PRI_REG} + puts $mig_prj_file { 30} + puts $mig_prj_file { 256} + puts $mig_prj_file { 3} + puts $mig_prj_file { 0} + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file {} + + close $mig_prj_file +} +# End of write_mig_file_gen2_polara_fpga_mig_7series_0_0() + + + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr3_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ddr3_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $ddr3_axi + + set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] + + + # Create ports + set mig_ddr3_init_calib_complete [ create_bd_port -dir O mig_ddr3_init_calib_complete ] + set mig_ddr3_sys_rst_n [ create_bd_port -dir I -type rst mig_ddr3_sys_rst_n ] + set mig_ddr3_sys_se_clock_clk [ create_bd_port -dir I -type clk mig_ddr3_sys_se_clock_clk ] + set mig_ddr3_ui_clk [ create_bd_port -dir O -type clk mig_ddr3_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {ddr3_axi} \ + CONFIG.FREQ_HZ {200000000} \ + ] $mig_ddr3_ui_clk + set mig_ddr3_ui_clk_sync_rst [ create_bd_port -dir O -type rst mig_ddr3_ui_clk_sync_rst ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $mig_ddr3_ui_clk_sync_rst + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + set_property -dict [ list \ + CONFIG.M_AXI_DATA_WIDTH {32} \ + ] $jtag_axi_0 + + # Create instance: mig_7series_0, and set properties + set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0 ] + + # Generate the PRJ File for MIG + set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ] + set str_mig_file_name mig_b.prj + set str_mig_file_path ${str_mig_folder}/${str_mig_file_name} + + write_mig_file_gen2_polara_fpga_mig_7series_0_0 $str_mig_file_path + + set_property -dict [ list \ + CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ + CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.XML_INPUT_FILE {mig_b.prj} \ + ] $mig_7series_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $smartconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + + # Create port connections + connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] + connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net sys_clk_i_0_1 [get_bd_ports mig_ddr3_sys_se_clock_clk] [get_bd_pins mig_7series_0/sys_clk_i] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + From bffd73c3f9a9c5752149a96f66b1fd3c03789d46 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 21 Jun 2024 14:36:49 -0400 Subject: [PATCH 069/144] Missing connections of ui_clk_sync_rst and init_calib_complete from BD to rest of system. --- piton/design/chipset/mc/rtl/gen2_polara_top.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index 407c1d9d3..aa0defd90 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -416,11 +416,11 @@ module gen2_polara_top( .ddr3_sdram_ras_n(ddr3_sdram_ras_n), .ddr3_sdram_reset_n(ddr3_sdram_reset_n), .ddr3_sdram_we_n(ddr3_sdram_we_n), - .mig_ddr3_init_calib_complete(mig_ddr3_init_calib_complete), - .mig_ddr3_sys_rst_n(mig_ddr3_sys_rst_n), + .mig_ddr3_init_calib_complete(noc_axi4_bridge_init_done), + .mig_ddr3_sys_rst_n(sys_rst_n), .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), .mig_ddr3_ui_clk(mig_ddr3_ui_clk), - .mig_ddr3_ui_clk_sync_rst(mig_ddr3_ui_clk_sync_rst) + .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst) ); `endif // !`ifndef POLARA_GEN2_CHIPSETSE From e6891462abfde680646bbc3a10a44166ab9e5b89 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 21 Jun 2024 15:05:26 -0400 Subject: [PATCH 070/144] Routed chipset_rst_n_ff to leds[3] for debugging. --- piton/design/chipset/rtl/chipset.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 9376c89c7..cac1690cf 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -806,7 +806,7 @@ end assign leds[0] = clk_locked; assign leds[1] = ~piton_ready_n; assign leds[2] = init_calib_complete; - assign leds[3] = 1'b0; + assign leds[3] = chipset_rst_n_ff; assign leds[4] = piton_prsnt_n; assign leds[5] = test_start; assign leds[6] = chipset_prsnt_n; From 22fc6a00556f6b7f0246055b1184ea798aef8918 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 21 Jun 2024 15:07:06 -0400 Subject: [PATCH 071/144] piton_prsnt_n to btnc of the genesys2 to allow control of it. --- piton/design/chipset/xilinx/genesys2/constraints.xdc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 46a9e6555..7b39cc619 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -156,8 +156,8 @@ set_property PACKAGE_PIN B19 [get_ports btnu] set_property IOSTANDARD LVCMOS18 [get_ports btnu] # btnc # piton_prsnt_n for Genesys2 chipset target (RR 2024/05/28) -#set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] -#set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] +set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] +set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] ## Ethernet @@ -477,9 +477,9 @@ set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] -set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] -set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] -set_property PULLUP true [get_ports piton_prsnt_n] +#set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] +#set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] +#set_property PULLUP true [get_ports piton_prsnt_n] #set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] From 21c502fc39cf5273e31b5b1040ca05f8c7b5526f Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 25 Jun 2024 11:00:55 -0400 Subject: [PATCH 072/144] Tcl script to test jtag-axi core validated. --- .../src/proto/genesys2/test_jtag_axi.tcl | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 piton/tools/src/proto/genesys2/test_jtag_axi.tcl diff --git a/piton/tools/src/proto/genesys2/test_jtag_axi.tcl b/piton/tools/src/proto/genesys2/test_jtag_axi.tcl new file mode 100644 index 000000000..f0f47e8ff --- /dev/null +++ b/piton/tools/src/proto/genesys2/test_jtag_axi.tcl @@ -0,0 +1,31 @@ +# #################################################################### +# +# test_jtag_axi.tcl +# +# Author : Raphael Rowley (2024/06) +# +# Description : +# Script to automate testing of JTAG-AXI Xilinx IP on Genesys Chipset +# +# #################################################################### + +# Inspired by: https://www.xilinx.com/video/software/jtag-to-axi-master-core.html + +# Assumptions: +# core is named hw_axi_1 +# DDR3 base address 0x8000_0000 + +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] + +# 2. Create a write transaction (16 word AXI burst write) +create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 80000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write + +# 3. Run the write transaction +run_hw_axi [get_hw_axi_txns write0] + +# 4. Create a read transaction (16 word AXI burst read) +create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 80000000 -len 16 -type read + +# 5. Run the read transaction +run_hw_axi [get_hw_axi_txns read0] From 6cdcb57702eb57e1f62534b5c6d2d8657da460e2 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 28 Jun 2024 14:15:54 -0400 Subject: [PATCH 073/144] Modified DDR3 base address in BD to match what NOC uses. --- piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl index e7702ba12..32743f353 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -376,8 +376,8 @@ proc create_root_design { parentCell } { connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] # Create address segments - assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force - assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force # Restore current instance From 1020deef2dbc9938e6890d8e3db64d9bd7c7cab3 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 2 Jul 2024 09:44:38 -0400 Subject: [PATCH 074/144] prints did not work. --- piton/tools/src/proto/fpga_lib.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index e4663798f..a4f84c3eb 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -261,8 +261,6 @@ def getTestList(fname, flog, ustr_files=False): test_list = list() suff = "ustr" if ustr_files else "([s|S|c]|riscv)" - dbg.print_info("suff is: ", suff) - dbg.print_info("Test found:") for line in f: mstr = "([0-9a-zA-Z_-]+\.%s)" % suff m = re.search(mstr, line) From d12d6e4e5a6660ad9a202f83fa7aac7b456adcee Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 2 Jul 2024 09:45:27 -0400 Subject: [PATCH 075/144] Corrections to reflect actual implementation. --- piton/tools/src/proto/block.list | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index ed97be326..b38eb662f 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -26,10 +26,10 @@ # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 -chipset chipset genesys2,64,1024;piton_board,50,0 +chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 -chip chip genesys2,66.667,1024;vc707,64,1024 +chip chip genesys2,66.667,1024;vc707,66.667,1024 chip_bridge_test_fpga fpga_tests/chip_bridge_test/chip_bridge_test_fpga genesys2,66.667,1024;piton_board,50,0 chip_bridge_test_chip fpga_tests/chip_bridge_test/chip_bridge_test_chip genesys2,66.667,1024;piton_board,50,0 memctrl_test fpga_tests/memio_unit_tests/memctrl_test genesys2,100,1024 From 6c6f5225d4e64e6a748e62a3b5182746d4a22091 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 3 Jul 2024 09:04:43 -0400 Subject: [PATCH 076/144] FMC pins to match Polara daughter card. --- .../chipset/xilinx/genesys2/constraints.xdc | 154 +++++++++--------- 1 file changed, 77 insertions(+), 77 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 7b39cc619..7b67bd135 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -29,7 +29,7 @@ set_property PACKAGE_PIN AD12 [get_ports clk_osc_p] set_property PACKAGE_PIN AD11 [get_ports clk_osc_n] set_property IOSTANDARD LVDS [get_ports clk_osc_n] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_mmcm] +#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_mmcm] # Non-MMCM clock constraints #create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] @@ -201,33 +201,33 @@ set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] #set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_p] #set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_n] #set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_p] -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] -set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS18} [get_ports io_clk] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] +set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports io_clk] # FMC Signals #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] #set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] #set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] -set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] #set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] #set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] #set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] -set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] #set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] #set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] -set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] #set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] #set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] @@ -235,7 +235,7 @@ set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] #set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] #set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] #set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] @@ -243,71 +243,71 @@ set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports chip_intf_cr #set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] #set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] -set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] +set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] #set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] #set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] -set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] #set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] #set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] -set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] #set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] #set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] -set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] #set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] #set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] -set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] #set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] #set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] -set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] #set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] #set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] -set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] #set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] #set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] -set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] #set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] #set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] -set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] #set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] #set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] #set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] #set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] #set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] #set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] -set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] #set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] @@ -318,164 +318,164 @@ set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports chip_intf_da #set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] #set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] -set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] #set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] #set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] #set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] #set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] #set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] #set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] #set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] #set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] -set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] #set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] #set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] #set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] #set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] #set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] #set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] #set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] #set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] -set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] #set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] #set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] -set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] #set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] #set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] #set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] #set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] #set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] #set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] #set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] #set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] #set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] -set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] #set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] #set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] -set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] #set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] #set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] #set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] #set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] -set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] #set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] #set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] -set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] #set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] #set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] -set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] #set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] #set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] -set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] #set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] #set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] -set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] #set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] #set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] -set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] #set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] #set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] -set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] #set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] #set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] -set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] #set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] #set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] -set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] #set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] #set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] -set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] #set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] #set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] @@ -486,61 +486,61 @@ set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] #set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] -set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] #set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] #set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] #set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] #set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] #set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] -set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] #set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] #set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] #set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] #set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] -set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] #set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] #set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] -set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] #set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] #set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] -set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] #set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] #set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] #set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] #set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] -set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] set_property PACKAGE_PIN F13 [get_ports piton_ready_n] set_property IOSTANDARD LVCMOS18 [get_ports piton_ready_n] @@ -551,116 +551,116 @@ set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS18} [get_ports chipset_prsn #set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] #set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] -set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] #set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] #set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] -set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] #set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] #set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] #set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] #set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] #set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] #set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] -set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] #set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] #set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] -set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] #set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] #set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] -set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] #set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] #set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] -set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] #set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] #set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] -set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] #set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] #set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] -set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] #set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] #set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] -set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] #set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] #set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] -set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] #set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] #set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] -set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] #set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] #set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] #set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] #set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] -set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] #set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] #set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] #set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] #set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] #set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] -set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] #set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] @@ -693,7 +693,7 @@ set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports intf_chip_cr #set_false_path -from [get_clocks core_ref_clk_clk_mmcm_1] -to [get_clocks clk_pll_i_1] -set_property LOC ILOGIC_X1Y119 [get_cells {chipset_impl/mc_top/mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det/u_phase_detector}] +#set_property LOC ILOGIC_X1Y119 [get_cells {chipset_impl/mc_top/mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det/u_phase_detector}] set_property PACKAGE_PIN AG2 [get_ports {ddr_dqs_p[2]}] set_property PACKAGE_PIN AH1 [get_ports {ddr_dqs_n[2]}] From c9459a2a5e384a3677c9d5d8a0840c972e42ad1e Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 3 Jul 2024 09:06:09 -0400 Subject: [PATCH 077/144] Fix for MIG with AXI interface for NOC<->AXI address translations. --- piton/design/chipset/include/chipset_define.vh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/piton/design/chipset/include/chipset_define.vh b/piton/design/chipset/include/chipset_define.vh index 026d98494..a9f039827 100644 --- a/piton/design/chipset/include/chipset_define.vh +++ b/piton/design/chipset/include/chipset_define.vh @@ -82,8 +82,13 @@ `define ADDR_TRANS_PHYS_WIDTH_ALIGN 4 `define ADDR_TRANS_SECTION_MULT 4 `elsif GENESYS2_BOARD // 32-bit PHY + `ifdef POLARA_GEN2_CHIPSET + `define ADDR_TRANS_PHYS_WIDTH_ALIGN 6 + `define ADDR_TRANS_SECTION_MULT 2 + `else `define ADDR_TRANS_PHYS_WIDTH_ALIGN 5 `define ADDR_TRANS_SECTION_MULT 2 + `endif `else // 64-bit interface by default `define ADDR_TRANS_PHYS_WIDTH_ALIGN 6 `define ADDR_TRANS_SECTION_MULT 1 From cd0384c555a40cf8e336874972d0c724bc279443 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 3 Jul 2024 10:34:08 -0400 Subject: [PATCH 078/144] Bitstream generation passes for Polara board routing. --- piton/design/chipset/xilinx/genesys2/constraints.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 7b67bd135..2c2b16d2c 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -28,8 +28,8 @@ set_property IOSTANDARD LVDS [get_ports clk_osc_p] set_property PACKAGE_PIN AD12 [get_ports clk_osc_p] set_property PACKAGE_PIN AD11 [get_ports clk_osc_n] set_property IOSTANDARD LVDS [get_ports clk_osc_n] - -#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_mmcm] +# Line needed to avoid placer failure +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_mmcm] # Non-MMCM clock constraints #create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] From b836eb62179693ab00bd95965bde4dffe07d3104 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 3 Jul 2024 14:29:23 -0400 Subject: [PATCH 079/144] Added GPIO bus in block design to control ASIC chip inputs (mostly FLL inputs). --- .../genesys2/gen2_polara_fpga_se_clk.tcl | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl index 32743f353..d8f153d04 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -311,6 +311,8 @@ proc create_root_design { parentCell } { set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] + set polara_gen2chipset_bus [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus ] + # Create ports set mig_ddr3_init_calib_complete [ create_bd_port -dir O mig_ddr3_init_calib_complete ] @@ -326,6 +328,13 @@ proc create_root_design { parentCell } { CONFIG.POLARITY {ACTIVE_HIGH} \ ] $mig_ddr3_ui_clk_sync_rst + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {14} \ + ] $axi_gpio_0 + # Create instance: jtag_axi_0, and set properties set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] set_property -dict [ list \ @@ -356,27 +365,31 @@ proc create_root_design { parentCell } { set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] set_property -dict [ list \ CONFIG.NUM_CLKS {1} \ - CONFIG.NUM_MI {1} \ + CONFIG.NUM_MI {2} \ CONFIG.NUM_SI {2} \ ] $smartconnect_0 # Create interface connections connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus] [get_bd_intf_pins axi_gpio_0/GPIO] connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] # Create port connections connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] - connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] - connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] connect_bd_net -net sys_clk_i_0_1 [get_bd_ports mig_ddr3_sys_se_clock_clk] [get_bd_pins mig_7series_0/sys_clk_i] connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force From 7ec9eff8169ce88241fe2198f082d30a2c84bbb1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 3 Jul 2024 20:43:10 -0400 Subject: [PATCH 080/144] Added support of FLL and other control signals for the Polara ASIC chip. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 39 +++++++++++++++++-- piton/design/chipset/rtl/chipset.v | 26 +++++++++++++ piton/design/chipset/rtl/chipset_impl.v.pyv | 11 ++++++ .../chipset/xilinx/genesys2/constraints.xdc | 16 ++++++++ 4 files changed, 88 insertions(+), 4 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index aa0defd90..a2e7fc28d 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -39,7 +39,20 @@ module gen2_polara_top( input logic mig_ddr3_sys_diff_clock_clk_n, input logic mig_ddr3_sys_diff_clock_clk_p, `else - input logic mig_ddr3_sys_se_clock_clk, + input logic mig_ddr3_sys_se_clock_clk, + + // Polara ASIC Control Signals + output logic chip_async_mux, + output logic chip_clk_en, + output logic chip_clk_mux_sel, + output logic chip_rst_n, + output logic fll_rst_n, + output logic fll_bypass, + output logic fll_clkdiv, + output logic fll_lock, + output logic fll_cfg_req, + output logic fll_opmode, + output logic [3:0] fll_range, `endif @@ -58,6 +71,7 @@ module gen2_polara_top( // UART input logic uart_boot_en + ); // ------------------------------------------------------------------------------- // Signal declarations @@ -148,7 +162,8 @@ module gen2_polara_top( logic afifo_rst_2; logic init_calib_complete; - + + logic [13:0] polara_gen2chipset_bus; // ------------------------------------------------------------------------------- // Behavioral @@ -420,9 +435,25 @@ module gen2_polara_top( .mig_ddr3_sys_rst_n(sys_rst_n), .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), .mig_ddr3_ui_clk(mig_ddr3_ui_clk), - .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst) + .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst), + .polara_gen2chipset_bus_tri_o(polara_gen2chipset_bus) ); - `endif // !`ifndef POLARA_GEN2_CHIPSETSE + + // Route polara_gen2chipset_bus signals + assign chip_async_mux = polara_gen2chipset_bus[1]; + assign chip_clk_en = polara_gen2chipset_bus[2]; + assign chip_clk_mux_sel = polara_gen2chipset_bus[3]; + assign chip_rst_n = polara_gen2chipset_bus[0]; + assign fll_rst_n = polara_gen2chipset_bus[4]; + assign fll_bypass = polara_gen2chipset_bus[5]; + assign fll_clkdiv = polara_gen2chipset_bus[6]; + assign fll_lock = polara_gen2chipset_bus[7]; + assign fll_cfg_req = polara_gen2chipset_bus[8]; + assign fll_opmode = polara_gen2chipset_bus[9]; + assign fll_range[3:0] = polara_gen2chipset_bus[13:10]; + + `endif // !`ifndef POLARA_GEN2_CHIPSETSE + endmodule diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index cac1690cf..622fa5e94 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -373,6 +373,21 @@ module chipset( `endif // endif PITONSYS_IOCTRL +// Polara Board specific I/Os +`ifdef POLARA_GEN2_CHIPSETSE + output wire chip_async_mux, + output wire chip_clk_en, + output wire chip_clk_mux_sel, + output wire chip_rst_n, + output wire fll_rst_n, + output wire fll_bypass, + output wire fll_clkdiv, + output wire fll_lock, + output wire fll_cfg_req, + output wire fll_opmode, + output wire [3:0] fll_range, +`endif + // Piton Board specific I/Os `ifdef PITON_BOARD output [1:0] sma_clk_out_p, @@ -1236,6 +1251,17 @@ chipset_impl_noc_power_test chipset_impl ( `ifdef POLARA_GEN2_CHIPSET `ifdef POLARA_GEN2_CHIPSETSE .mig_ddr3_sys_se_clock_clk(mc_clk), + .chip_async_mux(chip_async_mux), + .chip_clk_en(chip_clk_en), + .chip_clk_mux_sel(chip_clk_mux_sel), + .chip_rst_n(chip_rst_n), + .fll_rst_n(fll_rst_n), + .fll_bypass(fll_bypass), + .fll_clkdiv(fll_clkdiv), + .fll_lock(fll_lock), + .fll_cfg_req(fll_cfg_req), + .fll_opmode(fll_opmode), + .fll_range(fll_range), `else // POLARA_GEN2_CHIPSETSE .mig_ddr3_sys_diff_clock_clk_n(clk_osc_n), .mig_ddr3_sys_diff_clock_clk_p(clk_osc_p), diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index f9250d618..98a7b1f46 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -105,6 +105,17 @@ module chipset_impl( `ifdef POLARA_GEN2_CHIPSET `ifdef POLARA_GEN2_CHIPSETSE input wire mig_ddr3_sys_se_clock_clk, + output wire chip_async_mux, + output wire chip_clk_en, + output wire chip_clk_mux_sel, + output wire chip_rst_n, + output wire fll_rst_n, + output wire fll_bypass, + output wire fll_clkdiv, + output wire fll_lock, + output wire fll_cfg_req, + output wire fll_opmode, + output wire [3:0] fll_range, `else input wire mig_ddr3_sys_diff_clock_clk_n, input wire mig_ddr3_sys_diff_clock_clk_p, diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 2c2b16d2c..8cf797319 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -205,6 +205,22 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports core_ref_clk set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports io_clk] # FMC Signals + +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18} [get_ports chip_async_mux] +set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports chip_clk_en] +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS18} [get_ports chip_clk_mux_sel] +set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS18} [get_ports chip_rst_n] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports fll_rst_n] +set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS18} [get_ports fll_bypass] +set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports fll_clkdiv] +set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports fll_lock] +set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports fll_cfg_req] +set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS18} [get_ports fll_opmode] +set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS18} [get_ports fll_range[3]] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports fll_range[2]] +set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS18} [get_ports fll_range[1]] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports fll_range[0]] + #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] #set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] #set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] From 551a07c7be5d39fa96f8d8a0d7e95c6d87962dbe Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 5 Jul 2024 14:17:09 -0400 Subject: [PATCH 081/144] Restored to initial content, set PITON_CHIP_FPGA. --- piton/design/chip/xilinx/design.tcl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/piton/design/chip/xilinx/design.tcl b/piton/design/chip/xilinx/design.tcl index 9dd74eb55..dec2006a6 100644 --- a/piton/design/chip/xilinx/design.tcl +++ b/piton/design/chip/xilinx/design.tcl @@ -32,8 +32,7 @@ set DESIGN_NAME "chip" set DESIGN_INCLUDE_DIRS "" -# set DESIGN_DEFAULT_VERILOG_MACROS "PITON_CHIP_FPGA FPGA_SYN_1THREAD PITON_FPGA_NO_DMBR MERGE_L1_DCACHE CONFIG_DISABLE_BIST_CLEAR" -set DESIGN_DEFAULT_VERILOG_MACROS "FPGA_SYN_1THREAD PITON_FPGA_NO_DMBR MERGE_L1_DCACHE CONFIG_DISABLE_BIST_CLEAR" +set DESIGN_DEFAULT_VERILOG_MACROS "PITON_CHIP_FPGA FPGA_SYN_1THREAD PITON_FPGA_NO_DMBR MERGE_L1_DCACHE CONFIG_DISABLE_BIST_CLEAR" set DESIGN_RTL_IMPL_FILES [concat \ ${CHIP_RTL_IMPL_FILES} \ From f2021b9690ba526cba992805d3d60cad4eca22c6 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 5 Jul 2024 14:18:32 -0400 Subject: [PATCH 082/144] Constraints for 50MHz vc707chip to interface gen2 chipset for Polara. --- .../design/chip/xilinx/vc707/constraints.xdc | 165 +++++++++--------- 1 file changed, 84 insertions(+), 81 deletions(-) diff --git a/piton/design/chip/xilinx/vc707/constraints.xdc b/piton/design/chip/xilinx/vc707/constraints.xdc index 369ce1601..67110ce34 100644 --- a/piton/design/chip/xilinx/vc707/constraints.xdc +++ b/piton/design/chip/xilinx/vc707/constraints.xdc @@ -39,7 +39,7 @@ #set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] #set_property PACKAGE_PIN AV40 [get_ports sys_rst_n] set_property IOSTANDARD LVCMOS18 [get_ports rst_n] -set_property PACKAGE_PIN AV40 [get_ports rst_n] +set_property PACKAGE_PIN C39 [get_ports rst_n] # False paths #set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] @@ -176,97 +176,100 @@ set_property IOSTANDARD LVCMOS18 [get_ports leds[7]] #create_clock -period 14.9999993 -name io_clk -waveform {0.000 7.49999965} [get_ports io_clk] #create_clock -period 14.9999993 -name core_ref_clk -waveform {0.000 7.49999965} [get_ports core_ref_clk] # 64MHz -create_clock -period 15.625 -name io_clk -waveform {0.000 7.8125} [get_ports io_clk] -create_clock -period 15.625 -name core_ref_clk -waveform {0.000 7.8125} [get_ports core_ref_clk] +#create_clock -period 15.625 -name io_clk -waveform {0.000 7.8125} [get_ports io_clk] +#create_clock -period 15.625 -name core_ref_clk -waveform {0.000 7.8125} [get_ports core_ref_clk] +# 50MHz +create_clock -period 20 -name io_clk -waveform {0.000 10} [get_ports io_clk] +create_clock -period 20 -name core_ref_clk -waveform {0.000 10} [get_ports core_ref_clk] -set_property -dict {PACKAGE_PIN L39 IOSTANDARD LVCMOS18} [get_ports io_clk] -set_property -dict {PACKAGE_PIN L40 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] +set_property -dict {PACKAGE_PIN C38 IOSTANDARD LVCMOS18} [get_ports io_clk] +set_property -dict {PACKAGE_PIN E33 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] #[Place 30-876] Port 'core_ref_clk' is assigned to PACKAGE_PIN 'L40' which can only be used as the N side of a differential clock input. #Please use the following constraint(s) to pass this DRC check: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {core_ref_clk_IBUF}] -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] -set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] +set_property -dict {PACKAGE_PIN L31 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN K32 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] -set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] -set_property -dict {PACKAGE_PIN C33 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] -set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] - -set_property -dict {PACKAGE_PIN B39 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] - -set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] -set_property -dict {PACKAGE_PIN J37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] -set_property -dict {PACKAGE_PIN E37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] -set_property -dict {PACKAGE_PIN H38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] -set_property -dict {PACKAGE_PIN A35 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] -set_property -dict {PACKAGE_PIN H33 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] -set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] -set_property -dict {PACKAGE_PIN E33 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] -set_property -dict {PACKAGE_PIN F36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] -set_property -dict {PACKAGE_PIN B37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] -set_property -dict {PACKAGE_PIN D37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] -set_property -dict {PACKAGE_PIN C35 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] -set_property -dict {PACKAGE_PIN G36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] -set_property -dict {PACKAGE_PIN F34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] -set_property -dict {PACKAGE_PIN G32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] -set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] -set_property -dict {PACKAGE_PIN E34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] -set_property -dict {PACKAGE_PIN E32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] -set_property -dict {PACKAGE_PIN D35 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] -set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] -set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] -set_property -dict {PACKAGE_PIN J36 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] -set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] -set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] -set_property -dict {PACKAGE_PIN H28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] -set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] -set_property -dict {PACKAGE_PIN B34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] -set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] -set_property -dict {PACKAGE_PIN B32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] -set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] -set_property -dict {PACKAGE_PIN C38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] -set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] +set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] + +set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] + +set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN M31 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN B33 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN B32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN A34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN B34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] set_property -dict {PACKAGE_PIN A37 IOSTANDARD LVCMOS18} [get_ports piton_prsnt_n] set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports piton_ready_n] -set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] -set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] -set_property -dict {PACKAGE_PIN F39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] -set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] -set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] -set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] -set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] -set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] -set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] -set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] -set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] -set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] -set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] -set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] -set_property -dict {PACKAGE_PIN L31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] -set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN A36 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN A35 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN F37 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN F36 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN E39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN F39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN V31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN V30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN P31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[14]] -set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] -set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] -set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] -set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] -set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] -set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] -set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] -set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] -set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] -set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] -set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] -set_property -dict {PACKAGE_PIN V30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] - -set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] -set_property -dict {PACKAGE_PIN U31 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] -set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] \ No newline at end of file +set_property -dict {PACKAGE_PIN T31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN U31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN N31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] + +set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] \ No newline at end of file From 8624060c4183a06cf40bdac7a7e244f09953182f Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 8 Jul 2024 09:47:23 -0400 Subject: [PATCH 083/144] No need for chipset_prsnt_n for vc707 polara chip emulation. --- piton/design/chip/rtl/chip.v.pyv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 8db9fcbf2..eb02629e5 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -63,7 +63,7 @@ module chip( // Clock mux select (bypass PLL or not) // Double redundancy with pll_bypass input [1:0] clk_mux_sel, - + // JTAG input jtag_clk, input jtag_rst_l, @@ -84,9 +84,13 @@ module chip( output piton_prsnt_n, output piton_ready_n, + // No need for the vc707 chip that works with the genesys2 chipset (Polara project) +`ifndef POLARA_VC707_CHIP input chipset_prsnt_n, +`endif // endif POLARA_VC707_CHIP output [7:0] leds, + `endif // endif PITON_CHIP_FPGA `ifndef PITON_NO_CHIP_BRIDGE From 4fe1a5ea36cdd0cccffeef3bd4ac4a3f20ffd86b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 8 Jul 2024 09:48:52 -0400 Subject: [PATCH 084/144] block.list for 50MHz vc707 polara chip. --- piton/tools/src/proto/block.list | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index b38eb662f..8bd843e53 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -29,7 +29,7 @@ system . chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 -chip chip genesys2,66.667,1024;vc707,66.667,1024 +chip chip genesys2,66.667,1024;vc707,50,1024 chip_bridge_test_fpga fpga_tests/chip_bridge_test/chip_bridge_test_fpga genesys2,66.667,1024;piton_board,50,0 chip_bridge_test_chip fpga_tests/chip_bridge_test/chip_bridge_test_chip genesys2,66.667,1024;piton_board,50,0 memctrl_test fpga_tests/memio_unit_tests/memctrl_test genesys2,100,1024 From ba5f21cfc442d3ea49bee87d8ae8b71f32e0d99b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 8 Jul 2024 11:44:33 -0400 Subject: [PATCH 085/144] Extra I/Os for the Polara chip. --- piton/design/chipset/rtl/chipset_impl.v.pyv | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 98a7b1f46..25f581fba 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -847,6 +847,17 @@ credit_to_valrdy noc3_xbar_to_%s( .chipset_clk(chipset_clk), `ifdef POLARA_GEN2_CHIPSETSE .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), + .chip_async_mux(chip_async_mux), + .chip_clk_en(chip_clk_en), + .chip_clk_mux_sel(chip_clk_mux_sel), + .chip_rst_n(chip_rst_n), + .fll_rst_n(fll_rst_n), + .fll_bypass(fll_bypass), + .fll_clkdiv(fll_clkdiv), + .fll_lock(fll_lock), + .fll_cfg_req(fll_cfg_req), + .fll_opmode(fll_opmode), + .fll_range(fll_range), `else .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), From 97e1139528087baf287049ab158986745c4a5662 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 8 Jul 2024 11:45:15 -0400 Subject: [PATCH 086/144] block.list chipset on genesys2 to match frequency of vc707 chip for polara project. --- piton/tools/src/proto/block.list | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 8bd843e53..457ebfa5b 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -26,7 +26,7 @@ # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 -chipset chipset genesys2,66.667,1024;piton_board,50,0 +chipset chipset genesys2,50,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 chip chip genesys2,66.667,1024;vc707,50,1024 From 1df021b2dc48056f0454288204ceb9f48cdc77f1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 12 Jul 2024 14:30:49 -0400 Subject: [PATCH 087/144] Comments for clarity --- piton/design/chip/rtl/chip.v.pyv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index eb02629e5..cbaedd680 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -769,7 +769,7 @@ module chip( .rst_n (rst_n), `else // ifndef PITON_CHIP_FPGA .rst_n (rst_n & (~chipset_prsnt_n)), -`endif +`endif // ifndef PITON_CHIP_FPGA .pll_rst_n (pll_rst_n), .pll_rangea (pll_rangea), .clk_mux_sel (clk_mux_sel), From 41faf51dbf1430b2bea2e2a00ddfa0cfcd975a85 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 12 Jul 2024 14:37:19 -0400 Subject: [PATCH 088/144] Corrections to constraints for Polara vc707 chip emulation to match asic pinout. --- piton/design/chip/xilinx/vc707/constraints.xdc | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/piton/design/chip/xilinx/vc707/constraints.xdc b/piton/design/chip/xilinx/vc707/constraints.xdc index 67110ce34..32d67f099 100644 --- a/piton/design/chip/xilinx/vc707/constraints.xdc +++ b/piton/design/chip/xilinx/vc707/constraints.xdc @@ -36,8 +36,6 @@ #set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clk_in1_clk_mmcm] # Reset -#set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] -#set_property PACKAGE_PIN AV40 [get_ports sys_rst_n] set_property IOSTANDARD LVCMOS18 [get_ports rst_n] set_property PACKAGE_PIN C39 [get_ports rst_n] @@ -181,7 +179,8 @@ set_property IOSTANDARD LVCMOS18 [get_ports leds[7]] # 50MHz create_clock -period 20 -name io_clk -waveform {0.000 10} [get_ports io_clk] create_clock -period 20 -name core_ref_clk -waveform {0.000 10} [get_ports core_ref_clk] - +# Needed to pass placement (2024/07/08 RR) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {io_clk_IBUF}] set_property -dict {PACKAGE_PIN C38 IOSTANDARD LVCMOS18} [get_ports io_clk] set_property -dict {PACKAGE_PIN E33 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] @@ -192,11 +191,11 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {core_ref_clk_IBUF}] set_property -dict {PACKAGE_PIN L31 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] set_property -dict {PACKAGE_PIN K32 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] -set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] +#set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] -set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] -set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] +set_property -dict {PACKAGE_PIN L32 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] @@ -272,4 +271,4 @@ set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS18} [get_ports chip_intf_da set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] \ No newline at end of file +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] From ab3e652e8b9266b421e49ef11f159bd2a9b4d576 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 12 Jul 2024 14:45:44 -0400 Subject: [PATCH 089/144] Adding FMC_PRSNT monitoring on LED. --- piton/design/chipset/rtl/chipset.v | 4 +++- piton/design/chipset/xilinx/genesys2/constraints.xdc | 12 ++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 622fa5e94..27ccd06e9 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -386,6 +386,8 @@ module chipset( output wire fll_cfg_req, output wire fll_opmode, output wire [3:0] fll_range, + + input wire FMC_PRSNT, `endif // Piton Board specific I/Os @@ -824,7 +826,7 @@ end assign leds[3] = chipset_rst_n_ff; assign leds[4] = piton_prsnt_n; assign leds[5] = test_start; - assign leds[6] = chipset_prsnt_n; + assign leds[6] = FMC_PRSNT; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART `ifdef PITONSYS_UART_BOOT diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 8cf797319..a09f5bb9f 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -23,6 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# Debug +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports FMC_PRSNT] + # Clock signals set_property IOSTANDARD LVDS [get_ports clk_osc_p] set_property PACKAGE_PIN AD12 [get_ports clk_osc_p] @@ -38,8 +41,13 @@ set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_ #create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] #create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] # Assuming that io_clk has to be created like chipset_passthru_clk_p (RR 2024/05/21) -create_clock -period 15.000 -name io_clk -waveform {0.000 7.500} [get_ports io_clk] -create_clock -period 15.000 -name core_ref_clk -waveform {0.000 7.500} [get_ports core_ref_clk] +# 66.666 MHz +#create_clock -period 15.000 -name io_clk -waveform {0.000 7.500} [get_ports io_clk] +#create_clock -period 15.000 -name core_ref_clk -waveform {0.000 7.500} [get_ports core_ref_clk] +# 50 MHz +create_clock -period 20.000 -name io_clk -waveform {0.000 10.000} [get_ports io_clk] +create_clock -period 20.000 -name core_ref_clk -waveform {0.000 10.000} [get_ports core_ref_clk] + # Constraint RGMII interface create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] From 8a309f275e1a816cebcde076a6ce5139792392a0 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 15 Jul 2024 15:11:20 -0400 Subject: [PATCH 090/144] Corrected direction of fll_lock and fll_clkdiv. --- .../design/chipset/mc/rtl/gen2_polara_top.sv | 37 +++++++++++-------- piton/design/chipset/rtl/chipset.v | 4 +- piton/design/chipset/rtl/chipset_impl.v.pyv | 4 +- .../genesys2/gen2_polara_fpga_se_clk.tcl | 14 +++++-- 4 files changed, 36 insertions(+), 23 deletions(-) diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv index a2e7fc28d..59d34b0fb 100644 --- a/piton/design/chipset/mc/rtl/gen2_polara_top.sv +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -48,8 +48,8 @@ module gen2_polara_top( output logic chip_rst_n, output logic fll_rst_n, output logic fll_bypass, - output logic fll_clkdiv, - output logic fll_lock, + input logic fll_clkdiv, + input logic fll_lock, output logic fll_cfg_req, output logic fll_opmode, output logic [3:0] fll_range, @@ -163,7 +163,8 @@ module gen2_polara_top( logic init_calib_complete; - logic [13:0] polara_gen2chipset_bus; + logic [1:0] polara_gen2chipset_bus_i; + logic [11:0] polara_gen2chipset_bus_o; // ------------------------------------------------------------------------------- // Behavioral @@ -436,21 +437,27 @@ module gen2_polara_top( .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), .mig_ddr3_ui_clk(mig_ddr3_ui_clk), .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst), - .polara_gen2chipset_bus_tri_o(polara_gen2chipset_bus) + .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), + .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o) ); // Route polara_gen2chipset_bus signals - assign chip_async_mux = polara_gen2chipset_bus[1]; - assign chip_clk_en = polara_gen2chipset_bus[2]; - assign chip_clk_mux_sel = polara_gen2chipset_bus[3]; - assign chip_rst_n = polara_gen2chipset_bus[0]; - assign fll_rst_n = polara_gen2chipset_bus[4]; - assign fll_bypass = polara_gen2chipset_bus[5]; - assign fll_clkdiv = polara_gen2chipset_bus[6]; - assign fll_lock = polara_gen2chipset_bus[7]; - assign fll_cfg_req = polara_gen2chipset_bus[8]; - assign fll_opmode = polara_gen2chipset_bus[9]; - assign fll_range[3:0] = polara_gen2chipset_bus[13:10]; + assign chip_rst_n = polara_gen2chipset_bus_o[0]; + assign chip_async_mux = polara_gen2chipset_bus_o[1]; + assign chip_clk_en = polara_gen2chipset_bus_o[2]; + assign chip_clk_mux_sel = polara_gen2chipset_bus_o[3]; + + assign fll_rst_n = polara_gen2chipset_bus_o[4]; + assign fll_bypass = polara_gen2chipset_bus_o[5]; + assign fll_opmode = polara_gen2chipset_bus_o[6]; + assign fll_cfg_req = polara_gen2chipset_bus_o[7]; + + assign fll_range[3:0] = polara_gen2chipset_bus_o[11:8]; + + assign polara_gen2chipset_bus_i[0] = fll_lock; + assign polara_gen2chipset_bus_i[1] = fll_clkdiv; + + `endif // !`ifndef POLARA_GEN2_CHIPSETSE diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 27ccd06e9..1cc03f0c5 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -381,8 +381,8 @@ module chipset( output wire chip_rst_n, output wire fll_rst_n, output wire fll_bypass, - output wire fll_clkdiv, - output wire fll_lock, + input wire fll_clkdiv, + input wire fll_lock, output wire fll_cfg_req, output wire fll_opmode, output wire [3:0] fll_range, diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 25f581fba..a01c300b0 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -111,8 +111,8 @@ module chipset_impl( output wire chip_rst_n, output wire fll_rst_n, output wire fll_bypass, - output wire fll_clkdiv, - output wire fll_lock, + input wire fll_clkdiv, + input wire fll_lock, output wire fll_cfg_req, output wire fll_opmode, output wire [3:0] fll_range, diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl index d8f153d04..d2076bd96 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -43,7 +43,6 @@ if { $list_projs eq "" } { set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] } - # CHANGE DESIGN NAME HERE variable design_name set design_name gen2_polara_fpga_se_clk @@ -311,7 +310,9 @@ proc create_root_design { parentCell } { set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] - set polara_gen2chipset_bus [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus ] + set polara_gen2chipset_bus_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_i ] + + set polara_gen2chipset_bus_o [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_o ] # Create ports @@ -331,8 +332,12 @@ proc create_root_design { parentCell } { # Create instance: axi_gpio_0, and set properties set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_GPIO_WIDTH {14} \ + CONFIG.C_GPIO2_WIDTH {2} \ + CONFIG.C_GPIO_WIDTH {12} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_TRI_DEFAULT {0x00000300} \ ] $axi_gpio_0 # Create instance: jtag_axi_0, and set properties @@ -371,7 +376,8 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] - connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus_o] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports polara_gen2chipset_bus_i] [get_bd_intf_pins axi_gpio_0/GPIO2] connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] From 6018132b3140607b65aaa073388fc80db5985d47 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 18 Jul 2024 16:52:39 -0400 Subject: [PATCH 091/144] Frequency of chipset 50MHz. Needed to regenerate mmcm and uart IPs. --- .../ip_cores/atg_uart_init/atg_uart_init.xci | 461 ++++- .../ip_cores/atg_uart_init/uart_data.coe | 2 +- .../bram_16384x512/bram_16384x512.xci | 138 +- .../ip_cores/bram_256x512/bram_256x512.xci | 138 +- .../ip_cores/uart_16550/uart_16550.xci | 92 +- .../ip_cores/mig_7series_0/mig_7series_0.xci | 1571 ++++++++++++++++- .../ip_cores/sd_cache_bram/sd_cache_bram.xci | 136 +- .../ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci | 162 +- .../ip_cores/sd_data_fifo/sd_data_fifo.xci | 162 +- .../afifo_w64_d128_std/afifo_w64_d128_std.xci | 162 +- .../genesys2/ip_cores/clk_mmcm/clk_mmcm.xci | 326 +++- .../mac_eth_axi_lite/mac_eth_axi_lite.xci | 94 +- .../genesys2/ip_cores/afifo_w64/afifo_w64.xci | 162 +- .../genesys2/ip_cores/afifo_w3/afifo_w3.xci | 162 +- 14 files changed, 3623 insertions(+), 145 deletions(-) diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci index c39a5b875..3a2642bae 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci @@ -7,10 +7,284 @@ atg_uart_init - + 65536 + 100000000 + 0 + 0 + 0.0 + 1 + 1 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + WRITE_ONLY + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 0 0 4 @@ -23,15 +297,16 @@ 1 0 16 - 0x0000000013A00FFF + 0x0000000013A00000 0x0000000013A00FFF 3 0 - 0x0000000013A00FFF - 0x0000000013A00FFF + 0x0000000012A00000 + 0x0000000012A00FFF 3 0 16 + no_mem_file_loaded 0 1 0 @@ -47,10 +322,10 @@ 0x00000400 256 1 - atg_uart_init_addr.mif - atg_uart_init_ctrl.mif - atg_uart_init_data.mif - atg_uart_init_mask.mif + atg_uart_init_addr.mem + atg_uart_init_ctrl.mem + atg_uart_init_data.mem + atg_uart_init_mask.mem "00000000000000000000000000000001" 0 5000 @@ -74,25 +349,30 @@ 32 1 0 - atg_uart_init_default_addrram.mif - atg_uart_init_default_cmdram.mif + atg_uart_init_default_addrram.mem + atg_uart_init_default_cmdram.mem NONE NONE NONE - atg_uart_init_default_prmram.mif - atg_uart_init_default_mstram.mif + atg_uart_init_default_prmram.mem + atg_uart_init_default_mstram.mem + 0 254 0xABCD 8 8 32 1 + 0 1 + Seed_Based 100 Read_Write 16 16 Custom + no_mem_file_loaded + 0 0x5A5A 0x7C9B 16 @@ -197,25 +477,176 @@ 8 1080 kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 12 + 10 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe index 6c8df1dfe..aec4227ff 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe @@ -1,2 +1,2 @@ memory_initialization_radix=16; -memory_initialization_vector=00000080 00000024 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; +memory_initialization_vector=00000080 0000001b 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci index 84904252b..1c4658573 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci @@ -7,9 +7,89 @@ bram_16384x512 - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.0 + 0 14 14 1 @@ -60,6 +140,8 @@ 1 16384 16384 + 1 + 1 512 512 0 @@ -126,6 +208,8 @@ 8kx2 false false + 1 + 1 512 512 false @@ -154,28 +238,64 @@ false Stand_Alone kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 4 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -194,6 +314,16 @@ + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci index 124a0ffde..b1ad2f3a4 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci @@ -7,9 +7,89 @@ bram_256x512 - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.0 + 0 8 8 1 @@ -60,6 +140,8 @@ 1 256 256 + 1 + 1 512 512 0 @@ -126,6 +208,8 @@ 8kx2 false false + 1 + 1 512 512 false @@ -154,28 +238,64 @@ false Stand_Alone kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 4 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -194,6 +314,16 @@ + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci index e9e2c882b..7e59b48d5 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci @@ -9,51 +9,131 @@ uart_16550 + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 25000000 kintex7 0 0 1 - 66667000 + VERSAL_AI_CORE_ES1 + 50000000 1 25000000 25 0 0 16550 - 66667000 - 66.667 + 50000000 + 50 1 1 uart_16550 Custom false kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 13 + 26 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci b/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci index 506fc8d7c..8a128e4f8 100644 --- a/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci +++ b/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci @@ -7,8 +7,1215 @@ mig_7series_0 - + + 0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 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+ 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 32 32 32 @@ -1162,33 +2369,389 @@ Custom mig_a.prj kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 2 + 1 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci index e46abc50c..69c8d2150 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci @@ -7,9 +7,89 @@ sd_cache_bram - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.0 + 0 9 9 1 @@ -60,6 +140,8 @@ 1 512 512 + 1 + 1 64 64 0 @@ -126,6 +208,8 @@ 8kx2 false false + 1 + 1 64 64 false @@ -154,28 +238,64 @@ false Stand_Alone kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 4 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -185,6 +305,14 @@ + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci index 2a58d39f4..48dd33a64 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci @@ -7,13 +7,129 @@ sd_ctrl_fifo - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,28 +501,58 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -421,6 +567,14 @@ + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci index eeae03d3d..7d1474350 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci @@ -7,13 +7,129 @@ sd_data_fifo - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,28 +501,58 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -421,6 +567,14 @@ + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci index 454104a47..17e74af9b 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -7,13 +7,129 @@ afifo_w64_d128_std - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,28 +501,58 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -420,6 +566,14 @@ + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci index 5cb30b834..d6d6373a4 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci @@ -7,13 +7,118 @@ clk_mmcm - + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 MMCM cddcdone cddcreq 0000 - 0080 + 0000 clkfb_in_n clkfb_in clkfb_in_p @@ -24,80 +129,80 @@ clkfb_stopped 50.0 100.0 - 1105 - 0080 - 66.667 - 1042 - 0080 - 200.000 + 0000 + 0000 + 50.00000 + 0000 + 0000 + 200.00000 BUFG 50.0 false - 66.667 + 50.00000 0.000 50.000 - 66.666 + 50 0.000 1 - 1186 + 0000 0000 - 50.000 + 50.00000 BUFG 50.0 false - 200.000 + 200.00000 0.000 50.000 200.000 0.000 1 1 - 10c3 + 0000 0000 - 100.000 + 100.00000 BUFG 50.0 false - 50.000 + 50.00000 0.000 50.000 50.000 0.000 1 1 - 10c3 - 0003 - 100.000 + 0000 + 0000 + 100.00000 BUFG 50.0 false - 100.000 + 100.00000 0.000 50.000 100.000 0.000 1 1 - 130c + 0000 0000 - 25.000 + 25.00000 BUFG 50.0 false - 100.000 + 100.00000 180.000 50.000 100.000 180.000 1 1 - 10c3 - 0080 - 100.000 + 0000 + 0000 + 100.00000 BUFG 50.0 false - 25.000 + 25.00000 0.000 50.000 25.000 @@ -107,7 +212,7 @@ BUFG 50.0 false - 100.000 + 100.00000 0.000 50.000 100.000 @@ -129,17 +234,19 @@ dclk den din - 1041 + 0000 1 - 0.33332999999999996 - 1.3333199999999998 - 0.6666599999999999 - 0.6666599999999999 - 2.6666399999999997 - 0.6666599999999999 + 0.25 + 1.0 + 0.5 + 0.5 + 2.0 + 0.5 dout drdy dwe + 93.000 + 1.000 0 0 0 @@ -149,8 +256,8 @@ 0 0 FDBK_AUTO - 0800 - 9990 + 0000 + 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________200.000____________0.010 @@ -160,9 +267,9 @@ Units_MHz No_Jitter locked - 03e8 - 2001 - 23e9 + 0000 + 0000 + 0000 false false false @@ -172,37 +279,37 @@ false false OPTIMIZED - 3.000 + 5.000 0.000 FALSE - 5.0 + 5.000 10.0 - 9.000 + 20.000 0.500 0.000 FALSE - 3 + 5 0.500 0.000 FALSE - 12 + 20 0.500 0.000 FALSE - 6 + 10 0.500 0.000 FALSE FALSE - 6 + 10 0.500 180.000 FALSE - 24 + 40 0.500 0.000 FALSE - 6 + 10 0.500 0.000 FALSE @@ -213,18 +320,23 @@ 0.010 0.010 FALSE + 64.000 + 2.000 7 + 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - chipset_clk____66.667______0.000______50.0______117.498____105.563 - mc_sys_clk___200.000______0.000______50.0_______94.528____105.563 - sd_sys_clk____50.000______0.000______50.0______124.683____105.563 - chipset_passthru_clk___100.000______0.000______50.0______108.247____105.563 - chipset_passthru_clk_n___100.000____180.000______50.0______108.247____105.563 - net_phy_clk____25.000______0.000______50.0______143.534____105.563 - net_axi_clk___100.000______0.000______50.0______108.247____105.563 + chipset_clk__50.00000______0.000______50.0______129.198_____89.971 + mc_sys_clk__200.00000______0.000______50.0_______98.146_____89.971 + sd_sys_clk__50.00000______0.000______50.0______129.198_____89.971 + chipset_passthru_clk__100.00000______0.000______50.0______112.316_____89.971 + chipset_passthru_clk_n__100.00000____180.000______50.0______112.316_____89.971 + net_phy_clk__25.00000______0.000______50.0______148.629_____89.971 + net_axi_clk__100.00000______0.000______50.0______112.316_____89.971 0 0 + 128.000 + 1.000 WAVEFORM UNKNOWN false @@ -260,7 +372,7 @@ No notes 0.010 power_down - FFFF + 0000 1 clk_in1 MMCM @@ -315,6 +427,8 @@ 0 0 0 + 1440.000 + 600.000 clk_mmcm MMCM false @@ -334,63 +448,63 @@ 100.0 0.010 BUFG - 117.498 + 129.198 false - 105.563 + 89.971 50.000 - 66.666 + 50 0.000 1 true BUFG - 94.528 + 98.146 false - 105.563 + 89.971 50.000 200.000 0.000 1 true BUFG - 124.683 + 129.198 false - 105.563 + 89.971 50.000 50.000 0.000 1 true BUFG - 108.247 + 112.316 false - 105.563 + 89.971 50.000 100.000 0.000 1 true BUFG - 108.247 + 112.316 false - 105.563 + 89.971 50.000 100.000 180.000 1 true BUFG - 143.534 + 148.629 false - 105.563 + 89.971 50.000 25.000 0.000 1 true BUFG - 108.247 + 112.316 false - 105.563 + 89.971 50.000 100.000 0.000 @@ -445,37 +559,37 @@ No_Jitter locked OPTIMIZED - 3.000 + 5.000 0.000 false - 5.0 + 5.000 10.0 - 9.000 + 20.000 0.500 0.000 false - 3 + 5 0.500 0.000 false - 12 + 20 0.500 0.000 false - 6 + 10 0.500 0.000 false false - 6 + 10 0.500 180.000 false - 24 + 40 0.500 0.000 false - 6 + 10 0.500 0.000 false @@ -487,6 +601,7 @@ 0.010 false 7 + false false false WAVEFORM @@ -572,28 +687,48 @@ false false kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 8 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + @@ -618,15 +753,21 @@ + + + + + + @@ -642,6 +783,23 @@ + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci index 8ec9fc732..b4210bd91 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci @@ -9,6 +9,45 @@ mac_eth_axi_lite + 1 + false + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 0 1 kintex7 1 @@ -37,25 +76,74 @@ Custom false kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 9 + 23 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci b/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci index 947f56ca8..d5cfb8351 100644 --- a/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci +++ b/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci @@ -7,13 +7,129 @@ afifo_w64 - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,29 +501,59 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -427,6 +573,14 @@ + + + diff --git a/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci b/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci index 57d7873d8..68a373b0c 100644 --- a/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci +++ b/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci @@ -7,13 +7,129 @@ afifo_w3 - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,29 +501,59 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -427,6 +573,14 @@ + + + From 26436ca57c3c20d3e60a4363936ef470560cccc3 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 18 Jul 2024 16:54:11 -0400 Subject: [PATCH 092/144] modifications to remove piton board specific I/Os when doing polara chipset and updated constraints for Polara board. --- piton/design/chipset/rtl/chipset.v | 27 +++ .../chipset/xilinx/genesys2/constraints.xdc | 225 +++++++++++------- 2 files changed, 168 insertions(+), 84 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 1cc03f0c5..b7e852d0d 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -162,11 +162,13 @@ module chipset( `endif // Piton ready input +`ifndef POLARA_GEN2_CHIPSETSE `ifndef PITON_BOARD input piton_ready_n, input piton_prsnt_n, output chipset_prsnt_n, `endif // PITON_BOARD +`endif // POLARA_GEN2_CHIPSETSE // There are actually 3 options for how to // communicate to the chip: directly without a @@ -728,8 +730,12 @@ begin `else `ifdef PITONSYS_UART_RESET chipset_rst_n = rst_n_rect & clk_locked & (~piton_prsnt_n) & uart_rst_out_n; +`else +`ifdef POLARA_GEN2_CHIPSET + chipset_rst_n = rst_n_rect & clk_locked; `else chipset_rst_n = rst_n_rect & clk_locked & (~piton_prsnt_n); +`endif // POLARA_GEN2_CHIPSET `endif // PITONSYS_UART_RESET `endif // PITON_BOARD @@ -819,6 +825,27 @@ end assign leds[1] = init_calib_complete; assign leds[2] = processor_offchip_noc2_valid; assign leds[3] = offchip_processor_noc3_valid; +`elsif POLARA_GEN2_CHIPSET + assign leds[0] = clk_locked; + assign leds[1] = test_start; + assign leds[2] = init_calib_complete; + assign leds[3] = chipset_rst_n_ff; + assign leds[4] = chipset_rst_n_f; + assign leds[5] = rst_n_rect; + assign leds[6] = rst_n; + `ifdef PITONSYS_IOCTRL + `ifdef PITONSYS_UART + `ifdef PITONSYS_UART_BOOT + assign leds[7] = uart_boot_en; + `else // ifndef PITONSYS_UART_BOOT + assign leds[7] = 1'b0; + `endif // endif PITONSYS_UART_BOOT + `else // ifndef PITONSYS_UART + assign leds[7] = 1'b0; + `endif // endif PITONSYS_UART + `else // ifndef PITONSYS_IOCTRL + assign leds[7] = 1'b0; + `endif // endif PITONSYS_IOCTRL `else // PITON_BOARD assign leds[0] = clk_locked; assign leds[1] = ~piton_ready_n; diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index a09f5bb9f..75e66f91c 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -164,8 +164,8 @@ set_property PACKAGE_PIN B19 [get_ports btnu] set_property IOSTANDARD LVCMOS18 [get_ports btnu] # btnc # piton_prsnt_n for Genesys2 chipset target (RR 2024/05/28) -set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] -set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] +#set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] +#set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] ## Ethernet @@ -224,34 +224,34 @@ set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports fll_clkdiv] set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports fll_lock] set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports fll_cfg_req] set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS18} [get_ports fll_opmode] -set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS18} [get_ports fll_range[3]] -set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports fll_range[2]] -set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS18} [get_ports fll_range[1]] -set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports fll_range[0]] +set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS18} [get_ports {fll_range[3]}] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports {fll_range[2]}] +set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS18} [get_ports {fll_range[1]}] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports {fll_range[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] #set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] #set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] -set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] #set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] #set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] #set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] -set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] #set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] #set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] -set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[12]}] #set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] #set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] @@ -259,7 +259,7 @@ set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] #set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[2]}] #set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] #set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] @@ -267,239 +267,239 @@ set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_cr #set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] #set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] -set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] +set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_channel[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] #set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] #set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] -set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] #set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] #set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] -set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] #set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] #set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] -set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] #set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] #set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] -set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] #set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] #set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] -set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] #set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] #set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] -set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] #set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] #set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] #set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] #set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] -set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] #set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] #set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] -set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] #set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] #set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] #set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] #set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] -set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] #set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] #set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] -set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[14]] +set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] #set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] #set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] -set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] #set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] #set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] #set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] #set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] -set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] #set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] #set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] -set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] #set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] #set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] -set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] #set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] #set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] #set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] #set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] -set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] #set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] #set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] #set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] #set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] #set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] #set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] -set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] #set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] #set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] #set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] #set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] #set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] #set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] #set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] #set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] #set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] -set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] #set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] #set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] -set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] #set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] #set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] -set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] #set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] #set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] -set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] #set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] #set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] -set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] #set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] #set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] -set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] #set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] #set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] -set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] #set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] #set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] -set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] #set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] #set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] -set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] #set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] #set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] -set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] #set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] #set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] #set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] #set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] -set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] #set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] #set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] -set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[22]}] #set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] #set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] @@ -510,181 +510,181 @@ set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] #set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] -set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] #set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] #set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] #set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] -set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_channel[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] #set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] #set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] -set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] #set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] #set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] #set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] #set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] -set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] #set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] #set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] -set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] #set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] #set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] -set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] #set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] #set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] -set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] #set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] #set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] -set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[27]}] -set_property PACKAGE_PIN F13 [get_ports piton_ready_n] -set_property IOSTANDARD LVCMOS18 [get_ports piton_ready_n] -set_property PULLUP true [get_ports piton_ready_n] -set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] +#set_property PACKAGE_PIN F13 [get_ports piton_ready_n] +#set_property IOSTANDARD LVCMOS18 [get_ports piton_ready_n] +#set_property PULLUP true [get_ports piton_ready_n] +#set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[7]}] #set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] #set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] -set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] #set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] #set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] -set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] #set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] #set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] -set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] #set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] #set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] #set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] #set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] -set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] #set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] #set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] #set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] #set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] #set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] #set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] #set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] #set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] -set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] #set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] #set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] -set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] #set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] #set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] #set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] #set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] #set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] #set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] #set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] #set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] #set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] #set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] #set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] #set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] #set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] #set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] #set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] -set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[2]}] #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] #set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] @@ -751,3 +751,60 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] #set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] #set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] #set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] + + + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 1 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {chipset_impl/gen2_polara_top_i/ui_clk_syn_rst_delayed_reg_0[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 2 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {chipset_impl/uart_top/writer_str_sel[0]} {chipset_impl/uart_top/writer_str_sel[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list chipset_impl/uart_top/atg_init_done]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 1 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list chipset_impl/init_calib_complete_ff]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/uart_top/mux_sel_reg[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {chipset_impl/uart_top/mux_sel_reg[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/test_bad_end]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/test_good_end]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/uart_tx]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list uart_tx_OBUF]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets clk] From 0aee3aa5c91cd7aefe548f47af3aee8f7fe46158 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 18 Jul 2024 16:55:09 -0400 Subject: [PATCH 093/144] New base address. --- piton/tools/src/proto/genesys2/test_jtag_axi.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/piton/tools/src/proto/genesys2/test_jtag_axi.tcl b/piton/tools/src/proto/genesys2/test_jtag_axi.tcl index f0f47e8ff..fd393d734 100644 --- a/piton/tools/src/proto/genesys2/test_jtag_axi.tcl +++ b/piton/tools/src/proto/genesys2/test_jtag_axi.tcl @@ -13,19 +13,19 @@ # Assumptions: # core is named hw_axi_1 -# DDR3 base address 0x8000_0000 +# DDR3 base address 0x0000_0000 # 1. Reset the core reset_hw_axi [get_hw_axis hw_axi_1] # 2. Create a write transaction (16 word AXI burst write) -create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 80000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write +create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 00000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write # 3. Run the write transaction run_hw_axi [get_hw_axi_txns write0] # 4. Create a read transaction (16 word AXI burst read) -create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 80000000 -len 16 -type read +create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 00000000 -len 16 -type read # 5. Run the read transaction run_hw_axi [get_hw_axi_txns read0] From fc3a7067549873ff70b319dbc0820556cd529cf0 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 26 Jul 2024 13:39:16 -0400 Subject: [PATCH 094/144] Initial revision (jtag_axi_commands.tcl used for Polara ASIC testing). --- .../src/proto/genesys2/jtag_axi_commands.tcl | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 piton/tools/src/proto/genesys2/jtag_axi_commands.tcl diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl new file mode 100644 index 000000000..fb62cc516 --- /dev/null +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -0,0 +1,53 @@ +# #################################################################### +# +# test_jtag_axi.tcl +# +# Author : Raphael Rowley (2024/07) +# +# Description : +# Useful commands for JTAG-AXI Xilinx IP on Genesys Chipset +# +# #################################################################### + +# Inspired by: https://www.xilinx.com/video/software/jtag-to-axi-master-core.html + +# Assumptions: +# core is named hw_axi_1 +# DDR3 base address 0x0000_0000 +# GPIO base address 0x4000_0000 + +# GPIO mapping +# 0 (LSB): chip_rst_n +# 1: chip_async_mux +# 2: chip_clk_en +# 3: chip_clk_mux_sel +# 4: fll_rst_n +# 5: fll_bypass +# 6: fll_opmode +# 7: fll_cfg_req +# 11-8: fll_range[3:0] + +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] + +# 2. Create a write transaction (16 word AXI burst write) +create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 00000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write + +# 3. Run the write transaction +run_hw_axi [get_hw_axi_txns write0] + +# 4. Create a read transaction (16 word AXI burst read) +create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 00000000 -len 16 -type read + +# 5. Run the read transaction +run_hw_axi [get_hw_axi_txns read0] + +# 6. Assert chip reset +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] + +# 7. Deassert chip reset +create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rstoff] From 12e5df1dd5f1d9e474bc2054bae70b713f9cb287 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 26 Jul 2024 16:12:46 -0400 Subject: [PATCH 095/144] Added comments for clarity. --- .../src/proto/genesys2/jtag_axi_commands.tcl | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl index fb62cc516..c94577e72 100644 --- a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -10,13 +10,15 @@ # #################################################################### # Inspired by: https://www.xilinx.com/video/software/jtag-to-axi-master-core.html +# AXI GPIO documentation: https://docs.amd.com/v/u/en-US/pg144-axi-gpio # Assumptions: # core is named hw_axi_1 # DDR3 base address 0x0000_0000 # GPIO base address 0x4000_0000 -# GPIO mapping +# Channel 1 GPIO mapping (outputs) +# Channel 1 AXI GPIO Data Register Address Space Offset: 0x0000 # 0 (LSB): chip_rst_n # 1: chip_async_mux # 2: chip_clk_en @@ -27,9 +29,20 @@ # 7: fll_cfg_req # 11-8: fll_range[3:0] +# Channel 2 GPIO mapping (inputs) +# Channel 2 AXI GPIO Data Register Address Space Offset: 0x0008 +# 0: fll_lock +# 1: fll_clkdiv + +# #################################################################### +# Init +# #################################################################### # 1. Reset the core reset_hw_axi [get_hw_axis hw_axi_1] +# #################################################################### +# Genesys 2 Memory Test +# #################################################################### # 2. Create a write transaction (16 word AXI burst write) create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 00000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write @@ -42,6 +55,9 @@ create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 00000000 -len 16 # 5. Run the read transaction run_hw_axi [get_hw_axi_txns read0] +# #################################################################### +# VC707 chip emulation useful commands +# #################################################################### # 6. Assert chip reset create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write # Run it @@ -51,3 +67,9 @@ run_hw_axi [get_hw_axi_txns rston] create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write # Run it run_hw_axi [get_hw_axi_txns rstoff] + +# #################################################################### +# Polara ASIC useful commands +# #################################################################### + + From 51e55365a3c3d2b7361178fa7ed128d16607abb8 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 30 Jul 2024 08:16:56 -0400 Subject: [PATCH 096/144] Adding dbg0 signal for genesys2 chipset. --- piton/design/chipset/rtl/chipset.v | 14 ++++++++------ .../design/chipset/xilinx/genesys2/constraints.xdc | 2 +- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index b7e852d0d..ec4f9c484 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -389,7 +389,8 @@ module chipset( output wire fll_opmode, output wire [3:0] fll_range, - input wire FMC_PRSNT, + output wire dbg0, + `endif // Piton Board specific I/Os @@ -826,11 +827,12 @@ end assign leds[2] = processor_offchip_noc2_valid; assign leds[3] = offchip_processor_noc3_valid; `elsif POLARA_GEN2_CHIPSET + assign dbg0 = fll_clkdiv; assign leds[0] = clk_locked; - assign leds[1] = test_start; - assign leds[2] = init_calib_complete; - assign leds[3] = chipset_rst_n_ff; - assign leds[4] = chipset_rst_n_f; + assign leds[1] = fll_lock; + assign leds[2] = test_start; + assign leds[3] = init_calib_complete; + assign leds[4] = chipset_rst_n_ff; assign leds[5] = rst_n_rect; assign leds[6] = rst_n; `ifdef PITONSYS_IOCTRL @@ -853,7 +855,7 @@ end assign leds[3] = chipset_rst_n_ff; assign leds[4] = piton_prsnt_n; assign leds[5] = test_start; - assign leds[6] = FMC_PRSNT; + assign leds[6] = test_start; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART `ifdef PITONSYS_UART_BOOT diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 75e66f91c..0603be0c4 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -24,7 +24,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # Debug -set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports FMC_PRSNT] +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports dbg0] # Clock signals set_property IOSTANDARD LVDS [get_ports clk_osc_p] From 0bcb99464d479e55a1ac39ec1e5f6b3fa2d01435 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 30 Jul 2024 08:43:31 -0400 Subject: [PATCH 097/144] Added FLL test commands. --- .../src/proto/genesys2/jtag_axi_commands.tcl | 86 ++++++++++++++++++- 1 file changed, 83 insertions(+), 3 deletions(-) diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl index c94577e72..098645a01 100644 --- a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -58,12 +58,12 @@ run_hw_axi [get_hw_axi_txns read0] # #################################################################### # VC707 chip emulation useful commands # #################################################################### -# 6. Assert chip reset +# 6. Assert chip reset_n create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write # Run it run_hw_axi [get_hw_axi_txns rston] -# 7. Deassert chip reset +# 7. Deassert chip reset_n create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write # Run it run_hw_axi [get_hw_axi_txns rstoff] @@ -72,4 +72,84 @@ run_hw_axi [get_hw_axi_txns rstoff] # Polara ASIC useful commands # #################################################################### - +# ------------------------------------------ +# FLL Tests (chip stays in reset) +# ------------------------------------------ +# Test bypass +# ------------------------------------------ +# 1. Set bypass = 1, opmode = 1, fll_rst_n = 1 +create_hw_axi_txn -force bypassrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000070} -len 1 -type write +run_hw_axi [get_hw_axi_txns bypassrstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force bypasscfg [get_hw_axis hw_axi_1] -address 40000000 -data {000000F0} -len 1 -type write +run_hw_axi [get_hw_axi_txns bypasscfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns bypassrstoff] +# 4. Reset everything +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^0 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0000 +create_hw_axi_txn -force oprstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000050} -len 1 -type write +run_hw_axi [get_hw_axi_txns oprstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force opcfg [get_hw_axis hw_axi_1] -address 40000000 -data {000000D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns opcfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns oprstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^1 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0001 +create_hw_axi_txn -force op1rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000150} -len 1 -type write +run_hw_axi [get_hw_axi_txns op1rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op1cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000001D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op1cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op1rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^2 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0010 +create_hw_axi_txn -force op2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000250} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op2cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000002D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op2rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^4 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0100 +create_hw_axi_txn -force op4rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000450} -len 1 -type write +run_hw_axi [get_hw_axi_txns op4rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op4cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000004D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op4cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op4rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^8 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 1000 +create_hw_axi_txn -force op8rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000850} -len 1 -type write +run_hw_axi [get_hw_axi_txns op8rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op8cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000008D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op8cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op8rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] From 0cd394a360e01be937d62dd0e8b8d0154f43f717 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 31 Jul 2024 16:48:01 -0400 Subject: [PATCH 098/144] Added debug signals. --- piton/design/chipset/rtl/chipset.v | 36 +++++++++++- .../chipset/xilinx/genesys2/constraints.xdc | 56 ++++++++++--------- 2 files changed, 64 insertions(+), 28 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index ec4f9c484..aaef2f54c 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -390,6 +390,21 @@ module chipset( output wire [3:0] fll_range, output wire dbg0, + output wire dbg1, + output wire dbg2, + output wire dbg3, + output wire dbg4, + output wire dbg5, + output wire dbg6, + output wire dbg7, + output wire dbg8, + output wire dbg9, + output wire dbg10, + output wire dbg11, + output wire dbg12, + output wire dbg13, + output wire dbg14, + output wire dbg15, `endif @@ -523,6 +538,7 @@ module chipset( `ifdef PITON_CHIPSET_CLKS_GEN wire chipset_clk; wire mc_clk; + wire io_clk_wire; `endif // endif PITON_CHIPSET_CLKS_GEN `ifdef PITON_BOARD @@ -828,6 +844,22 @@ end assign leds[3] = offchip_processor_noc3_valid; `elsif POLARA_GEN2_CHIPSET assign dbg0 = fll_clkdiv; + assign dbg1 = chipset_clk; + assign dbg2 = chipset_clk; + assign dbg3 = intf_chip_credit_back[0]; + assign dbg4 = intf_chip_credit_back[1]; + assign dbg5 = intf_chip_credit_back[2]; + assign dbg6 = chip_intf_channel[0]; + assign dbg7 = chip_intf_channel[1]; + assign dbg8 = intf_chip_channel[0]; + assign dbg9 = intf_chip_channel[1]; + assign dbg10 = chip_intf_credit_back[0]; + assign dbg11 = chip_intf_credit_back[1]; + assign dbg12 = chip_intf_credit_back[2]; + assign dbg13 = chip_intf_data[0]; + assign dbg14 = chip_intf_data[1]; + assign dbg15 = chip_intf_data[2]; + assign leds[0] = clk_locked; assign leds[1] = fll_lock; assign leds[2] = test_start; @@ -910,10 +942,10 @@ end .reset(1'b0), .locked(clk_locked), - + // Main chipset clock .chipset_clk(chipset_clk) - + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 // Memory controller clock diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 0603be0c4..cb589450e 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -25,6 +25,21 @@ # Debug set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports dbg0] +set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports dbg1] +set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports dbg2] +set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports dbg3] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports dbg4] +set_property -dict {PACKAGE_PIN M23 IOSTANDARD LVCMOS18} [get_ports dbg5] +set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS18} [get_ports dbg6] +set_property -dict {PACKAGE_PIN J28 IOSTANDARD LVCMOS18} [get_ports dbg7] +set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports dbg8] +set_property -dict {PACKAGE_PIN L27 IOSTANDARD LVCMOS18} [get_ports dbg9] +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18} [get_ports dbg10] +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18} [get_ports dbg11] +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports dbg12] +set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS18} [get_ports dbg13] +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS18} [get_ports dbg14] +set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS18} [get_ports dbg15] # Clock signals set_property IOSTANDARD LVDS [get_ports clk_osc_p] @@ -754,6 +769,7 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] @@ -766,44 +782,32 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 1 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {chipset_impl/gen2_polara_top_i/ui_clk_syn_rst_delayed_reg_0[0]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]} {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 2 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {chipset_impl/uart_top/writer_str_sel[0]} {chipset_impl/uart_top/writer_str_sel[1]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 1 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list chipset_impl/uart_top/atg_init_done]] +set_property port_width 32 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_out/separator/D[0]} {fpga_bridge/fpga_chip_out/separator/D[1]} {fpga_bridge/fpga_chip_out/separator/D[2]} {fpga_bridge/fpga_chip_out/separator/D[3]} {fpga_bridge/fpga_chip_out/separator/D[4]} {fpga_bridge/fpga_chip_out/separator/D[5]} {fpga_bridge/fpga_chip_out/separator/D[6]} {fpga_bridge/fpga_chip_out/separator/D[7]} {fpga_bridge/fpga_chip_out/separator/D[8]} {fpga_bridge/fpga_chip_out/separator/D[9]} {fpga_bridge/fpga_chip_out/separator/D[10]} {fpga_bridge/fpga_chip_out/separator/D[11]} {fpga_bridge/fpga_chip_out/separator/D[12]} {fpga_bridge/fpga_chip_out/separator/D[13]} {fpga_bridge/fpga_chip_out/separator/D[14]} {fpga_bridge/fpga_chip_out/separator/D[15]} {fpga_bridge/fpga_chip_out/separator/D[16]} {fpga_bridge/fpga_chip_out/separator/D[17]} {fpga_bridge/fpga_chip_out/separator/D[18]} {fpga_bridge/fpga_chip_out/separator/D[19]} {fpga_bridge/fpga_chip_out/separator/D[20]} {fpga_bridge/fpga_chip_out/separator/D[21]} {fpga_bridge/fpga_chip_out/separator/D[22]} {fpga_bridge/fpga_chip_out/separator/D[23]} {fpga_bridge/fpga_chip_out/separator/D[24]} {fpga_bridge/fpga_chip_out/separator/D[25]} {fpga_bridge/fpga_chip_out/separator/D[26]} {fpga_bridge/fpga_chip_out/separator/D[27]} {fpga_bridge/fpga_chip_out/separator/D[28]} {fpga_bridge/fpga_chip_out/separator/D[29]} {fpga_bridge/fpga_chip_out/separator/D[30]} {fpga_bridge/fpga_chip_out/separator/D[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 1 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list chipset_impl/init_calib_complete_ff]] +set_property port_width 2 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/data_channel_fff[0]} {fpga_bridge/fpga_chip_in/data_channel_fff[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 1 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/uart_top/mux_sel_reg[0]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {chipset_impl/uart_top/mux_sel_reg[1]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/test_bad_end]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/test_good_end]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/uart_tx]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list uart_tx_OBUF]] +set_property port_width 2 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] From bc7344e83364048acf684e4c468c66e6b16a6ccc Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 31 Jul 2024 16:50:21 -0400 Subject: [PATCH 099/144] Commands to get to hello world --- .../src/proto/genesys2/jtag_axi_commands.tcl | 64 ++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl index 098645a01..2f4b77bad 100644 --- a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -77,6 +77,8 @@ run_hw_axi [get_hw_axi_txns rstoff] # ------------------------------------------ # Test bypass # ------------------------------------------ +create_hw_axi_txn -force fllrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000010} -len 1 -type write +run_hw_axi [get_hw_axi_txns fllrstoff] # 1. Set bypass = 1, opmode = 1, fll_rst_n = 1 create_hw_axi_txn -force bypassrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000070} -len 1 -type write run_hw_axi [get_hw_axi_txns bypassrstoff] @@ -131,10 +133,10 @@ run_hw_axi [get_hw_axi_txns rston] # Test FLL, f_fll = 2^4 * f_ref # ------------------------------------------ # 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0100 -create_hw_axi_txn -force op4rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000450} -len 1 -type write +create_hw_axi_txn -force op4rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000350} -len 1 -type write run_hw_axi [get_hw_axi_txns op4rstoff] # 2. Set cfgreq = 1 -create_hw_axi_txn -force op4cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000004D0} -len 1 -type write +create_hw_axi_txn -force op4cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000003D0} -len 1 -type write run_hw_axi [get_hw_axi_txns op4cfg] # 3. Set cfgreq = 0 run_hw_axi [get_hw_axi_txns op4rstoff] @@ -153,3 +155,61 @@ run_hw_axi [get_hw_axi_txns op8cfg] run_hw_axi [get_hw_axi_txns op8rstoff] # 4. Reset everything run_hw_axi [get_hw_axi_txns rston] + +# ------------------------------------------ +# Hello world, no FLL (brouillon) +# ------------------------------------------ +# 1. rst_n off +create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rstoff] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_async_mux = 1, chip_clk_en = 1, chip_clk_mux_sel = 1, rst on +create_hw_axi_txn -force cfgrst [get_hw_axis hw_axi_1] -address 40000000 -data {0000000E} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrst] +# 4. cfg take off rst +create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {0000000F} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrstoff] + + +# ------------------------------------------ +# Hello world, with FLL +# ------------------------------------------ +# FLL previously configured with range = 2 +# 1. Keep the config but activate: async_mux = 1, clk_en = 1 +create_hw_axi_txn -force en2rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000256} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rston] +# 2. Release the reset +create_hw_axi_txn -force en2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000257} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rstoff] + +# Does not seem to work + +# ------------------------------------------ +# Hello world, with FLL +# ------------------------------------------ +# 1. rst_n off +create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rstoff] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_clk_mux_sel = 1 (seems to work cuz current goes up) +create_hw_axi_txn -force muxon [get_hw_axis hw_axi_1] -address 40000000 -data {00000008} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns muxon] +# 3. chip_clk_en = 1 +create_hw_axi_txn -force enon [get_hw_axis hw_axi_1] -address 40000000 -data {0000000C} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns enon] +# 4. Take rst off (current goes down a bit) +create_hw_axi_txn -force syson [get_hw_axis hw_axi_1] -address 40000000 -data {0000000D} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns syson] From 50d37a9e7568e58cc36ebbc47b3273398b66d0bb Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 6 Aug 2024 09:58:36 -0400 Subject: [PATCH 100/144] Added ILA on the NOC's axi bus. --- piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl index d2076bd96..0ffb3b7e9 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -340,6 +340,9 @@ proc create_root_design { parentCell } { CONFIG.C_TRI_DEFAULT {0x00000300} \ ] $axi_gpio_0 + # Create instance: ila_0, and set properties + set ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_0 ] + # Create instance: jtag_axi_0, and set properties set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] set_property -dict [ list \ @@ -376,6 +379,7 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] +connect_bd_intf_net -intf_net [get_bd_intf_nets S01_AXI_0_1] [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins ila_0/SLOT_0_AXI] connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus_o] [get_bd_intf_pins axi_gpio_0/GPIO] connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports polara_gen2chipset_bus_i] [get_bd_intf_pins axi_gpio_0/GPIO2] connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] @@ -385,7 +389,7 @@ proc create_root_design { parentCell } { # Create port connections connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] - connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins ila_0/clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] From 8b74afa426ab3d2f8538c5a2dbcc55adb20c4630 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 6 Aug 2024 10:04:17 -0400 Subject: [PATCH 101/144] Removed unexisting signal. --- piton/design/chipset/rtl/chipset.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 1cc03f0c5..638c6bc1b 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -826,7 +826,7 @@ end assign leds[3] = chipset_rst_n_ff; assign leds[4] = piton_prsnt_n; assign leds[5] = test_start; - assign leds[6] = FMC_PRSNT; + assign leds[6] = chip_rst_n; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART `ifdef PITONSYS_UART_BOOT From f4d2463431e8ea2105fe7dcc78eee84eb93acb66 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 6 Aug 2024 10:08:51 -0400 Subject: [PATCH 102/144] update constraints for polara daugther board --- .../chipset/xilinx/genesys2/constraints.xdc | 156 +++++++++--------- 1 file changed, 78 insertions(+), 78 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index a09f5bb9f..225670ba5 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -224,34 +224,34 @@ set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports fll_clkdiv] set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports fll_lock] set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports fll_cfg_req] set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS18} [get_ports fll_opmode] -set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS18} [get_ports fll_range[3]] -set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports fll_range[2]] -set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS18} [get_ports fll_range[1]] -set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports fll_range[0]] +set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS18} [get_ports {fll_range[3]}] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports {fll_range[2]}] +set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS18} [get_ports {fll_range[1]}] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports {fll_range[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] #set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] #set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] -set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] #set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] #set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] #set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] -set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] #set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] #set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] -set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[12]}] #set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] #set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] @@ -259,7 +259,7 @@ set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] #set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[2]}] #set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] #set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] @@ -267,239 +267,239 @@ set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports chip_intf_cr #set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] #set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] -set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] +set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_channel[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] #set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] #set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] -set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] #set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] #set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] -set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] #set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] #set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] -set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] #set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] #set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] -set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] #set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] #set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] -set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] #set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] #set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] -set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] #set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] #set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] #set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] #set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] -set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[25]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] #set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] #set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] -set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] #set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] #set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[16]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] #set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] #set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] -set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] #set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] #set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] -set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[14]] +set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] #set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] #set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] -set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] #set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] #set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[11]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] #set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] #set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] -set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] #set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] #set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] -set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] #set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] #set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] -set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] #set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] #set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[9]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] #set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] #set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] -set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] #set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] #set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] #set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] #set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[31]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] #set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] #set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] -set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] #set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] #set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] #set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] #set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[6]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] #set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] #set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] #set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] #set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] #set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] -set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[15]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] #set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] #set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] -set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[13]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] #set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] #set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] -set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] #set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] #set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] -set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] #set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] #set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] -set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[18]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] #set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] #set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] -set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] #set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] #set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] -set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] #set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] #set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] -set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] #set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] #set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] -set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[10]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] #set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] #set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] -set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[14]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] #set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] #set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] #set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] #set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] -set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[30]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] #set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] #set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] -set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[22]}] #set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] #set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] @@ -510,61 +510,61 @@ set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports intf_chip_da #set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] #set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] -set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[29]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] #set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] #set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] #set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] -set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_channel[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] #set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] #set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] -set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[20]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] #set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] #set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[28]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] #set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] #set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] -set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] #set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] #set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] -set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] #set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] #set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] -set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[21]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] #set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] #set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] -set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] #set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] #set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] -set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[27]}] set_property PACKAGE_PIN F13 [get_ports piton_ready_n] set_property IOSTANDARD LVCMOS18 [get_ports piton_ready_n] @@ -575,116 +575,116 @@ set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS18} [get_ports chipset_prsn #set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] #set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] -set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[7]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] #set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] #set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] -set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[8]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] #set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] #set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] -set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] #set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] #set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[23]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] #set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] #set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] -set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[27]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] #set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] #set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[17]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] #set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] #set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[24]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] #set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] #set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[26]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] #set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] #set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] -set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[19]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] #set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] #set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] -set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] #set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] #set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[12]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] #set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] #set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] #set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] #set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[4]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] #set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] #set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] #set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] #set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[3]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] #set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] #set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] #set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] #set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] #set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] -set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[5]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] #set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] #set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[2]}] #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] #set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] From d3040e6735be396f2014a9e4d0569642a4edd5b6 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 7 Aug 2024 09:22:47 -0400 Subject: [PATCH 103/144] Start of adding option for a vc707 chipset. --- piton/tools/src/proto/protosyn,2.5 | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 9c41b5058..9f78828eb 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -146,7 +146,9 @@ def usage(): print("\n --vc707chip", file=sys.stderr) print(" Sets POLARA_VC707_CHIP rtl define used to recreate Polara chip on VC707 FPGA (False by default)", file=sys.stderr) print(" Assumes vc707 board is chosen", file=sys.stderr) -# parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) + print("\n --vc707chipset", file=sys.stderr) + print(" Sets POLARA_VC707_CHIPSET rtl define used to recreate Polara chipset on VC707 FPGA (False by default)", file=sys.stderr) + print(" Assumes vc707 board is chosen", file=sys.stderr) print("\n --gen2chipset", file=sys.stderr) print(" Sets POLARA_GEN2_CHIPSET define.", file=sys.stderr) print(" Assumes genesys2 board is chosen", file=sys.stderr) @@ -502,6 +504,7 @@ def setParserOptions(parser): parser.add_option("--zeroer_off", dest="zeroer_off", action="store_true", default=False) parser.add_option("--postroutephysopt", dest="postroutephysopt", action="store_true", default=False) parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) + parser.add_option("--vc707chipset", dest="polara_vc707_chipset_flag", action="store_true", default=False) parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) parser.add_option("--se", dest="se", action="store_true", default=False) @@ -644,8 +647,16 @@ def makeDefList(options): # --vc707chip option if options.polara_vc707_chip_flag == True: + # Set RTL define defines.append("POLARA_VC707_CHIP") + # --vc707chipset option + if options.polara_vc707_chipset_flag == True: + # Set RTL define + defines.append("POLARA_VC707_CHIPSET") + # Set environnment variable + os.environ["POLARA_VC707_CHIPSET"] = "1" + # --gen2chipset option if options.gen2_chipset == True: # Set RTL define From 07dac1ea765c4214be4664a0e68f5b9251f19b4f Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 7 Aug 2024 15:39:43 -0400 Subject: [PATCH 104/144] Initial revision. --- piton/tools/src/proto/ila_analyze.py | 237 +++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 piton/tools/src/proto/ila_analyze.py diff --git a/piton/tools/src/proto/ila_analyze.py b/piton/tools/src/proto/ila_analyze.py new file mode 100644 index 000000000..85d88a364 --- /dev/null +++ b/piton/tools/src/proto/ila_analyze.py @@ -0,0 +1,237 @@ +#!/usr/bin/env python3 +# +# +##################################################################### +# Filename : ila_analze.py +# Version : +# Created On : 2024-08-07 +# Author : Raphael Rowley +# Company : Polytechnique Montreal +# Email : raphael.rowley@polymtl.ca +# +# Description : Analyzes data got from Polara testing with ILA +# +##################################################################### + +import argparse +import csv + +INTERVAL_SAMPLES = 25 +RADIX = 'Radix - UNSIGNED' +HEADERS = ['Sample in Buffer', 'Sample in Window', 'TRIGGER', 'fpga_bridge/fpga_chip_out/serial_buffer_channel[1:0]', 'fpga_bridge/fpga_chip_out/credit_from_chip_ff[2:0]', 'fpga_bridge/fpga_chip_out/separator/D[31:0]', 'u_ila_0_data_channel_fff[1:0]', 'fpga_bridge/fpga_chip_in/credit_fifo_out[2:0]', 'u_ila_0_buffered_data[63:0]', 'u_ila_0_buffered_channel[1:0]'] + +ser_buff_channff0 = '0' +cred_frm_chip0 = '0' +d0 = '00000000' +channfff0 = '2' +credfifo_out0 = '0' +buff_data0 = '8083800800000000' +buff_chan0 = '0' + +ser_buff_channff1 = '0' +cred_frm_chip1 = '0' +d1 = '00000000' +channfff1 = '2' +credfifo_out1 = '0' +buff_data1 = '8000000080838008' +buff_chan1 = '2' + +ser_buff_channff2 = '0' +cred_frm_chip2 = '0' +d2 = '00000000' +channfff2 = '2' +credfifo_out2 = '0' +buff_data2 = '00000b0080838008' +buff_chan2 = '0' + +ser_buff_channff3 = '0' +cred_frm_chip3 = '0' +d3 = '00000000' +channfff3 = '2' +credfifo_out3 = '0' +buff_data3 = '00fff10100000b00' +buff_chan3 = '2' + +ser_buff_channff4 = '0' +cred_frm_chip4 = '0' +d4 = '00000000' +channfff4 = '2' +credfifo_out4 = '0' +buff_data4 = '0000000000000b00' +buff_chan4 = '0' + +def packet_compare(packet, ser_buff_channff, cred_frm_chip, d, channfff, credfifo_out, buff_data, buff_chan): + if packet == 0: + if ser_buff_channff == ser_buff_channff0: + if cred_frm_chip == cred_frm_chip0: + if d == d0: + if channfff == channfff0: + if credfifo_out == credfifo_out0: + if buff_data == buff_data0: + if buff_chan == buff_chan0: + return 0 + else: + print("In packet 0, buff_chan is", buff_chan, "not", buff_chan0) + else: + print("In packet 0, buff_data is", buff_data, "not", buff_data0) + else: + print("In packet 0, credfifo_out is", credfifo_out, "not", credfifo_out0) + else: + print("In packet 0, channfff is", channfff, "not", channfff0) + else: + print("In packet 0, d is", d, "not", d0) + else: + print("In packet 0, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip0) + else: + print("In packet 0, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff0) + if packet == 1: + if ser_buff_channff == ser_buff_channff1: + if cred_frm_chip == cred_frm_chip1: + if d == d1: + if channfff == channfff1: + if credfifo_out == credfifo_out1: + if buff_data == buff_data1: + if buff_chan == buff_chan1: + return 0 + else: + print("In packet 1, buff_chan is", buff_chan, "not", buff_chan1) + else: + print("In packet 1, buff_data is", buff_data, "not", buff_data1) + else: + print("In packet 1, credfifo_out is", credfifo_out, "not", credfifo_out1) + else: + print("In packet 1, channfff is", channfff, "not", channfff1) + else: + print("In packet 1, d is", d, "not", d1) + else: + print("In packet 1, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip1) + else: + print("In packet 1, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff1) + if packet == 2: + if ser_buff_channff == ser_buff_channff2: + if cred_frm_chip == cred_frm_chip2: + if d == d2: + if channfff == channfff2: + if credfifo_out == credfifo_out2: + if buff_data == buff_data2: + if buff_chan == buff_chan2: + return 0 + else: + print("In packet 2, buff_chan is", buff_chan, "not", buff_chan2) + else: + print("In packet 2, buff_data is", buff_data, "not", buff_data2) + else: + print("In packet 2, credfifo_out is", credfifo_out, "not", credfifo_out2) + else: + print("In packet 2, channfff is", channfff, "not", channfff2) + else: + print("In packet 2, d is", d, "not", d2) + else: + print("In packet 2, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip2) + else: + print("In packet 2, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff2) + if packet == 3: + if ser_buff_channff == ser_buff_channff3: + if cred_frm_chip == cred_frm_chip3: + if d == d3: + if channfff == channfff3: + if credfifo_out == credfifo_out3: + if buff_data == buff_data3: + if buff_chan == buff_chan3: + return 0 + else: + print("In packet 3, buff_chan is", buff_chan, "not", buff_chan3) + else: + print("In packet 3, buff_data is", buff_data, "not", buff_data3) + else: + print("In packet 3, credfifo_out is", credfifo_out, "not", credfifo_out3) + else: + print("In packet 3, channfff is", channfff, "not", channfff3) + else: + print("In packet 3, d is", d, "not", d3) + else: + print("In packet 3, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip3) + else: + print("In packet 3, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff3) + if packet == 4: + if ser_buff_channff == ser_buff_channff4: + if cred_frm_chip == cred_frm_chip4: + if d == d4: + if channfff == channfff4: + if credfifo_out == credfifo_out4: + if buff_data == buff_data4: + if buff_chan == buff_chan4: + return 0 + else: + print("In packet 4, buff_chan is", buff_chan, "not", buff_chan4) + else: + print("In packet 4, buff_data is", buff_data, "not", buff_data4) + else: + print("In packet 4, credfifo_out is", credfifo_out, "not", credfifo_out4) + else: + print("In packet 4, channfff is", channfff, "not", channfff4) + else: + print("In packet 4, d is", d, "not", d4) + else: + print("In packet 4, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip4) + else: + print("In packet 4, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff4) + +def main(): + + # Init + parser = argparse.ArgumentParser(description='Process ILA saved data.') + parser.add_argument('-f', '--file', help='File to analyze (assumes CSV).') + args = parser.parse_args() + + # Check inputs + if len(args.file) < 1: + print("Empty file provided") + return -1 + datafile = args.file + + # Load CSV + with open(datafile, newline='') as datacsv: + trigreader = csv.DictReader(datacsv) + + # Find trigger + for row in trigreader: + if row['TRIGGER'] == '1': + trigpoint = row['Sample in Buffer'] + print("Found trigger point, it is: ", trigpoint) + break + iterator = 0 + iterator1 = 0 + iterator2 = 0 + iterator3 = 0 + iterator4 = 0 + datacsv.seek(0) + datareader = csv.DictReader(datacsv) + print(datareader.fieldnames) + for row in datareader: + if row['Sample in Buffer'] != RADIX: + if (int(row['Sample in Buffer']) >= int(trigpoint)) and (int(row['Sample in Buffer']) < int(trigpoint) + INTERVAL_SAMPLES): + #print("First packet", iterator, "Sample:", row['Sample in Buffer']) + packet_compare(0, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (2*INTERVAL_SAMPLES)): + #print("Second packet", iterator1, "Sample:", row['Sample in Buffer']) + packet_compare(1, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator1 += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (2*INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (3*INTERVAL_SAMPLES)): + #print("Third packet", iterator2, "Sample:", row['Sample in Buffer']) + packet_compare(2, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator2 += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (3*INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (4*INTERVAL_SAMPLES)): + #print("Fourth packet", iterator3, "Sample:", row['Sample in Buffer']) + packet_compare(3, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator3 += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (4*INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (5*INTERVAL_SAMPLES)): + #print("Fifth packet", iterator4, "Sample:", row['Sample in Buffer']) + packet_compare(4, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator4 += 1 + +if __name__ == '__main__': + + main() + From 242675da4bddb62801a3349153a89f0aa47df32a Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 7 Aug 2024 16:08:37 -0400 Subject: [PATCH 105/144] Distinct port for io_clk on the mmcm. --- piton/design/chipset/rtl/chipset.v | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index aab40f267..4765ba362 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -687,6 +687,9 @@ wire sd_clk_out_internal; // the packet filter to peripherals flags invalid accesses wire invalid_access; +`ifdef POLARA_GEN2_CHIPSETSE + wire io_clk_wire; +`endif ////////////////////// // Sequential Logic // @@ -728,7 +731,12 @@ end // this chipset clocks. This means everything is synchronous // to the same clock assign core_ref_clk = chipset_clk; - assign io_clk = chipset_clk; + `ifndef POLARA_GEN2_CHIPSETSE + assign io_clk = chipset_clk; + `else + assign io_clk = io_clk_wire; + `endif + `endif // PITON_CLKS_CHIPSET `endif // PITON_BOARD @@ -940,6 +948,10 @@ end .clk_in1(clk_osc), `endif // endif PITON_CHIPSET_DIFF_CLK + `ifdef POLARA_GEN2_CHIPSETSE + .io_clk(io_clk_wire), + `endif + .reset(1'b0), .locked(clk_locked), @@ -1090,6 +1102,7 @@ fpga_bridge( .fpga_out_clk (chipset_clk ), .fpga_in_clk (chipset_clk ), + `ifndef POLARA_GEN2_CHIPSETSE `ifdef PITONSYS_INC_PASSTHRU .intf_out_clk (chipset_passthru_clk ), .intf_in_clk (passthru_chipset_clk ), @@ -1097,6 +1110,11 @@ fpga_bridge( .intf_out_clk (io_clk_loopback ), .intf_in_clk (io_clk_loopback ), `endif // endif PITONSYS_INC_PASSTHRU + `endif // endif POLARA_GEN2_CHIPSETSE + `ifdef POLARA_GEN2_CHIPSETSE + .intf_out_clk (io_clk_wire ), + .intf_in_clk (io_clk_wire ), + `endif .fpga_intf_data_noc1(fpga_intf_data_noc1), .fpga_intf_data_noc2(fpga_intf_data_noc2), From b8af58bc21eda424077edef3c7b1a302f1c1f84b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 7 Aug 2024 16:11:15 -0400 Subject: [PATCH 106/144] Start of work to have two phase options for io_clk --- piton/design/chipset/rtl/chipset.v | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index aab40f267..f4d3c7c78 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -541,6 +541,12 @@ module chipset( wire io_clk_wire; `endif // endif PITON_CHIPSET_CLKS_GEN +`ifdef POLARA_GEN2_CHIPSETSE + wire io_clk_wire_phase_sel; + wire io_clk_wire_phase_sel_f; + wire io_clk_wire_phase_sel_ff; +`endif + `ifdef PITON_BOARD // Internal generated clocks wire core_ref_clk_inter; @@ -714,6 +720,15 @@ end end `endif // PITON_BOARD +`ifdef POLARA_GEN2_CHIPSETSE +// Synchronizing with chipset_clk even if it's only to control a selection bit of a 'MUX' +always @(posedge chipset_clk) +begin + io_clk_wire_phase_sel_f <= io_clk_wire_phase_sel; + io_clk_wire_phase_sel_ff <= io_clk_wire_phase_sel_ff; +end +`endif // POLARA_GEN2_CHIPSETSE + ///////////////////////// // Combinational Logic // ///////////////////////// From 05007464efc8738308b60cf0a4af82ebeaf941a8 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 7 Aug 2024 16:24:12 -0400 Subject: [PATCH 107/144] Added comment --- piton/tools/src/proto/ila_analyze.py | 1 + 1 file changed, 1 insertion(+) diff --git a/piton/tools/src/proto/ila_analyze.py b/piton/tools/src/proto/ila_analyze.py index 85d88a364..4fc6615eb 100644 --- a/piton/tools/src/proto/ila_analyze.py +++ b/piton/tools/src/proto/ila_analyze.py @@ -208,6 +208,7 @@ def main(): datacsv.seek(0) datareader = csv.DictReader(datacsv) print(datareader.fieldnames) + # Analyze data for row in datareader: if row['Sample in Buffer'] != RADIX: if (int(row['Sample in Buffer']) >= int(trigpoint)) and (int(row['Sample in Buffer']) < int(trigpoint) + INTERVAL_SAMPLES): From 155be6e4c69381dd8d1e2e3cbb39a2ef50416ed5 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 7 Aug 2024 16:30:10 -0400 Subject: [PATCH 108/144] Ability to choose at run time between 2 io_clk phases. --- piton/design/chipset/rtl/chipset.v | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index b81a7f452..7874b30e5 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -538,10 +538,11 @@ module chipset( `ifdef PITON_CHIPSET_CLKS_GEN wire chipset_clk; wire mc_clk; - wire io_clk_wire; `endif // endif PITON_CHIPSET_CLKS_GEN `ifdef POLARA_GEN2_CHIPSETSE + wire io_clk_wire; + wire io_clk_wire_int; wire io_clk_wire_phase_sel; wire io_clk_wire_phase_sel_f; wire io_clk_wire_phase_sel_ff; @@ -693,10 +694,6 @@ wire sd_clk_out_internal; // the packet filter to peripherals flags invalid accesses wire invalid_access; -`ifdef POLARA_GEN2_CHIPSETSE - wire io_clk_wire; -`endif - ////////////////////// // Sequential Logic // ////////////////////// @@ -728,7 +725,7 @@ end always @(posedge chipset_clk) begin io_clk_wire_phase_sel_f <= io_clk_wire_phase_sel; - io_clk_wire_phase_sel_ff <= io_clk_wire_phase_sel_ff; + io_clk_wire_phase_sel_ff <= io_clk_wire_phase_sel_f; end `endif // POLARA_GEN2_CHIPSETSE @@ -736,6 +733,12 @@ end // Combinational Logic // ///////////////////////// +`ifdef POLARA_GEN2_CHIPSETSE + assign io_clk_wire = io_clk_wire_phase_sel_ff ? io_clk_wire_int : (~io_clk_wire_int); + assign io_clk_wire_phase_sel = sw[5]; + +`endif // POLARA_GEN2_CHIPSETSE + `ifndef PITON_BOARD `ifndef PITONSYS_INC_PASSTHRU assign io_clk_loopback = io_clk; @@ -888,7 +891,7 @@ end assign leds[2] = test_start; assign leds[3] = init_calib_complete; assign leds[4] = chipset_rst_n_ff; - assign leds[5] = rst_n_rect; + assign leds[5] = io_clk_wire_phase_sel_ff; assign leds[6] = rst_n; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART @@ -964,7 +967,7 @@ end `endif // endif PITON_CHIPSET_DIFF_CLK `ifdef POLARA_GEN2_CHIPSETSE - .io_clk(io_clk_wire), + .io_clk(io_clk_wire_int), `endif .reset(1'b0), From 0dffe62916783755428a1ad4009a52a09db032d1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 9 Aug 2024 10:10:37 -0400 Subject: [PATCH 109/144] Added protosyn option --noctest to instantiate chipset_impl_noc_power_test module. --- piton/tools/src/proto/protosyn,2.5 | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 9f78828eb..e24565dbf 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -150,8 +150,14 @@ def usage(): print(" Sets POLARA_VC707_CHIPSET rtl define used to recreate Polara chipset on VC707 FPGA (False by default)", file=sys.stderr) print(" Assumes vc707 board is chosen", file=sys.stderr) print("\n --gen2chipset", file=sys.stderr) - print(" Sets POLARA_GEN2_CHIPSET define.", file=sys.stderr) + print(" Sets POLARA_GEN2_CHIPSET define. Necessary with --se to create the Polara chipset.", file=sys.stderr) print(" Assumes genesys2 board is chosen", file=sys.stderr) + print("\n --se", file=sys.stderr) + print(" Sets POLARA_GEN2_CHIPSETSE define.", file=sys.stderr) + print(" Assumes genesys2 board is chosen", file=sys.stderr) + print("\n --noctest", file=sys.stderr) + print(" Sets PITON_NOC_POWER_CHIPSET_TEST define.", file=sys.stderr) + print(" To generate packets to test Polara's NOC.", file=sys.stderr) print("\n -h, --help", file=sys.stderr) print(" Display this help message and exit", file=sys.stderr) print("\n", file=sys.stderr) @@ -507,6 +513,7 @@ def setParserOptions(parser): parser.add_option("--vc707chipset", dest="polara_vc707_chipset_flag", action="store_true", default=False) parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) parser.add_option("--se", dest="se", action="store_true", default=False) + parser.add_option("--noctest", dest="noctest", action="store_true", default=False) return parser @@ -669,6 +676,13 @@ def makeDefList(options): # Set environnment variable os.environ["POLARA_GEN2_CHIPSETSE"] = "1" + # --noctest option + if options.noctest == True: + # Set RTL define + defines.append("PITON_NOC_POWER_CHIPSET_TEST") + # Set environnment variable + os.environ["PITON_NOC_POWER_CHIPSET_TEST"] = "1" + return defines def makeMemMapping(st_brd, work_dir, log_dir): From 70c2685f07de0b8c9dbd055eb1dd007851d8cb36 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 9 Aug 2024 10:30:43 -0400 Subject: [PATCH 110/144] Fixing chipset_impl_noc_power_test instanciation --- piton/design/chipset/rtl/chipset.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 7874b30e5..abd2cef6f 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1340,13 +1340,15 @@ chipset_impl_noc_power_test chipset_impl ( .piton_ready_n (piton_ready_n ), .test_start (test_start ), - .uart_rst_out_n (uart_rst_out_n ), - .invalid_access_o (invalid_access ), - + `ifdef PITON_NOC_POWER_CHIPSET_TEST .noc_power_test_hop_count (noc_power_test_hop_count), +`else + .uart_rst_out_n (uart_rst_out_n ), + .invalid_access_o (invalid_access ), `endif +`ifndef PITON_NOC_POWER_CHIPSET_TEST `ifdef POLARA_GEN2_CHIPSET `ifdef POLARA_GEN2_CHIPSETSE .mig_ddr3_sys_se_clock_clk(mc_clk), @@ -1366,6 +1368,7 @@ chipset_impl_noc_power_test chipset_impl ( .mig_ddr3_sys_diff_clock_clk_p(clk_osc_p), `endif // POLARA_GEN2_CHIPSETSE `endif // POLARA_GEN2_CHIPSET +`endif // PITON_NOC_POWER_CHIPSET_TEST `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 From 746c74633f6752ee0f4d0d6f51382184fe4b51e5 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 9 Aug 2024 10:31:46 -0400 Subject: [PATCH 111/144] Fixing signal types and fixed timing issue --- piton/design/chipset/rtl/chipset.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 7874b30e5..6fb3a4ce3 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -544,8 +544,8 @@ module chipset( wire io_clk_wire; wire io_clk_wire_int; wire io_clk_wire_phase_sel; - wire io_clk_wire_phase_sel_f; - wire io_clk_wire_phase_sel_ff; + reg io_clk_wire_phase_sel_f; + reg io_clk_wire_phase_sel_ff; `endif `ifdef PITON_BOARD @@ -1130,8 +1130,8 @@ fpga_bridge( `endif // endif PITONSYS_INC_PASSTHRU `endif // endif POLARA_GEN2_CHIPSETSE `ifdef POLARA_GEN2_CHIPSETSE - .intf_out_clk (io_clk_wire ), - .intf_in_clk (io_clk_wire ), + .intf_out_clk (io_clk_wire_int ), + .intf_in_clk (io_clk_wire_int ), `endif .fpga_intf_data_noc1(fpga_intf_data_noc1), From 461f30de6f0f0bf8114dd0ce43d3b545b5a474cc Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 9 Aug 2024 10:45:54 -0400 Subject: [PATCH 112/144] Fixing chipset_impl_noc_power_test instanciation --- piton/design/chipset/rtl/chipset.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index abd2cef6f..832870f5a 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1506,11 +1506,13 @@ chipset_impl_noc_power_test chipset_impl ( , .uart_tx(uart_tx), .uart_rx(uart_rx) + `ifndef PITON_NOC_POWER_CHIPSET_TEST `ifdef PITONSYS_UART_BOOT , .uart_boot_en(uart_boot_en), .uart_timeout_en(uart_timeout_en) `endif // endif PITONSYS_UART_BOOT + `endif // PITON_NOC_POWER_CHIPSET_TEST `endif // endif PITONSYS_UART `ifdef PITONSYS_SPI @@ -1527,6 +1529,7 @@ chipset_impl_noc_power_test chipset_impl ( .sd_cmd(sd_cmd), .sd_dat(sd_dat) `endif // endif PITONSYS_SPI + `ifndef PITON_NOC_POWER_CHIPSET_TEST `ifdef PITON_FPGA_ETHERNETLITE , .net_axi_clk (net_axi_clk ), @@ -1544,7 +1547,8 @@ chipset_impl_noc_power_test chipset_impl ( .net_phy_mdio_io (net_phy_mdio_io ), .net_phy_mdc (net_phy_mdc ) - `endif // PITON_FPGA_ETHERNETLITE + `endif // PITON_FPGA_ETHERNETLITE + `endif // PITON_NOC_POWER_CHIPSET_TEST `endif // endif PITONSYS_IOCTRL `ifdef ALVEO_BOARD From ce9e3e5f683e017ea662a5be9e82a3c327104b62 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 14 Aug 2024 14:20:05 -0400 Subject: [PATCH 113/144] Removed multi phase io clk chooser. --- .../ip_cores/atg_uart_init/atg_uart_init.xci | 6 +- .../ip_cores/atg_uart_init/uart_data.coe | 2 +- .../ip_cores/uart_16550/uart_16550.xci | 6 +- .../ip_cores/atg_uart_init/uart_data.coe | 2 +- piton/design/chipset/rtl/chipset.v | 21 +---- .../chipset/xilinx/genesys2/constraints.xdc | 2 +- .../genesys2/ip_cores/clk_mmcm/clk_mmcm.xci | 78 +++++++++---------- piton/tools/src/proto/block.list | 2 +- 8 files changed, 52 insertions(+), 67 deletions(-) diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci index 3a2642bae..015a1fe2e 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci @@ -326,7 +326,7 @@ atg_uart_init_ctrl.mem atg_uart_init_data.mem atg_uart_init_mask.mem - "00000000000000000000000000000001" + 00000000000000000000000000000001 0 5000 1 @@ -642,8 +642,8 @@ tic_object":false}],"PHASE":[{"value":"0.0",& e":"m_axi_lite_ch1_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"m_axi_lite_ch1_rdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"RREADY":[{"physical_name":"m_axi_lite_ch1_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"m_axi_lite_ch1_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"physical_name":"m_axi_lite_ch1_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"m_axi_lite_ch1_wdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"m_axi_lite_ch1_wready","physical_left":"0","physical_ri ght":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"m_axi_lite_ch1_wstrb","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"m_axi_lite_ch1_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"S_AXI:M_AXI:M_AXIS_MASTER:S_AXIS_MASTER:M_AXIS_SLAVE:S_AXIS_SLAVE:M_AXI_LITE_CH1:M_AXI_LITE_CH2:M_AXI_LITE_CH3:M_AXI_LITE_CH4:M_AXI_LITE_CH5","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"s_axi_aresetn","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all", "is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"p -hysical_name":"s_axi_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"s_axi_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"address_spaces":{"Reg1":{"range":"4294967296","display_name":"","description":""}},"memory_maps":{"S_AXI":{"address_blocks":{"Reg0":[{"base_address":"0","range":"65536","display_name":"","desc -ription":"","usage":"register","access":"read-write"}]}}}}}"/> +hysical_name":"s_axi_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"s_axi_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"address_spaces":{"Reg1":{"range":"4294967296","display_name":"","description":""},"address_spaces":{"range":"1","display_name":"","description":""}},"memory_maps":{"S_AXI":{"address_blocks":{" +Reg0":[{"base_address":"0","range":"65536","display_name":"","description":"","usage":"register","access":"read-write"}]}}}}}"/> diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe index aec4227ff..aef527768 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe @@ -1,2 +1,2 @@ memory_initialization_radix=16; -memory_initialization_vector=00000080 0000001b 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; +memory_initialization_vector=00000080 00000016 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci index 7e59b48d5..0fb4b96e2 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci @@ -53,15 +53,15 @@ 0 1 VERSAL_AI_CORE_ES1 - 50000000 + 40000000 1 25000000 25 0 0 16550 - 50000000 - 50 + 40000000 + 40 1 1 uart_16550 diff --git a/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe b/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe index b35ea84ba..aec4227ff 100644 --- a/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe +++ b/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe @@ -1,2 +1,2 @@ memory_initialization_radix=16; -memory_initialization_vector=00000080 00000021 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; +memory_initialization_vector=00000080 0000001b 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 50aed3dd0..b784460c8 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -543,9 +543,6 @@ module chipset( `ifdef POLARA_GEN2_CHIPSETSE wire io_clk_wire; wire io_clk_wire_int; - wire io_clk_wire_phase_sel; - reg io_clk_wire_phase_sel_f; - reg io_clk_wire_phase_sel_ff; `endif `ifdef PITON_BOARD @@ -719,25 +716,13 @@ end fpga_intf_rdy_noc3 ? 1'b1 : passthru_fifo_init_complete; end `endif // PITON_BOARD - -`ifdef POLARA_GEN2_CHIPSETSE -// Synchronizing with chipset_clk even if it's only to control a selection bit of a 'MUX' -always @(posedge chipset_clk) -begin - io_clk_wire_phase_sel_f <= io_clk_wire_phase_sel; - io_clk_wire_phase_sel_ff <= io_clk_wire_phase_sel_f; -end -`endif // POLARA_GEN2_CHIPSETSE ///////////////////////// // Combinational Logic // ///////////////////////// - `ifdef POLARA_GEN2_CHIPSETSE - assign io_clk_wire = io_clk_wire_phase_sel_ff ? io_clk_wire_int : (~io_clk_wire_int); - assign io_clk_wire_phase_sel = sw[5]; - -`endif // POLARA_GEN2_CHIPSETSE + assign io_clk_wire = io_clk_wire_int; +`endif `ifndef PITON_BOARD `ifndef PITONSYS_INC_PASSTHRU @@ -891,7 +876,7 @@ end assign leds[2] = test_start; assign leds[3] = init_calib_complete; assign leds[4] = chipset_rst_n_ff; - assign leds[5] = io_clk_wire_phase_sel_ff; + assign leds[5] = chipset_rst_n_ff; assign leds[6] = rst_n; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index cb589450e..fca357232 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -780,7 +780,7 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] +connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/mc_sys_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 2 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]} {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]}]] diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci index d6d6373a4..1d0f1b505 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci @@ -131,22 +131,22 @@ 100.0 0000 0000 - 50.00000 + 40.00000 0000 0000 200.00000 BUFG 50.0 false - 50.00000 + 40.00000 0.000 50.000 - 50 + 40 0.000 1 0000 0000 - 50.00000 + 8.00000 BUFG 50.0 false @@ -163,10 +163,10 @@ BUFG 50.0 false - 50.00000 + 8.00000 0.000 50.000 - 50.000 + 8 0.000 1 1 @@ -223,7 +223,7 @@ clk_in_sel chipset_clk mc_sys_clk - sd_sys_clk + io_clk chipset_passthru_clk chipset_passthru_clk_n net_phy_clk @@ -236,12 +236,12 @@ din 0000 1 - 0.25 - 1.0 - 0.5 - 0.5 - 2.0 - 0.5 + 0.2 + 5.0 + 0.4 + 0.4 + 1.6 + 0.4 dout drdy dwe @@ -284,7 +284,7 @@ FALSE 5.000 10.0 - 20.000 + 25.000 0.500 0.000 FALSE @@ -292,7 +292,7 @@ 0.500 0.000 FALSE - 20 + 125 0.500 0.000 FALSE @@ -326,9 +326,9 @@ 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - chipset_clk__50.00000______0.000______50.0______129.198_____89.971 + chipset_clk__40.00000______0.000______50.0______135.255_____89.971 mc_sys_clk__200.00000______0.000______50.0_______98.146_____89.971 - sd_sys_clk__50.00000______0.000______50.0______129.198_____89.971 + __io_clk___8.00000______0.000______50.0______186.029_____89.971 chipset_passthru_clk__100.00000______0.000______50.0______112.316_____89.971 chipset_passthru_clk_n__100.00000____180.000______50.0______112.316_____89.971 net_phy_clk__25.00000______0.000______50.0______148.629_____89.971 @@ -448,11 +448,11 @@ 100.0 0.010 BUFG - 129.198 + 135.255 false 89.971 50.000 - 50 + 40 0.000 1 true @@ -466,11 +466,11 @@ 1 true BUFG - 129.198 + 186.029 false 89.971 50.000 - 50.000 + 8 0.000 1 true @@ -518,7 +518,7 @@ false mc_sys_clk false - sd_sys_clk + io_clk false chipset_passthru_clk false @@ -564,7 +564,7 @@ false 5.000 10.0 - 20.000 + 25.000 0.500 0.000 false @@ -572,7 +572,7 @@ 0.500 0.000 false - 20 + 125 0.500 0.000 false @@ -784,21 +784,21 @@ - + diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 457ebfa5b..2a7fe49dc 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -26,7 +26,7 @@ # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 -chipset chipset genesys2,50,1024;piton_board,50,0 +chipset chipset genesys2,40,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 chip chip genesys2,66.667,1024;vc707,50,1024 From c24aa393931f5b634127f8a6de0059f7e211df96 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 14 Aug 2024 15:42:49 -0400 Subject: [PATCH 114/144] Start of revision of debugged nets. --- .../chipset/xilinx/genesys2/constraints.xdc | 27 +++++++++---------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index fca357232..9fd0437bf 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -770,6 +770,7 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] @@ -782,32 +783,28 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/mc_sys_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 2 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]} {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]}]] +set_property port_width 32 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/separator/D[0]} {fpga_bridge/fpga_chip_out/separator/D[1]} {fpga_bridge/fpga_chip_out/separator/D[2]} {fpga_bridge/fpga_chip_out/separator/D[3]} {fpga_bridge/fpga_chip_out/separator/D[4]} {fpga_bridge/fpga_chip_out/separator/D[5]} {fpga_bridge/fpga_chip_out/separator/D[6]} {fpga_bridge/fpga_chip_out/separator/D[7]} {fpga_bridge/fpga_chip_out/separator/D[8]} {fpga_bridge/fpga_chip_out/separator/D[9]} {fpga_bridge/fpga_chip_out/separator/D[10]} {fpga_bridge/fpga_chip_out/separator/D[11]} {fpga_bridge/fpga_chip_out/separator/D[12]} {fpga_bridge/fpga_chip_out/separator/D[13]} {fpga_bridge/fpga_chip_out/separator/D[14]} {fpga_bridge/fpga_chip_out/separator/D[15]} {fpga_bridge/fpga_chip_out/separator/D[16]} {fpga_bridge/fpga_chip_out/separator/D[17]} {fpga_bridge/fpga_chip_out/separator/D[18]} {fpga_bridge/fpga_chip_out/separator/D[19]} {fpga_bridge/fpga_chip_out/separator/D[20]} {fpga_bridge/fpga_chip_out/separator/D[21]} {fpga_bridge/fpga_chip_out/separator/D[22]} {fpga_bridge/fpga_chip_out/separator/D[23]} {fpga_bridge/fpga_chip_out/separator/D[24]} {fpga_bridge/fpga_chip_out/separator/D[25]} {fpga_bridge/fpga_chip_out/separator/D[26]} {fpga_bridge/fpga_chip_out/separator/D[27]} {fpga_bridge/fpga_chip_out/separator/D[28]} {fpga_bridge/fpga_chip_out/separator/D[29]} {fpga_bridge/fpga_chip_out/separator/D[30]} {fpga_bridge/fpga_chip_out/separator/D[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 3 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]} {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 32 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_out/separator/D[0]} {fpga_bridge/fpga_chip_out/separator/D[1]} {fpga_bridge/fpga_chip_out/separator/D[2]} {fpga_bridge/fpga_chip_out/separator/D[3]} {fpga_bridge/fpga_chip_out/separator/D[4]} {fpga_bridge/fpga_chip_out/separator/D[5]} {fpga_bridge/fpga_chip_out/separator/D[6]} {fpga_bridge/fpga_chip_out/separator/D[7]} {fpga_bridge/fpga_chip_out/separator/D[8]} {fpga_bridge/fpga_chip_out/separator/D[9]} {fpga_bridge/fpga_chip_out/separator/D[10]} {fpga_bridge/fpga_chip_out/separator/D[11]} {fpga_bridge/fpga_chip_out/separator/D[12]} {fpga_bridge/fpga_chip_out/separator/D[13]} {fpga_bridge/fpga_chip_out/separator/D[14]} {fpga_bridge/fpga_chip_out/separator/D[15]} {fpga_bridge/fpga_chip_out/separator/D[16]} {fpga_bridge/fpga_chip_out/separator/D[17]} {fpga_bridge/fpga_chip_out/separator/D[18]} {fpga_bridge/fpga_chip_out/separator/D[19]} {fpga_bridge/fpga_chip_out/separator/D[20]} {fpga_bridge/fpga_chip_out/separator/D[21]} {fpga_bridge/fpga_chip_out/separator/D[22]} {fpga_bridge/fpga_chip_out/separator/D[23]} {fpga_bridge/fpga_chip_out/separator/D[24]} {fpga_bridge/fpga_chip_out/separator/D[25]} {fpga_bridge/fpga_chip_out/separator/D[26]} {fpga_bridge/fpga_chip_out/separator/D[27]} {fpga_bridge/fpga_chip_out/separator/D[28]} {fpga_bridge/fpga_chip_out/separator/D[29]} {fpga_bridge/fpga_chip_out/separator/D[30]} {fpga_bridge/fpga_chip_out/separator/D[31]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 2 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/data_channel_fff[0]} {fpga_bridge/fpga_chip_in/data_channel_fff[1]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 3 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 64 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 2 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] From e8cc30dad5acf6add27f8ee4a7015e42c6e4823c Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 15 Aug 2024 15:52:27 -0400 Subject: [PATCH 115/144] Updated ILA debug nets to assure coherence between every observed signal (same place in pipeline) --- .../chipset/xilinx/genesys2/constraints.xdc | 168 ++++++++++++++++-- 1 file changed, 155 insertions(+), 13 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 9fd0437bf..6a7ec19f4 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -59,9 +59,8 @@ set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_ # 66.666 MHz #create_clock -period 15.000 -name io_clk -waveform {0.000 7.500} [get_ports io_clk] #create_clock -period 15.000 -name core_ref_clk -waveform {0.000 7.500} [get_ports core_ref_clk] -# 50 MHz -create_clock -period 20.000 -name io_clk -waveform {0.000 10.000} [get_ports io_clk] -create_clock -period 20.000 -name core_ref_clk -waveform {0.000 10.000} [get_ports core_ref_clk] +create_clock -period 125.000 -name io_clk -waveform {0.000 62.500} [get_ports io_clk] +create_clock -period 25.000 -name core_ref_clk -waveform {0.000 12.500} [get_ports core_ref_clk] # Constraint RGMII interface @@ -771,6 +770,9 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] + + + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] @@ -783,28 +785,168 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/mc_sys_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 32 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/separator/D[0]} {fpga_bridge/fpga_chip_out/separator/D[1]} {fpga_bridge/fpga_chip_out/separator/D[2]} {fpga_bridge/fpga_chip_out/separator/D[3]} {fpga_bridge/fpga_chip_out/separator/D[4]} {fpga_bridge/fpga_chip_out/separator/D[5]} {fpga_bridge/fpga_chip_out/separator/D[6]} {fpga_bridge/fpga_chip_out/separator/D[7]} {fpga_bridge/fpga_chip_out/separator/D[8]} {fpga_bridge/fpga_chip_out/separator/D[9]} {fpga_bridge/fpga_chip_out/separator/D[10]} {fpga_bridge/fpga_chip_out/separator/D[11]} {fpga_bridge/fpga_chip_out/separator/D[12]} {fpga_bridge/fpga_chip_out/separator/D[13]} {fpga_bridge/fpga_chip_out/separator/D[14]} {fpga_bridge/fpga_chip_out/separator/D[15]} {fpga_bridge/fpga_chip_out/separator/D[16]} {fpga_bridge/fpga_chip_out/separator/D[17]} {fpga_bridge/fpga_chip_out/separator/D[18]} {fpga_bridge/fpga_chip_out/separator/D[19]} {fpga_bridge/fpga_chip_out/separator/D[20]} {fpga_bridge/fpga_chip_out/separator/D[21]} {fpga_bridge/fpga_chip_out/separator/D[22]} {fpga_bridge/fpga_chip_out/separator/D[23]} {fpga_bridge/fpga_chip_out/separator/D[24]} {fpga_bridge/fpga_chip_out/separator/D[25]} {fpga_bridge/fpga_chip_out/separator/D[26]} {fpga_bridge/fpga_chip_out/separator/D[27]} {fpga_bridge/fpga_chip_out/separator/D[28]} {fpga_bridge/fpga_chip_out/separator/D[29]} {fpga_bridge/fpga_chip_out/separator/D[30]} {fpga_bridge/fpga_chip_out/separator/D[31]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 2 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]} {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 3 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 64 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[0]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 3 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[1]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 2 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[2]_i_1__0_n_0}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list io_clk_OBUF]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +set_property port_width 1 [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +set_property port_width 1 [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +set_property port_width 1 [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +set_property port_width 1 [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +set_property port_width 1 [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +set_property port_width 1 [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] +set_property port_width 1 [get_debug_ports u_ila_0/probe34] +connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] +set_property port_width 1 [get_debug_ports u_ila_0/probe35] +connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] +set_property port_width 1 [get_debug_ports u_ila_0/probe36] +connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] +set_property port_width 1 [get_debug_ports u_ila_0/probe37] +connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] +set_property port_width 1 [get_debug_ports u_ila_0/probe38] +connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] +set_property port_width 1 [get_debug_ports u_ila_0/probe39] +connect_debug_port u_ila_0/probe39 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] +set_property port_width 1 [get_debug_ports u_ila_0/probe40] +connect_debug_port u_ila_0/probe40 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] From b297b5dc96eca4db742a78d1599a8a85c07bd216 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 19 Aug 2024 09:04:11 -0400 Subject: [PATCH 116/144] MMCM generates io_clk and not io_clk --- piton/design/chipset/rtl/chipset.v | 6 +- .../genesys2/ip_cores/clk_mmcm/clk_mmcm.xci | 64 ++++++++++--------- 2 files changed, 38 insertions(+), 32 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index b784460c8..97e59264c 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -543,6 +543,8 @@ module chipset( `ifdef POLARA_GEN2_CHIPSETSE wire io_clk_wire; wire io_clk_wire_int; + wire io_clk_not_wire_int; + wire io_clk_wire_phase_sel; `endif `ifdef PITON_BOARD @@ -721,7 +723,8 @@ end // Combinational Logic // ///////////////////////// `ifdef POLARA_GEN2_CHIPSETSE - assign io_clk_wire = io_clk_wire_int; + assign io_clk_wire_phase_sel = sw[5]; + assign io_clk_wire = io_clk_wire_phase_sel ? io_clk_not_wire_int : io_clk_wire_int; `endif `ifndef PITON_BOARD @@ -953,6 +956,7 @@ end `ifdef POLARA_GEN2_CHIPSETSE .io_clk(io_clk_wire_int), + .io_clk_not(io_clk_not_wire_int), `endif .reset(1'b0), diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci index 1d0f1b505..fdf8f5c38 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci @@ -159,7 +159,7 @@ 1 0000 0000 - 100.00000 + 8.00000 BUFG 50.0 false @@ -176,11 +176,11 @@ BUFG 50.0 false - 100.00000 - 0.000 + 8.00000 + 180.000 50.000 - 100.000 - 0.000 + 8 + 180.000 1 1 0000 @@ -224,7 +224,7 @@ chipset_clk mc_sys_clk io_clk - chipset_passthru_clk + io_clk_not chipset_passthru_clk_n net_phy_clk net_axi_clk @@ -238,7 +238,7 @@ 1 0.2 5.0 - 0.4 + 5.0 0.4 1.6 0.4 @@ -296,9 +296,9 @@ 0.500 0.000 FALSE - 10 + 125 0.500 - 0.000 + 180.000 FALSE FALSE 10 @@ -329,7 +329,7 @@ chipset_clk__40.00000______0.000______50.0______135.255_____89.971 mc_sys_clk__200.00000______0.000______50.0_______98.146_____89.971 __io_clk___8.00000______0.000______50.0______186.029_____89.971 - chipset_passthru_clk__100.00000______0.000______50.0______112.316_____89.971 + io_clk_not___8.00000____180.000______50.0______186.029_____89.971 chipset_passthru_clk_n__100.00000____180.000______50.0______112.316_____89.971 net_phy_clk__25.00000______0.000______50.0______148.629_____89.971 net_axi_clk__100.00000______0.000______50.0______112.316_____89.971 @@ -475,12 +475,12 @@ 1 true BUFG - 112.316 + 186.029 false 89.971 50.000 - 100.000 - 0.000 + 8 + 180.000 1 true BUFG @@ -520,7 +520,7 @@ false io_clk false - chipset_passthru_clk + io_clk_not false chipset_passthru_clk_n false @@ -576,9 +576,9 @@ 0.500 0.000 false - 10 + 125 0.500 - 0.000 + 180.000 false false 10 @@ -745,6 +745,7 @@ + @@ -772,6 +773,7 @@ + @@ -784,21 +786,21 @@ - + From ee1edea1aee0f8c2d923a21d65b19ec31447bbb1 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 19 Aug 2024 10:20:48 -0400 Subject: [PATCH 117/144] Took out ethernet option for Polara chipset. --- piton/tools/src/proto/protosyn,2.5 | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index e24565dbf..344d07998 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -628,7 +628,9 @@ def makeDefList(options): if options.eth or options.design == "chipset" or options.design == "system": # Ethernet controller is supported on Genesys2 and nexysVideo if options.board == "genesys2" or options.board == "nexysVideo": - defines.append("PITON_FPGA_ETHERNETLITE") + # Don't want ethernet for the Polara chipset + if options.gen2_chipset == False: + defines.append("PITON_FPGA_ETHERNETLITE") else: print_info("--eth option is ignored for %s" % options.board) From c6b4cda434bc89d7f71da6d22ec1b75bf3810acf Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 19 Aug 2024 15:41:51 -0400 Subject: [PATCH 118/144] Initial revision. --- piton/design/chipset/rtl/polara_loopback.v | 261 +++++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 piton/design/chipset/rtl/polara_loopback.v diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v new file mode 100644 index 000000000..f64f15be7 --- /dev/null +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -0,0 +1,261 @@ +`include "define.tmp.h" +`include "piton_system.vh" + +// Filename: polara_loopback.v +// Author: Raphael Rowley (2024-08) +// Contact: raphael.rowley@polymtl.ca +// Description: Chipset implementation that just sends +// dummy packets into chip to test its NoC + +module chipset_impl_polara_loopback( + // Clocks and resets + input chipset_clk, + input chipset_rst_n, + + // Misc + output test_start, + + // Main chip interface + output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, + output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, + output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3, + output chipset_intf_val_noc1, + output chipset_intf_val_noc2, + output chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, + + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3, + input intf_chipset_val_noc1, + input intf_chipset_val_noc2, + input intf_chipset_val_noc3, + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3 + + // Just dummy signals +`ifdef PITONSYS_IOCTRL +`ifdef PITONSYS_UART + , + output uart_tx, + input uart_rx +`endif // endif PITONSYS_UART +`endif // endif PITONSYS_IOCTRL +); + +/////////////////////// +// Type declarations // +/////////////////////// + +// NoC power message header +// CHIPID: 14'd0 +// XPOS: variable, depends on number of hops +// YPOS: variable, depends on number of hops +// FBITS: 4'd0 +// PAYLOAD LENGTH: 8'd6 // Max accepted by L1.5 +// MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations +// MSHR/TAG: 8'd0 +// RESERVED: 6'd0 +parameter MSG_HEADER = {14'd0, 8'd0, 8'd0, 4'd0, 8'd6, + `MSG_TYPE_INV_FWD, 8'd0, 6'd0}; + +parameter STATE_RESET = 2'd0; +parameter STATE_SEND_HEADER = 2'd1; +parameter STATE_SEND_DATA_PATTERN_A = 2'd2; +parameter STATE_SEND_DATA_PATTERN_B = 2'd3; + +reg rst_n; + +reg [1:0] state_f; +reg [1:0] state_next; + +reg [7:0] payload_count_f; +reg [7:0] payload_count_next; + +reg [`NOC_DATA_WIDTH-1:0] out_data; + +////////////////////// +// Sequential Logic // +////////////////////// + +always @ (posedge chipset_clk) +begin + if (~rst_n) + begin + state_f <= STATE_RESET; + payload_count_f <= 8'd0; + end + else + begin + state_f <= state_next; + payload_count_f <= payload_count_next; + end +end // always @ (posedge chipset_clk) + +///////////////////////// +// Combinational Logic // +///////////////////////// + +`ifdef PITONSYS_IOCTRL +`ifdef PITONSYS_UART + assign uart_tx = 1'b0; +`endif // endif PITONSYS_UART +`endif // endif PITONSYS_IOCTRL + +// State machine +always @ * +begin + state_next = state_f; + payload_count_next = payload_count_f; + + case (state_f) + STATE_RESET: + begin + state_next = STATE_SEND_HEADER; + end + STATE_SEND_HEADER: + begin + if (chipset_intf_rdy_noc2) + state_next = STATE_SEND_DATA_PATTERN_A; + end + STATE_SEND_DATA_PATTERN_A: + begin + if (chipset_intf_rdy_noc2) + begin + if (payload_count_f == 8'd5) + begin + state_next = STATE_SEND_HEADER; + payload_count_next = 8'd0; + end + else + begin + state_next = STATE_SEND_DATA_PATTERN_B; + payload_count_next = payload_count_f + 1'b1; + end + end + end + STATE_SEND_DATA_PATTERN_B: + begin + if (chipset_intf_rdy_noc2) + begin + if (payload_count_f == 8'd5) + begin + state_next = STATE_SEND_HEADER; + payload_count_next = 8'd0; + end + else + begin + state_next = STATE_SEND_DATA_PATTERN_A; + payload_count_next = payload_count_f + 1'b1; + end + end + end + endcase +end // always @ * + +// Out data generation +always @ * +begin + out_data = {`NOC_DATA_WIDTH{1'bx}}; + + case (state_f) + STATE_RESET: + begin + out_data = {`NOC_DATA_WIDTH{1'bx}}; + end + STATE_SEND_HEADER: + begin + out_data = MSG_HEADER; + case (noc_power_test_hop_count) + 4'd0: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd0; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; + end + 4'd1: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd1; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; + end + 4'd2: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd2; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; + end + 4'd3: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd3; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; + end + 4'd4: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; + end + 4'd5: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd1; + end + 4'd6: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd2; + end + 4'd7: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd3; + end + 4'd8: + begin + out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; + out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd4; + end + endcase + end + STATE_SEND_DATA_PATTERN_A: + begin +`ifdef NOC_POWER_TEST_0xA_0x5_PATTERN + out_data = {`NOC_DATA_WIDTH/2{2'b01}}; +`elsif NOC_POWER_TEST_0x0_0x0_PATTERN + out_data = {`NOC_DATA_WIDTH{1'b0}}; +`elsif NOC_POWER_TEST_0x0_0x3_PATTERN + out_data = {`NOC_DATA_WIDTH/4{4'b0011}}; +`else + out_data = {`NOC_DATA_WIDTH{1'b1}}; +`endif // endif NOC_POWER_TEST_0xA_0x5_PATTERN + end + STATE_SEND_DATA_PATTERN_B: + begin +`ifdef NOC_POWER_TEST_0xA_0x5_PATTERN + out_data = {`NOC_DATA_WIDTH/2{2'b10}}; +`elsif NOC_POWER_TEST_0x0_0x0_PATTERN + out_data = {`NOC_DATA_WIDTH{1'b0}}; +`elsif NOC_POWER_TEST_0x0_0x3_PATTERN + out_data = {`NOC_DATA_WIDTH{1'b0}}; +`else + out_data = {`NOC_DATA_WIDTH{1'b0}}; +`endif // endif NOC_POWER_TEST_0xA_0x5_PATTERN + end + endcase +end + +assign test_start = 1'b1; + +assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; +assign chipset_intf_data_noc2 = out_data; +assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; + +assign chipset_intf_val_noc1 = 1'b0; +assign chipset_intf_val_noc2 = (state_f != STATE_RESET); +assign chipset_intf_val_noc3 = 1'b0; + +assign intf_chipset_rdy_noc1 = 1'b0; +assign intf_chipset_rdy_noc2 = 1'b0; +assign intf_chipset_rdy_noc3 = 1'b0; + +endmodule From 3ee8b4fb706c52c16241d64bcbb2552fec4422b8 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Tue, 20 Aug 2024 14:39:53 -0400 Subject: [PATCH 119/144] Initial revision. Script to generate BD used for polara loopback. --- .../genesys2/gen2_polara_fpga_loopback.tcl | 261 ++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl new file mode 100644 index 000000000..241101f6f --- /dev/null +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl @@ -0,0 +1,261 @@ + +################################################################ +# This is a generated script based on design: gen2_polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source gen2_polara_fpga_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7k325tffg900-2 + set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name gen2_polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:jtag_axi:1.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:smartconnect:1.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set polara_gen2chipset_bus_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_i ] + + set polara_gen2chipset_bus_o [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_o ] + + + # Create ports + set bd_clk [ create_bd_port -dir I -type clk -freq_hz 40000000 bd_clk ] + set mig_ddr3_sys_rst_n [ create_bd_port -dir I -type rst mig_ddr3_sys_rst_n ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {2} \ + CONFIG.C_GPIO_WIDTH {12} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_TRI_DEFAULT {0x00000300} \ + ] $axi_gpio_0 + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + set_property -dict [ list \ + CONFIG.M_AXI_DATA_WIDTH {32} \ + ] $jtag_axi_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus_o] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports polara_gen2chipset_bus_i] [get_bd_intf_pins axi_gpio_0/GPIO2] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + + # Create port connections + connect_bd_net -net aclk_0_1 [get_bd_ports bd_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins proc_sys_reset_0/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + From 0c9cfa7d316e77cc52801bae832b64a324e5f1ae Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 21 Aug 2024 17:01:23 -0400 Subject: [PATCH 120/144] Completed Polara loopback module. --- piton/design/chipset/rtl/chipset.v | 15 +- piton/design/chipset/rtl/polara_loopback.v | 358 ++++++++------------- 2 files changed, 153 insertions(+), 220 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 97e59264c..b7c3279aa 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -233,6 +233,7 @@ module chipset( `endif // endif PITON_NO_CHIP_BRIDGE PITONSYS_INC_PASSTHRU // DRAM and I/O interfaces +`ifndef POLARA_LOOPBACK // No need for DDR for Polara loopback tests `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 // Generalized interface for any FPGA board we support. @@ -329,6 +330,7 @@ module chipset( `endif // ifndef F1_BOARD `endif //`ifdef PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC +`endif // `ifndef POLARA_LOOPBACK `ifdef PITONSYS_IOCTRL @@ -1320,21 +1322,28 @@ credit_to_valrdy processor_offchip_noc3_c2v( // Intantiate the actual chipset implementation `ifndef PITON_NOC_POWER_CHIPSET_TEST +`ifdef POLARA_LOOPBACK +chipset_impl_polara_loopback chipset_impl( +`else chipset_impl chipset_impl ( +`endif // ifdef POLARA_LOOPBACK `else // ifdef PITON_NOC_POWER_CHIPSET_TEST chipset_impl_noc_power_test chipset_impl ( -`endif +`endif // ifdef PITON_NOC_POWER_CHIPSET_TEST .chipset_clk (chipset_clk ), .chipset_rst_n (chipset_rst_n_ff ), +`ifndef POLARA_LOOPBACK .piton_ready_n (piton_ready_n ), - +`endif .test_start (test_start ), `ifdef PITON_NOC_POWER_CHIPSET_TEST .noc_power_test_hop_count (noc_power_test_hop_count), `else +`ifndef POLARA_LOOPBACK .uart_rst_out_n (uart_rst_out_n ), .invalid_access_o (invalid_access ), +`endif // ifndef POLARA_LOOPBACK `endif `ifndef PITON_NOC_POWER_CHIPSET_TEST @@ -1394,6 +1403,7 @@ chipset_impl_noc_power_test chipset_impl ( .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) // DRAM and I/O interfaces + `ifndef POLARA_LOOPBACK `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 , @@ -1489,6 +1499,7 @@ chipset_impl_noc_power_test chipset_impl ( `endif //ifndef F1_BOARD `endif // endif PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC + `endif // endif POLARA_LOOPBACK `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index f64f15be7..d86c1c5c1 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -9,253 +9,175 @@ module chipset_impl_polara_loopback( // Clocks and resets - input chipset_clk, - input chipset_rst_n, - - // Misc - output test_start, + input chipset_clk, + input chipset_rst_n, // Main chip interface - output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, - output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, - output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3, - output chipset_intf_val_noc1, - output chipset_intf_val_noc2, - output chipset_intf_val_noc3, - input chipset_intf_rdy_noc1, - input chipset_intf_rdy_noc2, - input chipset_intf_rdy_noc3, - - input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, - input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, - input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3, - input intf_chipset_val_noc1, - input intf_chipset_val_noc2, - input intf_chipset_val_noc3, - output intf_chipset_rdy_noc1, - output intf_chipset_rdy_noc2, - output intf_chipset_rdy_noc3 - + output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, + output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, + output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3, + output chipset_intf_val_noc1, + output chipset_intf_val_noc2, + output chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, + + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3, + input intf_chipset_val_noc1, + input intf_chipset_val_noc2, + input intf_chipset_val_noc3, + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3, + + // Chip and other BD signals + input mc_clk, // not sure if needed + input mig_ddr3_sys_se_clock_clk, + output chip_async_mux, + output chip_clk_en, + output chip_clk_mux_sel, + output chip_rst_n, + output init_calib_complete, + output test_start, + + // FLL + input fll_clkdiv, + input fll_lock, + output fll_bypass, + output fll_cfg_req, + output fll_opmode, + output [3:0] fll_range, + output fll_rst_n, + // Just dummy signals -`ifdef PITONSYS_IOCTRL -`ifdef PITONSYS_UART - , - output uart_tx, - input uart_rx -`endif // endif PITONSYS_UART -`endif // endif PITONSYS_IOCTRL + output uart_tx, + input uart_rx, + input uart_boot_en, + input uart_timeout_en ); /////////////////////// // Type declarations // /////////////////////// -// NoC power message header -// CHIPID: 14'd0 -// XPOS: variable, depends on number of hops -// YPOS: variable, depends on number of hops +// ///////////////////////////////////////////////////////////////// +// NoC message for polara loopback +// CHIPID: 14'd1 +// XPOS: 8'd0 +// YPOS: 8'd0 // FBITS: 4'd0 -// PAYLOAD LENGTH: 8'd6 // Max accepted by L1.5 +// PAYLOAD LENGTH: 8'd0 // MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations // MSHR/TAG: 8'd0 // RESERVED: 6'd0 -parameter MSG_HEADER = {14'd0, 8'd0, 8'd0, 4'd0, 8'd6, - `MSG_TYPE_INV_FWD, 8'd0, 6'd0}; - -parameter STATE_RESET = 2'd0; -parameter STATE_SEND_HEADER = 2'd1; -parameter STATE_SEND_DATA_PATTERN_A = 2'd2; -parameter STATE_SEND_DATA_PATTERN_B = 2'd3; - -reg rst_n; - -reg [1:0] state_f; -reg [1:0] state_next; +// ///////////////////////////////////////////////////////////////// -reg [7:0] payload_count_f; -reg [7:0] payload_count_next; + wire [1:0] polara_gen2chipset_bus_i; + wire [11:0] polara_gen2chipset_bus_o; + wire chip_rst_n_inter; -reg [`NOC_DATA_WIDTH-1:0] out_data; + parameter STATE_RESET = 2'b00; + parameter STATE_SEND = 2'b01; + parameter STATE_WAIT = 2'b10; + reg [1:0] CurrentState, NextState; + + wire [`NOC_DATA_WIDTH-1:0] out_data; + + ////////////////////// // Sequential Logic // ////////////////////// -always @ (posedge chipset_clk) -begin - if (~rst_n) - begin - state_f <= STATE_RESET; - payload_count_f <= 8'd0; - end - else - begin - state_f <= state_next; - payload_count_f <= payload_count_next; - end -end // always @ (posedge chipset_clk) - + always @ (posedge chipset_clk) + begin: SEQ + if (~chip_rst_n_inter) + begin + CurrentState <= STATE_RESET; + end + else + begin + CurrentState <= NextState; + end + end + ///////////////////////// // Combinational Logic // ///////////////////////// -`ifdef PITONSYS_IOCTRL -`ifdef PITONSYS_UART - assign uart_tx = 1'b0; -`endif // endif PITONSYS_UART -`endif // endif PITONSYS_IOCTRL - -// State machine -always @ * -begin - state_next = state_f; - payload_count_next = payload_count_f; - - case (state_f) - STATE_RESET: - begin - state_next = STATE_SEND_HEADER; - end - STATE_SEND_HEADER: - begin - if (chipset_intf_rdy_noc2) - state_next = STATE_SEND_DATA_PATTERN_A; - end - STATE_SEND_DATA_PATTERN_A: - begin - if (chipset_intf_rdy_noc2) + // Output data + assign out_data = {14'd1, 8'd0, 8'd0, 4'd0, 8'd0, `MSG_TYPE_INV_FWD, 8'd0, 6'd0}; + + // State machine + always @ (*) + begin: COMB + case (CurrentState) + STATE_RESET: begin - if (payload_count_f == 8'd5) - begin - state_next = STATE_SEND_HEADER; - payload_count_next = 8'd0; - end - else - begin - state_next = STATE_SEND_DATA_PATTERN_B; - payload_count_next = payload_count_f + 1'b1; - end - end - end - STATE_SEND_DATA_PATTERN_B: - begin - if (chipset_intf_rdy_noc2) + if (chip_rst_n_inter) + begin + NextState = STATE_SEND; + end + else + begin + NextState = STATE_RESET; + end + end // case: STATE_RESET + STATE_SEND: begin - if (payload_count_f == 8'd5) - begin - state_next = STATE_SEND_HEADER; - payload_count_next = 8'd0; - end - else - begin - state_next = STATE_SEND_DATA_PATTERN_A; - payload_count_next = payload_count_f + 1'b1; - end + if (chipset_intf_rdy_noc2) + begin + NextState = STATE_WAIT; + end end - end - endcase -end // always @ * - -// Out data generation -always @ * -begin - out_data = {`NOC_DATA_WIDTH{1'bx}}; - - case (state_f) - STATE_RESET: - begin - out_data = {`NOC_DATA_WIDTH{1'bx}}; - end - STATE_SEND_HEADER: - begin - out_data = MSG_HEADER; - case (noc_power_test_hop_count) - 4'd0: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd0; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; - end - 4'd1: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd1; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; - end - 4'd2: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd2; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; - end - 4'd3: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd3; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; - end - 4'd4: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd0; - end - 4'd5: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd1; - end - 4'd6: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd2; - end - 4'd7: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd3; - end - 4'd8: - begin - out_data[`MSG_DST_X] = `MSG_DST_X_WIDTH'd4; - out_data[`MSG_DST_Y] = `MSG_DST_Y_WIDTH'd4; - end - endcase - end - STATE_SEND_DATA_PATTERN_A: - begin -`ifdef NOC_POWER_TEST_0xA_0x5_PATTERN - out_data = {`NOC_DATA_WIDTH/2{2'b01}}; -`elsif NOC_POWER_TEST_0x0_0x0_PATTERN - out_data = {`NOC_DATA_WIDTH{1'b0}}; -`elsif NOC_POWER_TEST_0x0_0x3_PATTERN - out_data = {`NOC_DATA_WIDTH/4{4'b0011}}; -`else - out_data = {`NOC_DATA_WIDTH{1'b1}}; -`endif // endif NOC_POWER_TEST_0xA_0x5_PATTERN - end - STATE_SEND_DATA_PATTERN_B: - begin -`ifdef NOC_POWER_TEST_0xA_0x5_PATTERN - out_data = {`NOC_DATA_WIDTH/2{2'b10}}; -`elsif NOC_POWER_TEST_0x0_0x0_PATTERN - out_data = {`NOC_DATA_WIDTH{1'b0}}; -`elsif NOC_POWER_TEST_0x0_0x3_PATTERN - out_data = {`NOC_DATA_WIDTH{1'b0}}; -`else - out_data = {`NOC_DATA_WIDTH{1'b0}}; -`endif // endif NOC_POWER_TEST_0xA_0x5_PATTERN - end - endcase -end - -assign test_start = 1'b1; + default: // STATE_WAIT + begin + NextState = STATE_WAIT; + end + endcase // case (CurrentState) + end + + + // Instantiate the block design + gen2_polara_fpga_loopback gen2_polara_fpga_i + (.bd_clk(chipset_clk), + .mig_ddr3_sys_rst_n(chipset_rst_n), + .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), + .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o)); + + // Route polara_gen2chipset_bus signals + assign chip_rst_n = chip_rst_n_inter; + assign chip_rst_n_inter = polara_gen2chipset_bus_o[0]; + assign chip_async_mux = polara_gen2chipset_bus_o[1]; + assign chip_clk_en = polara_gen2chipset_bus_o[2]; + assign chip_clk_mux_sel = polara_gen2chipset_bus_o[3]; + + assign fll_rst_n = polara_gen2chipset_bus_o[4]; + assign fll_bypass = polara_gen2chipset_bus_o[5]; + assign fll_opmode = polara_gen2chipset_bus_o[6]; + assign fll_cfg_req = polara_gen2chipset_bus_o[7]; + + assign fll_range[3:0] = polara_gen2chipset_bus_o[11:8]; + + assign polara_gen2chipset_bus_i[0] = fll_lock; + assign polara_gen2chipset_bus_i[1] = fll_clkdiv; -assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; -assign chipset_intf_data_noc2 = out_data; -assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; + // Assign network I/Os + assign test_start = 1'b1; -assign chipset_intf_val_noc1 = 1'b0; -assign chipset_intf_val_noc2 = (state_f != STATE_RESET); -assign chipset_intf_val_noc3 = 1'b0; + assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; + assign chipset_intf_data_noc2 = out_data; + assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; -assign intf_chipset_rdy_noc1 = 1'b0; -assign intf_chipset_rdy_noc2 = 1'b0; -assign intf_chipset_rdy_noc3 = 1'b0; + assign chipset_intf_val_noc1 = 1'b0; + assign chipset_intf_val_noc2 = (CurrentState != STATE_RESET); + assign chipset_intf_val_noc3 = 1'b0; + assign intf_chipset_rdy_noc1 = 1'b0; + assign intf_chipset_rdy_noc2 = 1'b0; + assign intf_chipset_rdy_noc3 = 1'b0; + endmodule From 5d25839f3d811ea26c8f0adf0ee3e2d86f39706b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Wed, 21 Aug 2024 18:09:48 -0400 Subject: [PATCH 121/144] Modified files to include loopback module in flow. --poloopback option to test Polara in loopback. --- .../ip_cores/atg_uart_init/atg_uart_init.xci | 28 +-- .../ip_cores/uart_16550/uart_16550.xci | 28 +-- .../chipset/xilinx/genesys2/constraints.xdc | 184 ++++++++++-------- piton/tools/src/proto/common/rtl_setup.tcl | 1 + piton/tools/src/proto/genesys2/board.tcl | 13 +- .../genesys2/gen2_polara_fpga_loopback.tcl | 114 ++--------- 6 files changed, 152 insertions(+), 216 deletions(-) diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci index 015a1fe2e..e3f12e2ae 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci @@ -326,7 +326,7 @@ atg_uart_init_ctrl.mem atg_uart_init_data.mem atg_uart_init_mask.mem - 00000000000000000000000000000001 + "00000000000000000000000000000001" 0 5000 1 @@ -631,19 +631,19 @@ +ion":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_lite_ch1_wstrb":[{"direction":"out","physical_left":"3","physical_right":"0","is_vector":"true"}],"m_axi_lite_ch1_wvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"status":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}]},"interfaces":{"M_AXI_LITE_CH1":{"vlnv":"xilinx.com:interface:aximm:1.0","abstraction_type":"xilinx.com:interface:aximm_rtl:1.0","mode":"master","address_space_ref":"Reg1","parameters":{"ADDR_WIDTH":[{"value":"32","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":false,"is_static_object":false}],"ARUSER_WIDTH":[{"value":"0","value_src":"constant","value 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+"value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"BAUDOUTn":[{"physical_name":"baudoutn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CTSn":[{"physical_name":"ctsn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"DCDn":[{"physical_name":"dcdn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"DDIS":[{"physical_name":"ddis","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"DSRn":[{"physical_name":"dsrn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"DTRn":[{"physical_name":"dtrn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used": +"none"}],"OUT1n":[{"physical_name":"out1n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"OUT2n":[{"physical_name":"out2n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RCLK":[{"physical_name":"rclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RI":[{"physical_name":"rin","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RTSn":[{"physical_name":"rtsn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RXRDYn":[{"physical_name":"rxrdyn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RxD":[{"physical_name":"sin","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TXRDYn":[{"physical_ +name":"txrdyn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TxD":[{"physical_name":"sout","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"XIN":[{"physical_name":"xin","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"XOUT":[{"physical_name":"xout","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"memory_maps":{"S_AXI":{"address_blocks":{"Reg":[{"base_address":"0","range":"65536","display_name":"Reg","description":"RegisterBlock","usage":"register","access":"read-write"}]}}}}}"/> diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 6a7ec19f4..f9ef63659 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -64,12 +64,12 @@ create_clock -period 25.000 -name core_ref_clk -waveform {0.000 12.500} [get_por # Constraint RGMII interface -create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] -set_output_delay -clock txc_gen 2.000 [get_ports net_phy_txctl] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[0]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[1]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[2]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[3]}] +#create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] +#set_output_delay -clock txc_gen 2.000 [get_ports net_phy_txctl] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[0]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[1]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[2]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[3]}] # Reset set_property IOSTANDARD LVCMOS33 [get_ports rst_n] @@ -186,37 +186,37 @@ set_property IOSTANDARD LVCMOS18 [get_ports btnu] # NOTUSED? set_property PACKAGE_PIN AK16 [get_ports net_ip2intc_irpt] # NOTUSED? set_property IOSTANDARD LVCMOS18 [get_ports net_ip2intc_irpt] # NOTUSED? set_property PULLUP true [get_ports net_ip2intc_irpt] -set_property PACKAGE_PIN AF12 [get_ports net_phy_mdc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdc] -set_property PACKAGE_PIN AG12 [get_ports net_phy_mdio_io] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdio_io] -set_property PACKAGE_PIN AH24 [get_ports net_phy_rst_n] -set_property IOSTANDARD LVCMOS33 [get_ports net_phy_rst_n] +#set_property PACKAGE_PIN AF12 [get_ports net_phy_mdc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdc] +#set_property PACKAGE_PIN AG12 [get_ports net_phy_mdio_io] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdio_io] +#set_property PACKAGE_PIN AH24 [get_ports net_phy_rst_n] +#set_property IOSTANDARD LVCMOS33 [get_ports net_phy_rst_n] #set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { ETH_PMEB }]; #IO_L1N_T0_32 Sch=eth_pmeb -set_property PACKAGE_PIN AG10 [get_ports net_phy_rxc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxc] -set_property PACKAGE_PIN AH11 [get_ports net_phy_rxctl] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxctl] -set_property PACKAGE_PIN AJ14 [get_ports {net_phy_rxd[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[0]}] -set_property PACKAGE_PIN AH14 [get_ports {net_phy_rxd[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[1]}] -set_property PACKAGE_PIN AK13 [get_ports {net_phy_rxd[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[2]}] -set_property PACKAGE_PIN AJ13 [get_ports {net_phy_rxd[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[3]}] -set_property PACKAGE_PIN AE10 [get_ports net_phy_txc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txc] -set_property PACKAGE_PIN AJ12 [get_ports {net_phy_txd[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[0]}] -set_property PACKAGE_PIN AK11 [get_ports {net_phy_txd[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[1]}] -set_property PACKAGE_PIN AJ11 [get_ports {net_phy_txd[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[2]}] -set_property PACKAGE_PIN AK10 [get_ports {net_phy_txd[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[3]}] -set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] +#set_property PACKAGE_PIN AG10 [get_ports net_phy_rxc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxc] +#set_property PACKAGE_PIN AH11 [get_ports net_phy_rxctl] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxctl] +#set_property PACKAGE_PIN AJ14 [get_ports {net_phy_rxd[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[0]}] +#set_property PACKAGE_PIN AH14 [get_ports {net_phy_rxd[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[1]}] +#set_property PACKAGE_PIN AK13 [get_ports {net_phy_rxd[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[2]}] +#set_property PACKAGE_PIN AJ13 [get_ports {net_phy_rxd[3]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[3]}] +#set_property PACKAGE_PIN AE10 [get_ports net_phy_txc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txc] +#set_property PACKAGE_PIN AJ12 [get_ports {net_phy_txd[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[0]}] +#set_property PACKAGE_PIN AK11 [get_ports {net_phy_txd[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[1]}] +#set_property PACKAGE_PIN AJ11 [get_ports {net_phy_txd[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[2]}] +#set_property PACKAGE_PIN AK10 [get_ports {net_phy_txd[3]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[3]}] +#set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] # FMC Clocks #set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_n] @@ -732,8 +732,8 @@ set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_c #set_false_path -from [get_clocks core_ref_clk_clk_mmcm_1] -to [get_clocks clk_pll_i_1] #set_property LOC ILOGIC_X1Y119 [get_cells {chipset_impl/mc_top/mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det/u_phase_detector}] -set_property PACKAGE_PIN AG2 [get_ports {ddr_dqs_p[2]}] -set_property PACKAGE_PIN AH1 [get_ports {ddr_dqs_n[2]}] +#set_property PACKAGE_PIN AG2 [get_ports {ddr_dqs_p[2]}] +#set_property PACKAGE_PIN AH1 [get_ports {ddr_dqs_n[2]}] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] @@ -773,6 +773,8 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +connect_debug_port dbg_hub/clk [get_nets clk] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] @@ -783,171 +785,183 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/mc_sys_clk]] +connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 64 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 2 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 3 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 1 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[0]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {chipset_impl/polara_gen2chipset_bus_o_tri_o[0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 1 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[1]_i_1__0_n_0}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/CurrentState[0]} {chipset_impl/CurrentState[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[2]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[0]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list io_clk_OBUF]] +connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[1]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] +connect_debug_port u_ila_0/probe7 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[2]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] +connect_debug_port u_ila_0/probe8 [get_nets [list io_clk_OBUF]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] +connect_debug_port u_ila_0/probe9 [get_nets [list offchip_processor_noc2_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +connect_debug_port u_ila_0/probe40 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] +set_property port_width 1 [get_debug_ports u_ila_0/probe41] +connect_debug_port u_ila_0/probe41 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] +set_property port_width 1 [get_debug_ports u_ila_0/probe42] +connect_debug_port u_ila_0/probe42 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] +set_property port_width 1 [get_debug_ports u_ila_0/probe43] +connect_debug_port u_ila_0/probe43 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets clk] +connect_debug_port dbg_hub/clk [get_nets dbg2_OBUF] diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index b17359664..d8f8658d3 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -778,6 +778,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv"\ + "${DV_ROOT}/design/chipset/rtl/polara_loopback.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ diff --git a/piton/tools/src/proto/genesys2/board.tcl b/piton/tools/src/proto/genesys2/board.tcl index a69f89002..f20ebb585 100644 --- a/piton/tools/src/proto/genesys2/board.tcl +++ b/piton/tools/src/proto/genesys2/board.tcl @@ -33,8 +33,17 @@ set FPGA_PART "xc7k325tffg900-2" set VIVADO_FLOW_PERF_OPT 0 set BOARD_DEFAULT_VERILOG_MACROS "GENESYS2_BOARD" -# Single ended clock (for MIG input clock) has a specific block design -if { [ info exists ::env(POLARA_GEN2_CHIPSETSE) ] } { +# First check if we are doing loopback test +if { [ info exists ::env(POLARA_LOOPBACK) ] } { + # Create a block design containing a JTAG-AXI master using the FPGA_PART variable + # It will produce the "gen2_polara_fpga.bd" file + + source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga_loopback.tcl + + # Grab the file from where the above tcl script has placed it + set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga_loopback/gen2_polara_fpga_loopback] +} elseif { [ info exists ::env(POLARA_GEN2_CHIPSETSE) ] } { + # Single ended clock (for MIG input clock) has a specific block design # Create a block design containing a JTAG-AXI master using the FPGA_PART variable # It will produce the "gen2_polara_fpga.bd" file diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl index 241101f6f..cb283f084 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl @@ -17,19 +17,6 @@ proc get_script_folder {} { variable script_folder set script_folder [_tcl::get_script_folder] -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2021.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - ################################################################ # START ################################################################ @@ -41,16 +28,25 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # project, but make sure you do not have an existing project # <./myproj/project_1.xpr> in the current working folder. +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/genesys2/bd_gen2 +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + set list_projs [get_projects -quiet] if { $list_projs eq "" } { - create_project project_1 myproj -part xc7k325tffg900-2 + create_project -force ${tmp_build_dir}/${tmp_prj} -part xc7k325tffg900-2 + # create_project project_1 myproj -part xc7k325tffg900-2 set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] } # CHANGE DESIGN NAME HERE variable design_name -set design_name gen2_polara_fpga +set design_name gen2_polara_fpga_loopback # If you do not already have an existing IP Integrator design open, # you can create a design using the following command: @@ -63,95 +59,11 @@ set nRet 0 set cur_design [current_bd_design -quiet] set list_cells [get_bd_cells -quiet] -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/genesys2 +current_bd_design $design_name common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_gpio:2.0\ -xilinx.com:ip:jtag_axi:1.2\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:smartconnect:1.0\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - ################################################################## # DESIGN PROCs ################################################################## From 1be197f533b8f9256272a8dd5694b509e2e68d1a Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 22 Aug 2024 08:46:50 -0400 Subject: [PATCH 122/144] Added option --poloopback to protoysyn. --- piton/tools/src/proto/protosyn,2.5 | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 344d07998..06716e125 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -155,8 +155,10 @@ def usage(): print("\n --se", file=sys.stderr) print(" Sets POLARA_GEN2_CHIPSETSE define.", file=sys.stderr) print(" Assumes genesys2 board is chosen", file=sys.stderr) - print("\n --noctest", file=sys.stderr) + print("\n --nocpowertest", file=sys.stderr) print(" Sets PITON_NOC_POWER_CHIPSET_TEST define.", file=sys.stderr) + print("\n --poloopback", file=sys.stderr) + print(" Sets POLARA_LOOPBACK define.", file=sys.stderr) print(" To generate packets to test Polara's NOC.", file=sys.stderr) print("\n -h, --help", file=sys.stderr) print(" Display this help message and exit", file=sys.stderr) @@ -513,7 +515,8 @@ def setParserOptions(parser): parser.add_option("--vc707chipset", dest="polara_vc707_chipset_flag", action="store_true", default=False) parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) parser.add_option("--se", dest="se", action="store_true", default=False) - parser.add_option("--noctest", dest="noctest", action="store_true", default=False) + parser.add_option("--nocpowertest", dest="noctest", action="store_true", default=False) + parser.add_option("--poloopback", dest="poloopback", action="store_true", default=False) return parser @@ -678,13 +681,21 @@ def makeDefList(options): # Set environnment variable os.environ["POLARA_GEN2_CHIPSETSE"] = "1" - # --noctest option + # --nocpowertest option if options.noctest == True: # Set RTL define defines.append("PITON_NOC_POWER_CHIPSET_TEST") # Set environnment variable os.environ["PITON_NOC_POWER_CHIPSET_TEST"] = "1" + # --poloopback option + if options.poloopback == True: + print("poloopback option chosen") + # Set RTL define + defines.append("POLARA_LOOPBACK") + # Set environnment variable + os.environ["POLARA_LOOPBACK"] = "1" + return defines def makeMemMapping(st_brd, work_dir, log_dir): From 5f1f14bc03c84f0eb44e451e8b4c47fb9c38dd8b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Thu, 22 Aug 2024 08:58:19 -0400 Subject: [PATCH 123/144] Commenting unused ports for constraints --- .../chipset/xilinx/genesys2/constraints.xdc | 72 +++++++++---------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 6a7ec19f4..f3e76ff53 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -64,12 +64,12 @@ create_clock -period 25.000 -name core_ref_clk -waveform {0.000 12.500} [get_por # Constraint RGMII interface -create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] -set_output_delay -clock txc_gen 2.000 [get_ports net_phy_txctl] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[0]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[1]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[2]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[3]}] +#create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] +#set_output_delay -clock txc_gen 2.000 [get_ports net_phy_txctl] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[0]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[1]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[2]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[3]}] # Reset set_property IOSTANDARD LVCMOS33 [get_ports rst_n] @@ -186,37 +186,37 @@ set_property IOSTANDARD LVCMOS18 [get_ports btnu] # NOTUSED? set_property PACKAGE_PIN AK16 [get_ports net_ip2intc_irpt] # NOTUSED? set_property IOSTANDARD LVCMOS18 [get_ports net_ip2intc_irpt] # NOTUSED? set_property PULLUP true [get_ports net_ip2intc_irpt] -set_property PACKAGE_PIN AF12 [get_ports net_phy_mdc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdc] -set_property PACKAGE_PIN AG12 [get_ports net_phy_mdio_io] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdio_io] -set_property PACKAGE_PIN AH24 [get_ports net_phy_rst_n] -set_property IOSTANDARD LVCMOS33 [get_ports net_phy_rst_n] +#set_property PACKAGE_PIN AF12 [get_ports net_phy_mdc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdc] +#set_property PACKAGE_PIN AG12 [get_ports net_phy_mdio_io] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdio_io] +#set_property PACKAGE_PIN AH24 [get_ports net_phy_rst_n] +#set_property IOSTANDARD LVCMOS33 [get_ports net_phy_rst_n] #set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { ETH_PMEB }]; #IO_L1N_T0_32 Sch=eth_pmeb -set_property PACKAGE_PIN AG10 [get_ports net_phy_rxc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxc] -set_property PACKAGE_PIN AH11 [get_ports net_phy_rxctl] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxctl] -set_property PACKAGE_PIN AJ14 [get_ports {net_phy_rxd[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[0]}] -set_property PACKAGE_PIN AH14 [get_ports {net_phy_rxd[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[1]}] -set_property PACKAGE_PIN AK13 [get_ports {net_phy_rxd[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[2]}] -set_property PACKAGE_PIN AJ13 [get_ports {net_phy_rxd[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[3]}] -set_property PACKAGE_PIN AE10 [get_ports net_phy_txc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txc] -set_property PACKAGE_PIN AJ12 [get_ports {net_phy_txd[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[0]}] -set_property PACKAGE_PIN AK11 [get_ports {net_phy_txd[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[1]}] -set_property PACKAGE_PIN AJ11 [get_ports {net_phy_txd[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[2]}] -set_property PACKAGE_PIN AK10 [get_ports {net_phy_txd[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[3]}] -set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] +#set_property PACKAGE_PIN AG10 [get_ports net_phy_rxc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxc] +#set_property PACKAGE_PIN AH11 [get_ports net_phy_rxctl] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxctl] +#set_property PACKAGE_PIN AJ14 [get_ports {net_phy_rxd[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[0]}] +#set_property PACKAGE_PIN AH14 [get_ports {net_phy_rxd[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[1]}] +#set_property PACKAGE_PIN AK13 [get_ports {net_phy_rxd[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[2]}] +#set_property PACKAGE_PIN AJ13 [get_ports {net_phy_rxd[3]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[3]}] +#set_property PACKAGE_PIN AE10 [get_ports net_phy_txc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txc] +#set_property PACKAGE_PIN AJ12 [get_ports {net_phy_txd[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[0]}] +#set_property PACKAGE_PIN AK11 [get_ports {net_phy_txd[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[1]}] +#set_property PACKAGE_PIN AJ11 [get_ports {net_phy_txd[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[2]}] +#set_property PACKAGE_PIN AK10 [get_ports {net_phy_txd[3]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[3]}] +#set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] # FMC Clocks #set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_n] From 4a62a1e30ec1c0f2785a9c1e8c493a4afdfac35a Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 23 Aug 2024 15:31:53 -0400 Subject: [PATCH 124/144] Corrected chipID in order to get bounceback and FBITS adjusted to west which is the asic's input port. --- piton/design/chipset/rtl/polara_loopback.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index d86c1c5c1..0b9dae9d7 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -65,12 +65,12 @@ module chipset_impl_polara_loopback( // ///////////////////////////////////////////////////////////////// // NoC message for polara loopback -// CHIPID: 14'd1 +// CHIPID: 14'b10000000000000 // XPOS: 8'd0 // YPOS: 8'd0 -// FBITS: 4'd0 +// FBITS: 4'b0010 // PAYLOAD LENGTH: 8'd0 -// MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations +// MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations 8'd18=8'b00010010 // MSHR/TAG: 8'd0 // RESERVED: 6'd0 // ///////////////////////////////////////////////////////////////// @@ -109,7 +109,7 @@ module chipset_impl_polara_loopback( ///////////////////////// // Output data - assign out_data = {14'd1, 8'd0, 8'd0, 4'd0, 8'd0, `MSG_TYPE_INV_FWD, 8'd0, 6'd0}; + assign out_data = {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, `MSG_TYPE_INV_FWD, 8'd0, 6'd0}; // State machine always @ (*) From 884a59a9c164bfda9101aa0e58f6f174dcabf041 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 16 Sep 2024 12:33:17 -0400 Subject: [PATCH 125/144] Initial revision. --- piton/design/chipset/rtl/polara_debouncer.sv | 129 +++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 piton/design/chipset/rtl/polara_debouncer.sv diff --git a/piton/design/chipset/rtl/polara_debouncer.sv b/piton/design/chipset/rtl/polara_debouncer.sv new file mode 100644 index 000000000..152ae10e3 --- /dev/null +++ b/piton/design/chipset/rtl/polara_debouncer.sv @@ -0,0 +1,129 @@ +// Debouncer module to use for the switches in the Polara loopback chipset. +// Taken from: https://github.com/iammituraj/debouncer/blob/main/debouncer.sv +// N_BOUNCE = ceil(log_2(T_bounce / T_clk)) +// For T_bounce = 10ms and T_clk = 40MHz, this gives N_BOUNCE = 19 +/*=============================================================================================================================== + Module : Debouncer + + Description : Debouncer is used to filter bouncing found in typical switches and provide a clean, glitch-free state change. + -- Configurable bouncing interval in powers of 2 (threshold). + -- Changes state at the output based on counting the no. of times the same input is sampled consecutively. + Switch state transition appears at output only if the count crosses the threshold. + -- Debounces both assertion and release of switches. + -- Supports both pull-up and pull-down switch inputs. + -- Debouncer is designed to debounce switches with pull-down (OFF state = '0', ON state = '1'). + For pull-up switches (OFF state = '1', ON state = '0'), debounced signal should be treated as valid + only after one bouncing interval latency after reset. Because on reset, debounced signal + drives '0' by default, which is ON state for pull-up switch. This may be undesirable. + If the initial latency is undesired, IS_PULLUP parameter can be set. + + Developer : Mitu Raj, chip@chipmunklogic.com at Chipmunk Logic ™, https://chipmunklogic.com + Notes : Fully synthesisable, portable and tested code. + < 10 MHz clock is recommended for minimal resource usage assuming < 10 ms as switch bouncing time. + License : Open-source. + Date : Nov-09-2021 +===============================================================================================================================*/ + +/*------------------------------------------------------------------------------------------------------------------------------- + D E B O U N C E R +-------------------------------------------------------------------------------------------------------------------------------*/ + +module debouncer #( + + // Global Parameters + parameter N_BOUNCE = 19 , // Bouncing interval in clock cycles = 2^N_BOUNCE + parameter IS_PULLUP = 0 // Optional: '1' for pull-up switch, '0' for pull-down switch + +) + +( + input logic clk , // Clock + input logic rstn , // Active-low synchronous reset + input logic i_sig , // Bouncing signal from switch + output logic o_sig_debounced // Debounced signal +) ; + + +/*------------------------------------------------------------------------------------------------------------------------------- + Internal Registers/Signals +-------------------------------------------------------------------------------------------------------------------------------*/ +logic isig_rg, isig_sync_rg ; // Registers in 2FF Synchronizer +logic sig_rg, sig_d_rg, sig_debounced_rg ; // Registers for switch's state +logic [N_BOUNCE : 0] counter_rg ; // Counter +logic [N_BOUNCE : 0] nxt_cnt ; // Next count + + +/*------------------------------------------------------------------------------------------------------------------------------- + Synchronous logic for debouncing +-------------------------------------------------------------------------------------------------------------------------------*/ +always @(posedge clk) begin + + // Reset + if (!rstn) begin + + // Internal Registers + sig_rg <= IS_PULLUP ; + sig_d_rg <= IS_PULLUP ; + sig_debounced_rg <= IS_PULLUP ; + counter_rg <= 1 ; + + end + + // Out of reset + else begin + + // Register state of switch + sig_rg <= isig_sync_rg ; + sig_d_rg <= sig_rg ; + + // Increment counter if two consecutive states are same, otherwise reset + counter_rg <= (sig_d_rg == sig_rg) ? nxt_cnt : 1 ; + + // Counter overflow, valid state registered + if (counter_rg [N_BOUNCE]) begin + sig_debounced_rg <= sig_d_rg ; + end + + end + +end + +assign nxt_cnt = (counter_rg [N_BOUNCE])? counter_rg : (counter_rg + 1) ; + + +/*------------------------------------------------------------------------------------------------------------------------------- + 2FF Synchronizer +-------------------------------------------------------------------------------------------------------------------------------*/ +always @(posedge clk) begin + + // Reset + if (!rstn) begin + + // Internal Registers + isig_rg <= IS_PULLUP ; + isig_sync_rg <= IS_PULLUP ; + + end + + // Out of reset + else begin + + isig_rg <= i_sig ; // Metastable flop + isig_sync_rg <= isig_rg ; // Synchronizing flop + + end + +end + + +/*------------------------------------------------------------------------------------------------------------------------------- + Continuous Assignments +-------------------------------------------------------------------------------------------------------------------------------*/ +assign o_sig_debounced = sig_debounced_rg ; + + +endmodule + +/*------------------------------------------------------------------------------------------------------------------------------- + D E B O U N C E R +-------------------------------------------------------------------------------------------------------------------------------*/ From dbb80cb6515fe9ef73ecb27e0d510abb65a7eedd Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 16 Sep 2024 12:34:20 -0400 Subject: [PATCH 126/144] Now using switches 1 and 0 to control what channel the loopback module sends packets on. --- piton/design/chipset/rtl/chipset.v | 3 ++ piton/design/chipset/rtl/polara_loopback.v | 63 ++++++++++++++++++---- piton/tools/src/proto/common/rtl_setup.tcl | 3 +- 3 files changed, 59 insertions(+), 10 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index b7c3279aa..76bff5149 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1343,6 +1343,9 @@ chipset_impl_noc_power_test chipset_impl ( `ifndef POLARA_LOOPBACK .uart_rst_out_n (uart_rst_out_n ), .invalid_access_o (invalid_access ), +`else // ifndef POLARA_LOOPBACK + .sw_channel_msb(sw[1]), + .sw_channel_lsb(sw[0]), `endif // ifndef POLARA_LOOPBACK `endif diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index 0b9dae9d7..18883b468 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -12,13 +12,17 @@ module chipset_impl_polara_loopback( input chipset_clk, input chipset_rst_n, + // Switches + input sw_channel_msb, + input sw_channel_lsb, + // Main chip interface - output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, - output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, - output [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3, - output chipset_intf_val_noc1, - output chipset_intf_val_noc2, - output chipset_intf_val_noc3, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3, + output reg chipset_intf_val_noc1, + output reg chipset_intf_val_noc2, + output reg chipset_intf_val_noc3, input chipset_intf_rdy_noc1, input chipset_intf_rdy_noc2, input chipset_intf_rdy_noc3, @@ -85,8 +89,11 @@ module chipset_impl_polara_loopback( reg [1:0] CurrentState, NextState; - wire [`NOC_DATA_WIDTH-1:0] out_data; + wire [`NOC_DATA_WIDTH-1:0] out_data; + wire sw_msb_debounced; + wire sw_lsb_debounced; + wire [1:0] sw_debounced; ////////////////////// // Sequential Logic // @@ -132,6 +139,10 @@ module chipset_impl_polara_loopback( begin NextState = STATE_WAIT; end + else + begin + NextState = STATE_SEND; + end end default: // STATE_WAIT begin @@ -148,6 +159,21 @@ module chipset_impl_polara_loopback( .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o)); + // Instantiate debouncers for the 2 channel switches + debouncer debouncer_sw_msb( + .clk(chipset_clk), + .rstn(chipset_rst_n), + .i_sig(sw_channel_msb), + .o_sig_debounced(sw_msb_debounced)); + debouncer debouncer_sw_lsb( + .clk(chipset_clk), + .rstn(chipset_rst_n), + .i_sig(sw_channel_lsb), + .o_sig_debounced(sw_lsb_debounced)); + assign sw_debounced = {sw_msb_debounced, sw_lsb_debounced}; + + + // Route polara_gen2chipset_bus signals assign chip_rst_n = chip_rst_n_inter; assign chip_rst_n_inter = polara_gen2chipset_bus_o[0]; @@ -165,9 +191,28 @@ module chipset_impl_polara_loopback( assign polara_gen2chipset_bus_i[0] = fll_lock; assign polara_gen2chipset_bus_i[1] = fll_clkdiv; + // Demuxes to route data and valid signals + always @(*) begin : DATA_DEMUX + case(sw_debounced) + 2'h1: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = {out_data, {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}} }; + 2'h2: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {`NOC_DATA_WIDTH{1'bx}}, out_data, {`NOC_DATA_WIDTH{1'bx}} }; + 2'h3: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}}, out_data}; + default: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}} }; + endcase + end + + always @(*) begin : VALID_DEMUX + case(sw_debounced) + 2'h1: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = {(CurrentState != STATE_RESET), 1'b0, 1'b0 }; + 2'h2: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, (CurrentState != STATE_RESET), 1'b0 }; + 2'h3: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, (CurrentState != STATE_RESET) }; + default: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, 1'b0 }; + endcase + end + // Assign network I/Os assign test_start = 1'b1; - +/* assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; assign chipset_intf_data_noc2 = out_data; assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; @@ -175,7 +220,7 @@ module chipset_impl_polara_loopback( assign chipset_intf_val_noc1 = 1'b0; assign chipset_intf_val_noc2 = (CurrentState != STATE_RESET); assign chipset_intf_val_noc3 = 1'b0; - +*/ assign intf_chipset_rdy_noc1 = 1'b0; assign intf_chipset_rdy_noc2 = 1'b0; assign intf_chipset_rdy_noc3 = 1'b0; diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index d8f8658d3..e19a50f1c 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -778,7 +778,8 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv"\ - "${DV_ROOT}/design/chipset/rtl/polara_loopback.v" \ + "${DV_ROOT}/design/chipset/rtl/polara_debouncer.sv" \ + "${DV_ROOT}/design/chipset/rtl/polara_loopback.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ From 16e767beeed151b457c99c9e4758e2c7eb2e8099 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 16 Sep 2024 13:59:57 -0400 Subject: [PATCH 127/144] Added jtag commands for testing polara ASIC with loopback module. --- .../src/proto/genesys2/jtag_axi_commands.tcl | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl index 2f4b77bad..497ccc055 100644 --- a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -40,6 +40,24 @@ # 1. Reset the core reset_hw_axi [get_hw_axis hw_axi_1] +# #################################################################### +# Loopback flow. We are not using FLL +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_async_mux = 1, chip_clk_en = 1, chip_clk_mux_sel = 1, rst on +create_hw_axi_txn -force cfgrst [get_hw_axis hw_axi_1] -address 40000000 -data {0000000E} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrst] +# 4. cfg take off rst +create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {0000000F} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrstoff] + # #################################################################### # Genesys 2 Memory Test # #################################################################### From 9bd27e9c7628417d3938fa3f22d9992043ac80a5 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 23 Sep 2024 15:28:55 -0400 Subject: [PATCH 128/144] Separated packet generating logic into is own module. --- piton/design/chipset/rtl/polara_loopback.v | 227 ++++++++------------- 1 file changed, 89 insertions(+), 138 deletions(-) diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index 18883b468..3443a1662 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -9,63 +9,71 @@ module chipset_impl_polara_loopback( // Clocks and resets - input chipset_clk, - input chipset_rst_n, + input chipset_clk, + input chipset_rst_n, // Switches - input sw_channel_msb, - input sw_channel_lsb, + input sw_channel_msb, + input sw_channel_lsb, + input sw_march, // Main chip interface + /* output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, - output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3, - output reg chipset_intf_val_noc1, - output reg chipset_intf_val_noc2, - output reg chipset_intf_val_noc3, - input chipset_intf_rdy_noc1, - input chipset_intf_rdy_noc2, - input chipset_intf_rdy_noc3, - - input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, - input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, - input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3, - input intf_chipset_val_noc1, - input intf_chipset_val_noc2, - input intf_chipset_val_noc3, - output intf_chipset_rdy_noc1, - output intf_chipset_rdy_noc2, - output intf_chipset_rdy_noc3, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3,*/ + output reg [64-1:0] chipset_intf_data_noc1, + output reg [64-1:0] chipset_intf_data_noc2, + output reg [64-1:0] chipset_intf_data_noc3, + output reg chipset_intf_val_noc1, + output reg chipset_intf_val_noc2, + output reg chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, + + /*input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3,*/ + input [64-1:0] intf_chipset_data_noc1, + input [64-1:0] intf_chipset_data_noc2, + input [64-1:0] intf_chipset_data_noc3, + input intf_chipset_val_noc1, + input intf_chipset_val_noc2, + input intf_chipset_val_noc3, + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3, // Chip and other BD signals - input mc_clk, // not sure if needed - input mig_ddr3_sys_se_clock_clk, - output chip_async_mux, - output chip_clk_en, - output chip_clk_mux_sel, - output chip_rst_n, - output init_calib_complete, - output test_start, + input mc_clk, // not sure if needed + input mig_ddr3_sys_se_clock_clk, + output chip_async_mux, + output chip_clk_en, + output chip_clk_mux_sel, + output chip_rst_n, + output init_calib_complete, + output test_start, // FLL - input fll_clkdiv, - input fll_lock, - output fll_bypass, - output fll_cfg_req, - output fll_opmode, - output [3:0] fll_range, - output fll_rst_n, + input fll_clkdiv, + input fll_lock, + output fll_bypass, + output fll_cfg_req, + output fll_opmode, + output [3:0] fll_range, + output fll_rst_n, // Just dummy signals - output uart_tx, - input uart_rx, - input uart_boot_en, - input uart_timeout_en + output uart_tx, + input uart_rx, + input uart_boot_en, + input uart_timeout_en ); -/////////////////////// -// Type declarations // -/////////////////////// +// ///////////////////// +// Type declarations // +// ///////////////////// // ///////////////////////////////////////////////////////////////// // NoC message for polara loopback @@ -82,82 +90,47 @@ module chipset_impl_polara_loopback( wire [1:0] polara_gen2chipset_bus_i; wire [11:0] polara_gen2chipset_bus_o; wire chip_rst_n_inter; - - parameter STATE_RESET = 2'b00; - parameter STATE_SEND = 2'b01; - parameter STATE_WAIT = 2'b10; - - reg [1:0] CurrentState, NextState; - - wire [`NOC_DATA_WIDTH-1:0] out_data; - + wire sw_msb_debounced; - wire sw_lsb_debounced; - wire [1:0] sw_debounced; + wire sw_lsb_debounced; + wire [1:0] sw_debounced; + wire sw_march_debounced; ////////////////////// // Sequential Logic // ////////////////////// - - always @ (posedge chipset_clk) - begin: SEQ - if (~chip_rst_n_inter) - begin - CurrentState <= STATE_RESET; - end - else - begin - CurrentState <= NextState; - end - end ///////////////////////// // Combinational Logic // ///////////////////////// - // Output data - assign out_data = {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, `MSG_TYPE_INV_FWD, 8'd0, 6'd0}; - - // State machine - always @ (*) - begin: COMB - case (CurrentState) - STATE_RESET: - begin - if (chip_rst_n_inter) - begin - NextState = STATE_SEND; - end - else - begin - NextState = STATE_RESET; - end - end // case: STATE_RESET - STATE_SEND: - begin - if (chipset_intf_rdy_noc2) - begin - NextState = STATE_WAIT; - end - else - begin - NextState = STATE_SEND; - end - end - default: // STATE_WAIT - begin - NextState = STATE_WAIT; - end - endcase // case (CurrentState) - end - - + // Instantiate the packet generator + polara_loopback_packet_gen packet_gen_i( + .chipset_clk(chipset_clk), + .chip_rst_n(chip_rst_n_inter), + .sw_debounced(sw_debounced), + .march(sw_march_debounced), + .chipset_intf_data_noc1(chipset_intf_data_noc1), + .chipset_intf_data_noc2(chipset_intf_data_noc2), + .chipset_intf_data_noc3(chipset_intf_data_noc3), + .chipset_intf_val_noc1(chipset_intf_val_noc1), + .chipset_intf_val_noc2(chipset_intf_val_noc2), + .chipset_intf_val_noc3(chipset_intf_val_noc3), + .chipset_intf_rdy_noc1(chipset_intf_rdy_noc1), + .chipset_intf_rdy_noc2(chipset_intf_rdy_noc2), + .chipset_intf_rdy_noc3(chipset_intf_rdy_noc3), + .intf_chipset_rdy_noc1(intf_chipset_rdy_noc1), + .intf_chipset_rdy_noc2(intf_chipset_rdy_noc2), + .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) + ); + // Instantiate the block design - gen2_polara_fpga_loopback gen2_polara_fpga_i - (.bd_clk(chipset_clk), - .mig_ddr3_sys_rst_n(chipset_rst_n), - .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), - .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o)); + gen2_polara_fpga_loopback gen2_polara_fpga_i( + .bd_clk(chipset_clk), + .mig_ddr3_sys_rst_n(chipset_rst_n), + .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), + .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o) + ); // Instantiate debouncers for the 2 channel switches debouncer debouncer_sw_msb( @@ -171,6 +144,12 @@ module chipset_impl_polara_loopback( .i_sig(sw_channel_lsb), .o_sig_debounced(sw_lsb_debounced)); assign sw_debounced = {sw_msb_debounced, sw_lsb_debounced}; + + debouncer debouncer_sw_march( + .clk(chipset_clk), + .rstn(chipset_rst_n), + .i_sig(sw_march), + .o_sig_debounced(sw_march_debounced)); @@ -191,38 +170,10 @@ module chipset_impl_polara_loopback( assign polara_gen2chipset_bus_i[0] = fll_lock; assign polara_gen2chipset_bus_i[1] = fll_clkdiv; - // Demuxes to route data and valid signals - always @(*) begin : DATA_DEMUX - case(sw_debounced) - 2'h1: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = {out_data, {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}} }; - 2'h2: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {`NOC_DATA_WIDTH{1'bx}}, out_data, {`NOC_DATA_WIDTH{1'bx}} }; - 2'h3: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}}, out_data}; - default: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}}, {`NOC_DATA_WIDTH{1'bx}} }; - endcase - end - - always @(*) begin : VALID_DEMUX - case(sw_debounced) - 2'h1: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = {(CurrentState != STATE_RESET), 1'b0, 1'b0 }; - 2'h2: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, (CurrentState != STATE_RESET), 1'b0 }; - 2'h3: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, (CurrentState != STATE_RESET) }; - default: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, 1'b0 }; - endcase - end + // Assign network I/Os assign test_start = 1'b1; -/* - assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; - assign chipset_intf_data_noc2 = out_data; - assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; - - assign chipset_intf_val_noc1 = 1'b0; - assign chipset_intf_val_noc2 = (CurrentState != STATE_RESET); - assign chipset_intf_val_noc3 = 1'b0; -*/ - assign intf_chipset_rdy_noc1 = 1'b0; - assign intf_chipset_rdy_noc2 = 1'b0; - assign intf_chipset_rdy_noc3 = 1'b0; + endmodule From d5d97ef2c7268b45fa5f231424bbad34244518cc Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 23 Sep 2024 15:31:41 -0400 Subject: [PATCH 129/144] Initial revision, module for generating loopback packets. --- .../chipset/rtl/polara_loopback_packet_gen.v | 194 ++++++++++++++++++ 1 file changed, 194 insertions(+) create mode 100644 piton/design/chipset/rtl/polara_loopback_packet_gen.v diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen.v b/piton/design/chipset/rtl/polara_loopback_packet_gen.v new file mode 100644 index 000000000..f2993f024 --- /dev/null +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen.v @@ -0,0 +1,194 @@ +//`include "define.tmp.h" +//`include "piton_system.vh" + +// Filename: polara_loopback.v +// Author: Raphael Rowley (2024-09) +// Contact: raphael.rowley@polymtl.ca +// Description: Packet generation logic for polara_loopback.v +module polara_loopback_packet_gen( + input chipset_clk, + input chip_rst_n, + input [1:0] sw_debounced, + input march, + // Main chip interface + /* + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3,*/ + output reg [64-1:0] chipset_intf_data_noc1, + output reg [64-1:0] chipset_intf_data_noc2, + output reg [64-1:0] chipset_intf_data_noc3, + output reg chipset_intf_val_noc1, + output reg chipset_intf_val_noc2, + output reg chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, + + + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3 +); + // ///////////////////// + // Type declarations // + // ///////////////////// + + // ///////////////////////////////////////////////////////////////// + // NoC message for polara loopback + // CHIPID: 14'b10000000000000 + // XPOS: 8'd0 + // YPOS: 8'd0 + // FBITS: 4'b0010 + // PAYLOAD LENGTH: 8'd0 + // MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations 8'd18=8'b00010010 + // MSHR/TAG: 8'd0 + // RESERVED: 6'd0 + // ///////////////////////////////////////////////////////////////// + + parameter STATE_RESET = 3'b000; + parameter STATE_SEND = 3'b001; + parameter STATE_WAIT = 3'b010; + parameter STATE_SEND_HEADER = 3'b011; + parameter STATE_SEND_DATA = 3'b100; + + + reg [2:0] CurrentState, NextState; + //wire [`NOC_DATA_WIDTH-1:0] out_data; + reg [64-1:0] out_data, next_data; + reg [6:0] payload_count; + + reg noc_rdy; + + // //////////////////// + // Sequential Logic // + // //////////////////// + always @ (posedge chipset_clk) + begin: SEQ + if (~chip_rst_n) + begin + CurrentState <= STATE_RESET; + out_data <= {64{1'b0}}; + payload_count <= 7'd0; + end + else + begin + case (CurrentState) + STATE_RESET: + begin + if (march) + begin + CurrentState <= STATE_SEND_HEADER; + out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd65, 8'd18, 8'd0, 6'd0}; + end + else + begin + CurrentState <= STATE_SEND; + out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, 8'd18, 8'd0, 6'd0}; + end + end // case: STATE_RESET + + STATE_SEND_HEADER: + begin + if (noc_rdy) + begin + CurrentState <= STATE_SEND_DATA; + out_data <= {64{1'b0}}; + payload_count <= 7'd0; + end + end // case: STATE_SEND_HEADER + + STATE_SEND_DATA: + begin + if (noc_rdy) + begin + if (payload_count == 7'd64) + begin + CurrentState <= STATE_WAIT; + out_data <= {64{1'b0}}; + payload_count <= 7'd0; + end + else if (payload_count == 7'd0) + begin + out_data <= { {63{1'b0}} , {1'b1} }; + payload_count <= payload_count + 1'd1; + end + else + begin + out_data <= out_data << 1; + payload_count <= payload_count + 1'd1; + end + end + end // case: STATE_SEND_DATA + + STATE_SEND: + begin + if (noc_rdy) + begin + CurrentState = STATE_WAIT; + end + else + begin + CurrentState = STATE_SEND; + end + end // case: STATE_SEND + + default: // STATE_WAIT + begin + CurrentState <= STATE_WAIT; + end + + endcase // case (CurrentState) + end // else: !if(~chip_rst_n) + end // block: SEQ + + + + + // /////////////////////// + // Combinational Logic // + // /////////////////////// + + // Demuxes to route data and valid signals + // `NOC_DATA_WIDTH = 64 + // And choose which rdy signal to monitor to transmit on + always @(*) begin : RDY_DEMUX + case(sw_debounced) + 2'h1: noc_rdy = chipset_intf_rdy_noc1; + 2'h2: noc_rdy = chipset_intf_rdy_noc2; + default: noc_rdy = chipset_intf_rdy_noc3; + endcase // case (sw_debounced) + end + + always @(*) begin : DATA_DEMUX + case(sw_debounced) + 2'h1: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = {out_data, {64{1'b0}}, {64{1'b0}} }; + 2'h2: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {64{1'b0}}, out_data, {64{1'b0}} }; + 2'h3: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {64{1'b0}}, {64{1'b0}}, out_data}; + default: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {64{1'b0}}, {64{1'b0}}, {64{1'b0}} }; + endcase + end + + always @(*) begin : VALID_DEMUX + case(sw_debounced) + 2'h1: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = {(CurrentState != STATE_RESET), 1'b0, 1'b0 }; + 2'h2: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, (CurrentState != STATE_RESET), 1'b0 }; + 2'h3: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, (CurrentState != STATE_RESET) }; + default: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, 1'b0 }; + endcase + end + + /* + assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; + assign chipset_intf_data_noc2 = out_data; + assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; + + assign chipset_intf_val_noc1 = 1'b0; + assign chipset_intf_val_noc2 = (CurrentState != STATE_RESET); + assign chipset_intf_val_noc3 = 1'b0; + */ + assign intf_chipset_rdy_noc1 = 1'b0; + assign intf_chipset_rdy_noc2 = 1'b0; + assign intf_chipset_rdy_noc3 = 1'b0; + +endmodule // polara_loopback_packet_gen From 490be2eb3384bb622df36d7cb791908e8a3a0ebe Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 23 Sep 2024 15:32:04 -0400 Subject: [PATCH 130/144] Initial revision, testbench for generating loopback packets. --- .../rtl/polara_loopback_packet_gen_tb.v | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v new file mode 100644 index 000000000..47c140f50 --- /dev/null +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v @@ -0,0 +1,95 @@ +`timescale 1ns / 1ps + +// Filename: polara_loopback_packet_gen_tb.v +// Author: Raphael Rowley (2024-09) +// Contact: raphael.rowley@polymtl.ca +// Description: Testbench to functionnally simulate the packet gen logic for polara_loopback.v + +module polara_loopback_packet_gen_tb(); + + // ///////////////////// + // Type declarations // + // ///////////////////// + reg chipset_clk; + reg chip_rst_n_inter; + reg [1:0] sw_debounced; + reg march; + + + wire [64-1:0] chipset_intf_data_noc1; + wire [64-1:0] chipset_intf_data_noc2; + wire [64-1:0] chipset_intf_data_noc3; + + wire chipset_intf_val_noc1; + wire chipset_intf_val_noc2; + wire chipset_intf_val_noc3; + + reg chipset_intf_rdy_noc1; + reg chipset_intf_rdy_noc2; + reg chipset_intf_rdy_noc3; + + wire intf_chipset_rdy_noc1; + wire intf_chipset_rdy_noc2; + wire intf_chipset_rdy_noc3; + + // Instantiate DUT + polara_loopback_packet_gen dut( + .chipset_clk(chipset_clk), + .chip_rst_n(chip_rst_n_inter), + .sw_debounced(sw_debounced), + .march(march), + .chipset_intf_data_noc1(chipset_intf_data_noc1), + .chipset_intf_data_noc2(chipset_intf_data_noc2), + .chipset_intf_data_noc3(chipset_intf_data_noc3), + .chipset_intf_val_noc1(chipset_intf_val_noc1), + .chipset_intf_val_noc2(chipset_intf_val_noc2), + .chipset_intf_val_noc3(chipset_intf_val_noc3), + .chipset_intf_rdy_noc1(chipset_intf_rdy_noc1), + .chipset_intf_rdy_noc2(chipset_intf_rdy_noc2), + .chipset_intf_rdy_noc3(chipset_intf_rdy_noc3), + .intf_chipset_rdy_noc1(intf_chipset_rdy_noc1), + .intf_chipset_rdy_noc2(intf_chipset_rdy_noc2), + .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) + ); + // Clock gen + initial begin + assign chipset_clk = 1'b0; + forever #12.5 assign chipset_clk = ~chipset_clk; + end + + // Reset generation + initial begin + chip_rst_n_inter = 1'b0; + #50 + chip_rst_n_inter = 1'b1; + $display("rst_n is over: %h", chip_rst_n_inter); + #50 + $display("Current state should be 1, it is: %h", dut.CurrentState); + + end + + // Stimulus + initial begin + sw_debounced = 2'b01; + chipset_intf_rdy_noc1 = 1'b0; + chipset_intf_rdy_noc2 = 1'b0; + chipset_intf_rdy_noc3 = 1'b0; + march = 1'b0; + #150 + chipset_intf_rdy_noc1 = 1'b1; + #150 + chip_rst_n_inter = 1'b0; + chipset_intf_rdy_noc1 = 1'b0; + march = 1'b1; + #50 + chip_rst_n_inter = 1'b1; + #50 + chipset_intf_rdy_noc1 = 1'b1; + #2000 + + $finish; + + end + + +endmodule // polara_loopback_packet_gen_tb From ab69407847e9a84bce63a7a07d64e9ed3a68082f Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 23 Sep 2024 15:56:51 -0400 Subject: [PATCH 131/144] Testing what happens if noc is not ready --- piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v index 47c140f50..f1cc63bc4 100644 --- a/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v @@ -85,6 +85,10 @@ module polara_loopback_packet_gen_tb(); chip_rst_n_inter = 1'b1; #50 chipset_intf_rdy_noc1 = 1'b1; + #500 + chipset_intf_rdy_noc1 = 1'b0; + #500 + chipset_intf_rdy_noc1 = 1'b1; #2000 $finish; From 5b69341c23454e2351d53888f2ff4aecc97a5fac Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 30 Sep 2024 10:24:49 -0400 Subject: [PATCH 132/144] Modifications to allow bitstream generation. --- piton/design/chipset/rtl/chipset.v | 3 +- piton/design/chipset/rtl/polara_loopback.v | 18 +- .../chipset/xilinx/genesys2/constraints.xdc | 211 ++++++++++++++---- piton/tools/src/proto/common/rtl_setup.tcl | 3 +- 4 files changed, 182 insertions(+), 53 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 76bff5149..bbcc2dedd 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1345,7 +1345,8 @@ chipset_impl_noc_power_test chipset_impl ( .invalid_access_o (invalid_access ), `else // ifndef POLARA_LOOPBACK .sw_channel_msb(sw[1]), - .sw_channel_lsb(sw[0]), + .sw_channel_lsb(sw[0]), + .sw_march(sw[2]), `endif // ifndef POLARA_LOOPBACK `endif diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index 3443a1662..e8e2db58f 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -22,15 +22,15 @@ module chipset_impl_polara_loopback( output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3,*/ - output reg [64-1:0] chipset_intf_data_noc1, - output reg [64-1:0] chipset_intf_data_noc2, - output reg [64-1:0] chipset_intf_data_noc3, - output reg chipset_intf_val_noc1, - output reg chipset_intf_val_noc2, - output reg chipset_intf_val_noc3, - input chipset_intf_rdy_noc1, - input chipset_intf_rdy_noc2, - input chipset_intf_rdy_noc3, + output [64-1:0] chipset_intf_data_noc1, + output [64-1:0] chipset_intf_data_noc2, + output [64-1:0] chipset_intf_data_noc3, + output chipset_intf_val_noc1, + output chipset_intf_val_noc2, + output chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, /*input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index f9ef63659..4d8c80297 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -775,6 +775,129 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] connect_debug_port dbg_hub/clk [get_nets clk] +connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/CurrentState[0]} {chipset_impl/CurrentState[1]}]] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] + +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_50] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_51] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_52] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_31] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_27] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_24] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_25] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_26] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_28] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_29] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_30] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_32] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_33] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_34] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_35] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_36] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_37] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_38] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_39] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_40] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_41] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_42] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_43] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_44] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_45] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_46] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_47] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_48] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_49] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_53] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_54] +set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_55] + +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/CurrentState__0[1]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/CurrentState__0[2]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/CurrentState__0[0]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[33]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[34]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[36]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[51]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[56]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[47]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[42]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[39]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[41]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[44]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[45]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[46]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[49]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[50]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[53]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[55]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[58]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[61]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[63]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[62]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[60]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[57]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[54]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[52]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[9]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[0]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[2]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[4]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[7]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[13]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[15]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[20]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[17]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[23]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[22]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[30]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[31]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[11]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[12]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[32]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[35]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[37]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[38]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[40]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[43]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[48]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[59]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[6]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[8]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[3]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[1]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[5]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[10]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[16]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[19]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[21]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[27]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[28]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[24]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[26]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[29]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[25]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[18]}] +set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[14]}] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] @@ -803,164 +926,168 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe3] connect_debug_port u_ila_0/probe3 [get_nets [list {chipset_impl/polara_gen2chipset_bus_o_tri_o[0]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 2 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/CurrentState[0]} {chipset_impl/CurrentState[1]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[0]_i_1__0_n_0}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {chipset_impl/packet_gen_i/CurrentState__0[0]} {chipset_impl/packet_gen_i/CurrentState__0[1]} {chipset_impl/packet_gen_i/CurrentState__0[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[1]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[0]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[2]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[1]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list io_clk_OBUF]] +connect_debug_port u_ila_0/probe8 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[2]_i_1__0_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list offchip_processor_noc2_valid]] +connect_debug_port u_ila_0/probe9 [get_nets [list io_clk_OBUF]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] +connect_debug_port u_ila_0/probe10 [get_nets [list offchip_processor_noc2_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +connect_debug_port u_ila_0/probe40 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +connect_debug_port u_ila_0/probe41 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +connect_debug_port u_ila_0/probe42 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +connect_debug_port u_ila_0/probe43 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] +set_property port_width 1 [get_debug_ports u_ila_0/probe44] +connect_debug_port u_ila_0/probe44 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index e19a50f1c..5e1ead991 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -777,7 +777,8 @@ set PASSTHRU_PRJ_IP_FILES [list \ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ - "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv"\ + "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv"\ + "${DV_ROOT}/design/chipset/rtl/polara_loopback_packet_gen.v" \ "${DV_ROOT}/design/chipset/rtl/polara_debouncer.sv" \ "${DV_ROOT}/design/chipset/rtl/polara_loopback.v" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ From 5137f702f1bae7ae097558197ece437c91944d3f Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 30 Sep 2024 10:30:13 -0400 Subject: [PATCH 133/144] Inverted channel pins coming from ASIC --- piton/design/chipset/xilinx/genesys2/constraints.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index f9ef63659..b99414ed2 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -667,7 +667,7 @@ set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_d #set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] #set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] #set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] @@ -686,7 +686,7 @@ set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_c #set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] #set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] #set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] From 6c4f9dcd3a0c245f3edc10f4625adbc9ad3003cb Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 18 Oct 2024 08:21:36 -0400 Subject: [PATCH 134/144] Added FLL Loopback flow. --- .../src/proto/genesys2/jtag_axi_commands.tcl | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl index 497ccc055..a909e722f 100644 --- a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -33,6 +33,7 @@ # Channel 2 AXI GPIO Data Register Address Space Offset: 0x0008 # 0: fll_lock # 1: fll_clkdiv +# set_msg_config -id "Labtoolstcl 44-481" -limit 5500 # #################################################################### # Init @@ -58,6 +59,35 @@ create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -dat # Run it run_hw_axi [get_hw_axi_txns cfgrstoff] +# #################################################################### +# Loopback flow. FLL +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# f_fll = 2^2 * f_ref +# ------------------------------------------ +# 3. Set opmode = 1, fll_rst_n = 1, fll_range = 0010 +create_hw_axi_txn -force op2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000250} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2rstoff] +# 4. Set cfgreq = 1 +create_hw_axi_txn -force op2cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000002D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2cfg] +# 5. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op2rstoff] +# FLL previously configured with range = 2 +# 7. Keep the config but activate: async_mux = 1, clk_en = 1 +create_hw_axi_txn -force en2rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000256} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rston] +# 8. Release the reset +create_hw_axi_txn -force en2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000257} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rstoff] + + # #################################################################### # Genesys 2 Memory Test # #################################################################### From c8cf695bc7da9c7aef17324d124b37e4925108f3 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 18 Oct 2024 08:22:50 -0400 Subject: [PATCH 135/144] ILA for loopback mode --- .../chipset/xilinx/genesys2/constraints.xdc | 232 ++++-------------- 1 file changed, 52 insertions(+), 180 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index e27400595..6c04440e1 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -667,7 +667,7 @@ set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_d #set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] #set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] #set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] @@ -686,7 +686,7 @@ set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_c #set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] #set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] #set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] #set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] @@ -766,143 +766,11 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] #set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] #set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] - - - - - - - -connect_debug_port dbg_hub/clk [get_nets clk] - -connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/CurrentState[0]} {chipset_impl/CurrentState[1]}]] -connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] - -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_50] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_51] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_52] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_31] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_27] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_24] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_25] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_26] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_28] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_29] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_30] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_32] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_33] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_34] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_35] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_36] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_37] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_38] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_39] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_40] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_41] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_42] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_43] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_44] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_45] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_46] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_47] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_48] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_49] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_53] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_54] -set_property MARK_DEBUG true [get_nets fpga_bridge/fpga_chip_out/separator_n_55] - -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/CurrentState__0[1]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/CurrentState__0[2]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/CurrentState__0[0]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[33]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[34]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[36]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[51]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[56]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[47]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[42]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[39]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[41]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[44]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[45]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[46]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[49]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[50]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[53]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[55]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[58]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[61]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[63]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[62]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[60]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[57]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[54]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[52]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[9]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[0]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[2]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[4]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[7]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[13]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[15]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[20]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[17]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[23]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[22]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[30]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[31]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[11]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[12]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[32]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[35]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[37]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[38]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[40]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[43]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[48]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[59]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[6]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[8]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[3]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[1]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[5]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[10]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[16]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[19]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[21]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[27]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[28]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[24]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[26]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[29]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[25]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[18]}] -set_property MARK_DEBUG true [get_nets {chipset_impl/packet_gen_i/data_out[14]}] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] @@ -914,16 +782,16 @@ set_property port_width 3 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 64 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 2 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 1 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {chipset_impl/polara_gen2chipset_bus_o_tri_o[0]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 64 [get_debug_ports u_ila_0/probe4] @@ -935,159 +803,163 @@ connect_debug_port u_ila_0/probe5 [get_nets [list {chipset_impl/packet_gen_i/Cur create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[0]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[1]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out_f[2]_i_1__0_n_0}]] +connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list io_clk_OBUF]] +connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list offchip_processor_noc2_valid]] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] +connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] +connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] +connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] +connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] +connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] +connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] +connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] +connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] +connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] +connect_debug_port u_ila_0/probe40 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] +connect_debug_port u_ila_0/probe41 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] +connect_debug_port u_ila_0/probe42 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +connect_debug_port u_ila_0/probe43 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +connect_debug_port u_ila_0/probe44 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] +set_property port_width 1 [get_debug_ports u_ila_0/probe45] +connect_debug_port u_ila_0/probe45 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] From 5ca4ab2058f288433201a0e178a1232b410f037b Mon Sep 17 00:00:00 2001 From: rrpsid Date: Fri, 18 Oct 2024 09:07:17 -0400 Subject: [PATCH 136/144] Added I/O constraints for max delays --- .../chipset/xilinx/genesys2/constraints.xdc | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 6c04440e1..6270940ca 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -705,6 +705,95 @@ set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_c #set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS25 } [get_ports { F79_N }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] #set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS25 } [get_ports { F79_P }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] +# ############################################################### +# Input and output delay constraints +# ############################################################### +# Inputs +# Try by saying can arrive in 90% of clock period +# 90% * 125 = 112.5 +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_channel[1]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_channel[0]] + +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[31]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[30]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[29]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[28]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[27]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[26]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[25]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[24]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[23]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[22]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[21]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[20]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[19]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[18]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[17]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[16]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[15]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[14]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[13]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[12]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[11]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[10]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[9]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[8]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[7]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[6]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[5]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[4]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[3]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[2]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[1]] +set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[0]] + +set_input_delay -max -clock io_clk 112.5 [get_ports intf_chip_credit_back[2]] +set_input_delay -max -clock io_clk 112.5 [get_ports intf_chip_credit_back[1]] +set_input_delay -max -clock io_clk 112.5 [get_ports intf_chip_credit_back[0]] + +# Outputs +# Try by saying can leave in 20% of clock period +# 20% * 125 = 25 + +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_channel[1]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_channel[0]] + +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[31]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[30]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[29]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[28]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[27]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[26]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[25]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[24]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[23]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[22]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[21]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[20]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[19]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[18]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[17]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[16]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[15]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[14]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[13]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[12]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[11]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[10]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[9]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[8]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[7]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[6]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[5]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[4]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[3]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[2]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[1]] +set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[0]] + +set_output_delay -max -clock io_clk 25 [get_ports chip_intf_credit_back[2]] +set_output_delay -max -clock io_clk 25 [get_ports chip_intf_credit_back[1]] +set_output_delay -max -clock io_clk 25 [get_ports chip_intf_credit_back[0]] ### False paths #set_clock_groups -name sync_gr1 -logically_exclusive -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] From 94d14a5d0ae5f703a570c641e0a28e33596c05c0 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 21 Oct 2024 14:30:58 -0400 Subject: [PATCH 137/144] Added a synchronizer for the reset since the debouncers required a synchronized one. Added go signal to control when data is sent. --- piton/design/chipset/rtl/polara_loopback.v | 97 ++++++++++++------- .../chipset/rtl/polara_loopback_packet_gen.v | 35 +++++-- .../rtl/polara_loopback_packet_gen_tb.v | 26 ++++- 3 files changed, 113 insertions(+), 45 deletions(-) diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index e8e2db58f..e030bd118 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -9,13 +9,15 @@ module chipset_impl_polara_loopback( // Clocks and resets - input chipset_clk, - input chipset_rst_n, + input chipset_clk, + input chipset_rst_n, // Switches - input sw_channel_msb, - input sw_channel_lsb, - input sw_march, + input sw_channel_msb, + input sw_channel_lsb, + input sw_march, + input sw_go, + output sanity_is_waiting, // Main chip interface /* @@ -35,40 +37,40 @@ module chipset_impl_polara_loopback( /*input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3,*/ - input [64-1:0] intf_chipset_data_noc1, - input [64-1:0] intf_chipset_data_noc2, - input [64-1:0] intf_chipset_data_noc3, - input intf_chipset_val_noc1, - input intf_chipset_val_noc2, - input intf_chipset_val_noc3, - output intf_chipset_rdy_noc1, - output intf_chipset_rdy_noc2, - output intf_chipset_rdy_noc3, + input [64-1:0] intf_chipset_data_noc1, + input [64-1:0] intf_chipset_data_noc2, + input [64-1:0] intf_chipset_data_noc3, + input intf_chipset_val_noc1, + input intf_chipset_val_noc2, + input intf_chipset_val_noc3, + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3, // Chip and other BD signals - input mc_clk, // not sure if needed - input mig_ddr3_sys_se_clock_clk, - output chip_async_mux, - output chip_clk_en, - output chip_clk_mux_sel, - output chip_rst_n, - output init_calib_complete, - output test_start, + input mc_clk, // not sure if needed + input mig_ddr3_sys_se_clock_clk, + output chip_async_mux, + output chip_clk_en, + output chip_clk_mux_sel, + output chip_rst_n, + output init_calib_complete, + output test_start, // FLL - input fll_clkdiv, - input fll_lock, - output fll_bypass, - output fll_cfg_req, - output fll_opmode, - output [3:0] fll_range, - output fll_rst_n, + input fll_clkdiv, + input fll_lock, + output fll_bypass, + output fll_cfg_req, + output fll_opmode, + output [3:0] fll_range, + output fll_rst_n, // Just dummy signals - output uart_tx, - input uart_rx, - input uart_boot_en, - input uart_timeout_en + output uart_tx, + input uart_rx, + input uart_boot_en, + input uart_timeout_en ); // ///////////////////// @@ -95,6 +97,9 @@ module chipset_impl_polara_loopback( wire sw_lsb_debounced; wire [1:0] sw_debounced; wire sw_march_debounced; + wire sw_go_debounced; + + reg Q1, chipset_rstn_sync; ////////////////////// // Sequential Logic // @@ -110,6 +115,8 @@ module chipset_impl_polara_loopback( .chip_rst_n(chip_rst_n_inter), .sw_debounced(sw_debounced), .march(sw_march_debounced), + .go(sw_go_debounced), + .sanity_is_waiting(sanity_is_waiting), .chipset_intf_data_noc1(chipset_intf_data_noc1), .chipset_intf_data_noc2(chipset_intf_data_noc2), .chipset_intf_data_noc3(chipset_intf_data_noc3), @@ -127,29 +134,45 @@ module chipset_impl_polara_loopback( // Instantiate the block design gen2_polara_fpga_loopback gen2_polara_fpga_i( .bd_clk(chipset_clk), - .mig_ddr3_sys_rst_n(chipset_rst_n), + .mig_ddr3_sys_rst_n(chipset_rstn_sync), .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o) ); + // Synchronize the reset signal and send to the rest of the blocks + always @ (posedge chipset_clk, negedge chipset_rst_n) + if(!chipset_rst_n) begin + Q1 <= 1’b0; + chipset_rstn_sync <= 1’b0; + end else begin + Q1 <= 1’b1; + chipset_rstn_sync <= Q1; + end + end + // Instantiate debouncers for the 2 channel switches debouncer debouncer_sw_msb( .clk(chipset_clk), - .rstn(chipset_rst_n), + .rstn(chipset_rstn_sync), .i_sig(sw_channel_msb), .o_sig_debounced(sw_msb_debounced)); debouncer debouncer_sw_lsb( .clk(chipset_clk), - .rstn(chipset_rst_n), + .rstn(chipset_rstn_sync), .i_sig(sw_channel_lsb), .o_sig_debounced(sw_lsb_debounced)); assign sw_debounced = {sw_msb_debounced, sw_lsb_debounced}; debouncer debouncer_sw_march( .clk(chipset_clk), - .rstn(chipset_rst_n), + .rstn(chipset_rstn_sync), .i_sig(sw_march), .o_sig_debounced(sw_march_debounced)); + debouncer debouncer_sw_go( + .clk(chipset_clk), + .rstn(chipset_rstn_sync), + .i_sig(sw_go), + .o_sig_debounced(sw_go_debounced)); diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen.v b/piton/design/chipset/rtl/polara_loopback_packet_gen.v index f2993f024..2dd173a1e 100644 --- a/piton/design/chipset/rtl/polara_loopback_packet_gen.v +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen.v @@ -9,7 +9,9 @@ module polara_loopback_packet_gen( input chipset_clk, input chip_rst_n, input [1:0] sw_debounced, - input march, + input march, + input go, + output reg sanity_is_waiting, // Main chip interface /* output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, @@ -60,22 +62,36 @@ module polara_loopback_packet_gen( reg noc_rdy; + + // //////////////////// // Sequential Logic // // //////////////////// - always @ (posedge chipset_clk) + always @ (posedge chipset_clk, negedge chip_rst_n) begin: SEQ if (~chip_rst_n) begin CurrentState <= STATE_RESET; out_data <= {64{1'b0}}; payload_count <= 7'd0; + sanity_is_waiting <= 1'b1; end else begin case (CurrentState) STATE_RESET: begin + sanity_is_waiting <= 1'b1; + if (go) + begin + sanity_is_waiting <= 1'b0; + CurrentState <= STATE_WAIT; + end + end // case: STATE_RESET + + STATE_WAIT: + begin + sanity_is_waiting <= 1'b0; if (march) begin CurrentState <= STATE_SEND_HEADER; @@ -86,10 +102,11 @@ module polara_loopback_packet_gen( CurrentState <= STATE_SEND; out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, 8'd18, 8'd0, 6'd0}; end - end // case: STATE_RESET + end STATE_SEND_HEADER: begin + sanity_is_waiting <= 1'b0; if (noc_rdy) begin CurrentState <= STATE_SEND_DATA; @@ -100,11 +117,13 @@ module polara_loopback_packet_gen( STATE_SEND_DATA: begin + sanity_is_waiting <= 1'b0; if (noc_rdy) begin if (payload_count == 7'd64) begin - CurrentState <= STATE_WAIT; + sanity_is_waiting <= 1'b1; + CurrentState <= STATE_RESET; out_data <= {64{1'b0}}; payload_count <= 7'd0; end @@ -123,9 +142,12 @@ module polara_loopback_packet_gen( STATE_SEND: begin + sanity_is_waiting <= 1'b0; if (noc_rdy) begin - CurrentState = STATE_WAIT; + sanity_is_waiting <= 1'b1; + CurrentState = STATE_RESET; + out_data <= {64{1'b0}}; end else begin @@ -135,7 +157,8 @@ module polara_loopback_packet_gen( default: // STATE_WAIT begin - CurrentState <= STATE_WAIT; + sanity_is_waiting <= 1'b1; + CurrentState <= STATE_RESET; end endcase // case (CurrentState) diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v index f1cc63bc4..74d038e93 100644 --- a/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v @@ -14,8 +14,10 @@ module polara_loopback_packet_gen_tb(); reg chip_rst_n_inter; reg [1:0] sw_debounced; reg march; - + reg go; + wire sanity; + wire [64-1:0] chipset_intf_data_noc1; wire [64-1:0] chipset_intf_data_noc2; wire [64-1:0] chipset_intf_data_noc3; @@ -38,6 +40,8 @@ module polara_loopback_packet_gen_tb(); .chip_rst_n(chip_rst_n_inter), .sw_debounced(sw_debounced), .march(march), + .go(go), + .sanity_is_waiting(sanity), .chipset_intf_data_noc1(chipset_intf_data_noc1), .chipset_intf_data_noc2(chipset_intf_data_noc2), .chipset_intf_data_noc3(chipset_intf_data_noc3), @@ -75,12 +79,17 @@ module polara_loopback_packet_gen_tb(); chipset_intf_rdy_noc2 = 1'b0; chipset_intf_rdy_noc3 = 1'b0; march = 1'b0; + go = 1'b1; + #150 chipset_intf_rdy_noc1 = 1'b1; #150 + go = 1'b0; chip_rst_n_inter = 1'b0; chipset_intf_rdy_noc1 = 1'b0; march = 1'b1; + #50 + go = 1'b1; #50 chip_rst_n_inter = 1'b1; #50 @@ -90,7 +99,20 @@ module polara_loopback_packet_gen_tb(); #500 chipset_intf_rdy_noc1 = 1'b1; #2000 - + chip_rst_n_inter = 1'b0; + go = 1'b0; + #100 + chip_rst_n_inter = 1'b1; + $display("rst_n is over: %h", chip_rst_n_inter); + #50 + $display("Current state should be 1, it is: %h", dut.CurrentState); + #400 + go = 1'b1; + #400 + go = 1'b0; + #2000 + go = 1'b1; + #1000 $finish; end From 117c4903be82b20bec91a013a9b0fe1d7dac6f68 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Sun, 3 Nov 2024 09:22:42 -0500 Subject: [PATCH 138/144] Added commands to run system fully synchronous --- .../src/proto/genesys2/jtag_axi_commands.tcl | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl index a909e722f..333a9b7ec 100644 --- a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -59,6 +59,24 @@ create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -dat # Run it run_hw_axi [get_hw_axi_txns cfgrstoff] +# #################################################################### +# Loopback flow. We are not using FLL. All synchronous +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_async_mux = 0, chip_clk_en = 1, chip_clk_mux_sel = 1, rst on +create_hw_axi_txn -force cfgrst [get_hw_axis hw_axi_1] -address 40000000 -data {0000000C} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrst] +# 4. cfg take off rst +create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {0000000D} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrstoff] + # #################################################################### # Loopback flow. FLL # #################################################################### From fb14d659b7f1115962b53ee46821365ac44761ec Mon Sep 17 00:00:00 2001 From: rrpsid Date: Sun, 3 Nov 2024 09:23:45 -0500 Subject: [PATCH 139/144] Fixes to allow bitstream generation --- piton/design/chipset/rtl/polara_loopback.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v index e030bd118..c17209428 100644 --- a/piton/design/chipset/rtl/polara_loopback.v +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -142,13 +142,12 @@ module chipset_impl_polara_loopback( // Synchronize the reset signal and send to the rest of the blocks always @ (posedge chipset_clk, negedge chipset_rst_n) if(!chipset_rst_n) begin - Q1 <= 1’b0; - chipset_rstn_sync <= 1’b0; + Q1 <= 1'b0; + chipset_rstn_sync <= 1'b0; end else begin - Q1 <= 1’b1; + Q1 <= 1'b1; chipset_rstn_sync <= Q1; end - end // Instantiate debouncers for the 2 channel switches debouncer debouncer_sw_msb( From 4fb8de85d47b822e6b6cdf72255fd6890da3e792 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Sun, 3 Nov 2024 09:24:20 -0500 Subject: [PATCH 140/144] Fixes to allow bitstream generation for 8MHz chipset loopback variation --- .../ip_cores/atg_uart_init/uart_data.coe | 2 +- .../chipset/xilinx/genesys2/constraints.xdc | 243 +++++++++--------- .../genesys2/ip_cores/clk_mmcm/clk_mmcm.xci | 28 +- piton/tools/src/proto/block.list | 2 +- 4 files changed, 136 insertions(+), 139 deletions(-) diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe index aef527768..b4b7e995f 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe @@ -1,2 +1,2 @@ memory_initialization_radix=16; -memory_initialization_vector=00000080 00000016 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; +memory_initialization_vector=00000080 00000004 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 6270940ca..722a1931a 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -711,89 +711,89 @@ set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_c # Inputs # Try by saying can arrive in 90% of clock period # 90% * 125 = 112.5 -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_channel[1]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_channel[0]] - -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[31]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[30]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[29]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[28]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[27]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[26]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[25]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[24]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[23]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[22]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[21]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[20]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[19]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[18]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[17]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[16]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[15]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[14]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[13]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[12]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[11]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[10]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[9]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[8]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[7]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[6]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[5]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[4]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[3]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[2]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[1]] -set_input_delay -max -clock io_clk 112.5 [get_ports chip_intf_data[0]] - -set_input_delay -max -clock io_clk 112.5 [get_ports intf_chip_credit_back[2]] -set_input_delay -max -clock io_clk 112.5 [get_ports intf_chip_credit_back[1]] -set_input_delay -max -clock io_clk 112.5 [get_ports intf_chip_credit_back[0]] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_channel[1]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_channel[0]}] + +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[31]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[30]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[29]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[28]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[27]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[26]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[25]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[24]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[23]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[22]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[21]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[20]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[19]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[18]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[17]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[16]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[15]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[14]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[13]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[12]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[11]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[10]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[9]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[8]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[7]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[6]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[5]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[4]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[3]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[2]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[1]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[0]}] + +set_input_delay -clock io_clk -max 112.500 [get_ports {intf_chip_credit_back[2]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {intf_chip_credit_back[1]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {intf_chip_credit_back[0]}] # Outputs # Try by saying can leave in 20% of clock period # 20% * 125 = 25 -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_channel[1]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_channel[0]] - -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[31]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[30]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[29]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[28]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[27]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[26]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[25]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[24]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[23]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[22]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[21]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[20]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[19]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[18]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[17]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[16]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[15]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[14]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[13]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[12]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[11]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[10]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[9]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[8]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[7]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[6]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[5]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[4]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[3]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[2]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[1]] -set_output_delay -max -clock io_clk 25 [get_ports intf_chip_data[0]] - -set_output_delay -max -clock io_clk 25 [get_ports chip_intf_credit_back[2]] -set_output_delay -max -clock io_clk 25 [get_ports chip_intf_credit_back[1]] -set_output_delay -max -clock io_clk 25 [get_ports chip_intf_credit_back[0]] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_channel[1]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_channel[0]}] + +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[31]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[30]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[29]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[28]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[27]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[26]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[25]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[24]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[23]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[22]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[21]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[20]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[19]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[18]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[17]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[16]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[15]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[14]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[13]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[12]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[11]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[10]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[9]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[8]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[7]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[6]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[5]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[4]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[3]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[2]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[1]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[0]}] + +set_output_delay -clock io_clk -max 25.000 [get_ports {chip_intf_credit_back[2]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {chip_intf_credit_back[1]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {chip_intf_credit_back[0]}] ### False paths #set_clock_groups -name sync_gr1 -logically_exclusive -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] @@ -855,6 +855,7 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] #set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] #set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] @@ -887,168 +888,164 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe4] connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 3 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {chipset_impl/packet_gen_i/CurrentState__0[0]} {chipset_impl/packet_gen_i/CurrentState__0[1]} {chipset_impl/packet_gen_i/CurrentState__0[2]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +connect_debug_port u_ila_0/probe9 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +connect_debug_port u_ila_0/probe10 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] +connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] +connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] +connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] +connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] +connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] +connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] +connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] +connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] +connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] +connect_debug_port u_ila_0/probe40 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] +connect_debug_port u_ila_0/probe41 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] +connect_debug_port u_ila_0/probe42 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] +connect_debug_port u_ila_0/probe43 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] -set_property port_width 1 [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] +connect_debug_port u_ila_0/probe44 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci index fdf8f5c38..8a7755f96 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci @@ -131,17 +131,17 @@ 100.0 0000 0000 - 40.00000 + 8.00000 0000 0000 200.00000 BUFG 50.0 false - 40.00000 + 8.00000 0.000 50.000 - 40 + 8 0.000 1 0000 @@ -236,12 +236,12 @@ din 0000 1 - 0.2 - 5.0 - 5.0 - 0.4 - 1.6 - 0.4 + 0.04 + 1.0 + 1.0 + 0.08 + 0.32 + 0.08 dout drdy dwe @@ -284,7 +284,7 @@ FALSE 5.000 10.0 - 25.000 + 125.000 0.500 0.000 FALSE @@ -326,7 +326,7 @@ 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - chipset_clk__40.00000______0.000______50.0______135.255_____89.971 + chipset_clk___8.00000______0.000______50.0______186.029_____89.971 mc_sys_clk__200.00000______0.000______50.0_______98.146_____89.971 __io_clk___8.00000______0.000______50.0______186.029_____89.971 io_clk_not___8.00000____180.000______50.0______186.029_____89.971 @@ -448,11 +448,11 @@ 100.0 0.010 BUFG - 135.255 + 186.029 false 89.971 50.000 - 40 + 8 0.000 1 true @@ -564,7 +564,7 @@ false 5.000 10.0 - 25.000 + 125.000 0.500 0.000 false diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 2a7fe49dc..01ef11a8f 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -26,7 +26,7 @@ # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 -chipset chipset genesys2,40,1024;piton_board,50,0 +chipset chipset genesys2,8,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 chip chip genesys2,66.667,1024;vc707,50,1024 From c1b12f54ec89cb1c2b356c26742ecabaa8da4c32 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 11 Nov 2024 09:31:09 -0500 Subject: [PATCH 141/144] Connecting switch 3 to go signal. And now sending on one edge, receiving on the other in fpga bridge. Constraints updated for ILA. --- piton/design/chipset/rtl/chipset.v | 1 + .../chipset/xilinx/genesys2/constraints.xdc | 124 ++++++++---------- .../common/fpga_bridge/rtl/fpga_bridge.v | 7 +- 3 files changed, 58 insertions(+), 74 deletions(-) diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index bbcc2dedd..d6adce844 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -1347,6 +1347,7 @@ chipset_impl_noc_power_test chipset_impl ( .sw_channel_msb(sw[1]), .sw_channel_lsb(sw[0]), .sw_march(sw[2]), + .sw_go(sw[3]), `endif // ifndef POLARA_LOOPBACK `endif diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 722a1931a..feb851345 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -856,11 +856,19 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] #set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] +connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] +connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] +connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] +connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] +connect_debug_port u_ila_0/probe9 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] +connect_debug_port u_ila_0/probe10 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] @@ -868,184 +876,156 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 3 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 3 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 64 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 2 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 64 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] +connect_debug_port u_ila_0/probe5 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] +connect_debug_port u_ila_0/probe6 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] +connect_debug_port u_ila_0/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] +connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] +connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] +connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] +connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] +connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] +connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] +connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] +connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] +connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] +connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] +connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] +connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] +connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] +connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] +connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] +connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] +connect_debug_port u_ila_0/probe36 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] -set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] -set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] -set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +connect_debug_port u_ila_0/probe37 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/piton/design/common/fpga_bridge/rtl/fpga_bridge.v b/piton/design/common/fpga_bridge/rtl/fpga_bridge.v index 032616756..fefaa9976 100644 --- a/piton/design/common/fpga_bridge/rtl/fpga_bridge.v +++ b/piton/design/common/fpga_bridge/rtl/fpga_bridge.v @@ -72,12 +72,15 @@ module fpga_bridge( parameter SEND_CREDIT_THRESHOLD = 9'd255; + wire not_intf_out_clk = ~intf_out_clk; + + fpga_bridge_send_32 #( .FULL_THRESHOLD(SEND_CREDIT_THRESHOLD) )fpga_chip_out( .rst(~rst_n), .wr_clk(fpga_out_clk), - .rd_clk(intf_out_clk), + .rd_clk(not_intf_out_clk), .credit_wr_clk(intf_in_clk), .bin_data_1(fpga_intf_data_noc1), .bin_val_1(fpga_intf_val_noc1), @@ -97,7 +100,7 @@ fpga_bridge_rcv_32 fpga_chip_in ( .rst(~rst_n), .wr_clk(intf_in_clk), .rd_clk(fpga_in_clk), - .credit_rd_clk(intf_out_clk), + .credit_rd_clk(not_intf_out_clk), .bout_data_1(intf_fpga_data_noc1), .bout_val_1(intf_fpga_val_noc1), .bout_rdy_1(intf_fpga_rdy_noc1), From a4bc52ec3f31dba8070cafbf2033695bd096cac9 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 25 Nov 2024 13:16:59 -0500 Subject: [PATCH 142/144] Send a single loopback packet before the marching 1s --- piton/design/chipset/rtl/polara_loopback_packet_gen.v | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen.v b/piton/design/chipset/rtl/polara_loopback_packet_gen.v index 2dd173a1e..2cef48a2d 100644 --- a/piton/design/chipset/rtl/polara_loopback_packet_gen.v +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen.v @@ -53,6 +53,7 @@ module polara_loopback_packet_gen( parameter STATE_WAIT = 3'b010; parameter STATE_SEND_HEADER = 3'b011; parameter STATE_SEND_DATA = 3'b100; + parameter STATE_SPECIAL_WAIT = 3'b101; reg [2:0] CurrentState, NextState; @@ -85,9 +86,15 @@ module polara_loopback_packet_gen( if (go) begin sanity_is_waiting <= 1'b0; - CurrentState <= STATE_WAIT; + CurrentState <= STATE_SPECIAL_WAIT; end end // case: STATE_RESET + STATE_SPECIAL_WAIT: + begin + sanity_is_waiting <= 1'b0; + CurrentState <= STATE_SEND; + out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, 8'd18, 8'd0, 6'd0}; + end STATE_WAIT: begin @@ -146,7 +153,7 @@ module polara_loopback_packet_gen( if (noc_rdy) begin sanity_is_waiting <= 1'b1; - CurrentState = STATE_RESET; + CurrentState = STATE_WAIT; out_data <= {64{1'b0}}; end else From abf8a5ac67c22784a0cb3a5fe068d3f08678b352 Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 25 Nov 2024 13:20:13 -0500 Subject: [PATCH 143/144] Changes to ILA so that normal chipset can run --- .../chipset/xilinx/genesys2/constraints.xdc | 239 ++++++++++-------- 1 file changed, 127 insertions(+), 112 deletions(-) diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index feb851345..ef12cabc6 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -856,13 +856,18 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] #set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] -connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] -connect_debug_port u_ila_0/probe5 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] -connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] -connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] -connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] -connect_debug_port u_ila_0/probe9 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] -connect_debug_port u_ila_0/probe10 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] +#connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] +#connect_debug_port u_ila_0/probe5 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] +#connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] +#connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] +#connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] +#connect_debug_port u_ila_0/probe9 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] +#connect_debug_port u_ila_0/probe10 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] + +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] @@ -876,156 +881,166 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 2 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 64 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 3 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] +set_property port_width 64 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 3 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 1 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +connect_debug_port u_ila_0/probe6 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +connect_debug_port u_ila_0/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_35]] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] -set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] -set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_40]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_41]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_42]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] -set_property port_width 1 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_43]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] -set_property port_width 1 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_44]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] -set_property port_width 1 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_45]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -set_property port_width 1 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_46]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] -set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_47]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] -set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_48]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] -set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_49]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] -set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_50]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] -set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_51]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] -set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_52]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] -set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_53]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] -set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_54]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] -set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_55]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] -set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] -set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +create_debug_core u_ila_1 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] +set_property port_width 1 [get_debug_ports u_ila_1/clk] +connect_debug_port u_ila_1/clk [get_nets [list not_intf_out_clk]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] +set_property port_width 1 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] +set_property port_width 1 [get_debug_ports u_ila_1/probe1] +connect_debug_port u_ila_1/probe1 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] +set_property port_width 1 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] +set_property port_width 1 [get_debug_ports u_ila_1/probe3] +connect_debug_port u_ila_1/probe3 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4] +set_property port_width 1 [get_debug_ports u_ila_1/probe4] +connect_debug_port u_ila_1/probe4 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5] +set_property port_width 1 [get_debug_ports u_ila_1/probe5] +connect_debug_port u_ila_1/probe5 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6] +set_property port_width 1 [get_debug_ports u_ila_1/probe6] +connect_debug_port u_ila_1/probe6 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7] +set_property port_width 1 [get_debug_ports u_ila_1/probe7] +connect_debug_port u_ila_1/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8] +set_property port_width 1 [get_debug_ports u_ila_1/probe8] +connect_debug_port u_ila_1/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9] +set_property port_width 1 [get_debug_ports u_ila_1/probe9] +connect_debug_port u_ila_1/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10] +set_property port_width 1 [get_debug_ports u_ila_1/probe10] +connect_debug_port u_ila_1/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11] +set_property port_width 1 [get_debug_ports u_ila_1/probe11] +connect_debug_port u_ila_1/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12] +set_property port_width 1 [get_debug_ports u_ila_1/probe12] +connect_debug_port u_ila_1/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13] +set_property port_width 1 [get_debug_ports u_ila_1/probe13] +connect_debug_port u_ila_1/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14] +set_property port_width 1 [get_debug_ports u_ila_1/probe14] +connect_debug_port u_ila_1/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15] +set_property port_width 1 [get_debug_ports u_ila_1/probe15] +connect_debug_port u_ila_1/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16] +set_property port_width 1 [get_debug_ports u_ila_1/probe16] +connect_debug_port u_ila_1/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17] +set_property port_width 1 [get_debug_ports u_ila_1/probe17] +connect_debug_port u_ila_1/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18] +set_property port_width 1 [get_debug_ports u_ila_1/probe18] +connect_debug_port u_ila_1/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe19] +set_property port_width 1 [get_debug_ports u_ila_1/probe19] +connect_debug_port u_ila_1/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe20] +set_property port_width 1 [get_debug_ports u_ila_1/probe20] +connect_debug_port u_ila_1/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] From 21e014dd5c3643d34e304ecc9f36c9e8cfbd9bfc Mon Sep 17 00:00:00 2001 From: rrpsid Date: Mon, 25 Nov 2024 13:38:58 -0500 Subject: [PATCH 144/144] Removed ILA on DDR since vivado had trouble synthesizing the chipset with it. The ILA failed timing --- .../src/proto/genesys2/gen2_polara_fpga_se_clk.tcl | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl index 0ffb3b7e9..dfc112c05 100644 --- a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -67,7 +67,7 @@ common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the va # MIG PRJ FILE TCL PROCs ################################################################## -proc write_mig_file_gen2_polara_fpga_mig_7series_0_0 { str_mig_prj_filepath } { +proc write_mig_file_gen2_polara_fpga_se_clk_mig_7series_0_0 { str_mig_prj_filepath } { file mkdir [ file dirname "$str_mig_prj_filepath" ] set mig_prj_file [open $str_mig_prj_filepath w+] @@ -233,7 +233,7 @@ proc write_mig_file_gen2_polara_fpga_mig_7series_0_0 { str_mig_prj_filepath } { close $mig_prj_file } -# End of write_mig_file_gen2_polara_fpga_mig_7series_0_0() +# End of write_mig_file_gen2_polara_fpga_se_clk_mig_7series_0_0() @@ -340,9 +340,6 @@ proc create_root_design { parentCell } { CONFIG.C_TRI_DEFAULT {0x00000300} \ ] $axi_gpio_0 - # Create instance: ila_0, and set properties - set ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_0 ] - # Create instance: jtag_axi_0, and set properties set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] set_property -dict [ list \ @@ -357,7 +354,7 @@ proc create_root_design { parentCell } { set str_mig_file_name mig_b.prj set str_mig_file_path ${str_mig_folder}/${str_mig_file_name} - write_mig_file_gen2_polara_fpga_mig_7series_0_0 $str_mig_file_path + write_mig_file_gen2_polara_fpga_se_clk_mig_7series_0_0 $str_mig_file_path set_property -dict [ list \ CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ @@ -379,7 +376,6 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] -connect_bd_intf_net -intf_net [get_bd_intf_nets S01_AXI_0_1] [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins ila_0/SLOT_0_AXI] connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus_o] [get_bd_intf_pins axi_gpio_0/GPIO] connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports polara_gen2chipset_bus_i] [get_bd_intf_pins axi_gpio_0/GPIO2] connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] @@ -389,7 +385,7 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets S01_AXI_0_1] [get_bd_intf_ports # Create port connections connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] - connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins ila_0/clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]