Violation of ALU operand forwarding if preceded by FPU multicycle instruction

[dd-baoshan]

There is PC mismatch in one of the fpu failing tests. Initial debug shows that it could be a potential bug in operand forwarding “addi x16 … -> jar x0 x16 …”

The error message as below and it happen for jalr instruction. From the trace log,

• The first jalr reflect the correct X16 value (‘h26be) but it jumped to ‘h26b2 which cause the Imperas mismatch below
• The second jalr reflect the correct X16 value (‘h26be) and it jumped correctly

From wave below

• Red line indicates the start of decoding first jalr
• At M1, fdiv writeback the result to port_b of regfile X4, the addi writeback to x16 is push one cycle later at M2
• At M2, the first jalr uses previous X16 value which is ‘h26b2 as target jump (this caused PC mismatched)
• The same sequence “addi -> jar” happen again at M4, this time it works normally because there is no contention of writeback at port_b between fdiv and addi

Component:RTL

Steps to Reproduce

1. cv32e40p git hash: 7df7d2d
2. core-v-verif git hash: 02ee75284e34acf908dda5344f642a7cb3b0ac0c
3. Users need to checkout below core-v-verif to replicate the issue. The reproduce steps as followings.

git clone --branch cv32e40p/dev_dd https://github.com/XavierAubert/core-v-verif.git sandbox

cd sandbox/cv32e40p/sim/uvmt

make gen_corev-dv test TEST=corev_rand_fp_instr_data_fwd_test CFG_PLUSARGS=+UVM_TIMEOUT=1000000 CHECK_SIM:we_RESULT=YES COMP=1 CV_CORE=cv32e40p COREV=1 CFG=pulp_fpu_zfinx_1cyclat TEST_CFG_FILE=floating_pt_instr_en,floating_pt_zfinx_instr_en SIMULATOR=vsim USE_ISS=yes COV=NO RUN_INDEX=1567674295 GEN_START_INDEX=1567674295 SEED=1567674295

[pascalgouedo]

Corrected with PR #897