where and how does the memory was connected to the other parts of the board in the gem5 components implementation

[gxflying]

Hi sirs:
I fail to find the connection between the memory object and the other objects in the system.
as a common sence, the memory should be connected to the cpu by the cpu_side_port, and be connected to the disk by the mem_side_port
and I find in the abstract_board.py that the memory should be connected in the _connect_things by the method incorporate_memory of the memory,

gem5/src/python/gem5/components/boards/abstract_board.py

Line 355 in 1bb9bb3

self.get_memory().incorporate_memory(self)

BUT all the memory types in the components does nothing in the method which is acctually empy
so how does the memory connected to the other parts of system, and in which method?
hope your reply, thanks

gem5/src/python/gem5/components/memory/simple.py

Line 63 in 1bb9bb3

def incorporate_memory(self, board: AbstractBoard) -> None:

gem5/src/python/gem5/components/memory/dramsim_3.py

Line 107 in 1bb9bb3

def incorporate_memory(self, board: AbstractBoard) -> None:

gem5/src/python/gem5/components/memory/dramsys.py

Line 73 in 1bb9bb3

def incorporate_memory(self, board: AbstractBoard) -> None:

[gxflying]

I think I had find the connecting flow, acctrually the memory connection is done in the cache_hierarchy.incorporate_cache

1. in the abstract.py:: _connect_things , it will call cache_hierarchy::incorporate_cache
   

   gem5/src/python/gem5/components/boards/abstract_board.py

   Line 359 in 1bb9bb3

   self.get_cache_hierarchy().incorporate_cache(self)

   
   every cache_hierarchy under ./src/python/gem5/components/cachehierarchies/ will implemtent a incorporate_cache method , and take private_l1_private_l2_cache_hierarchy.py for example, it will connect the memory, caches, system_port
   

   gem5/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

   Line 118 in 1bb9bb3

   for _, port in board.get_memory().get_mem_ports():