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    15 repositories

    • scgallery

      Public
      SiliconCompiler Design Gallery
      Verilog
      •
      Apache License 2.0
      •2•24•1•2•Updated Jan 27, 2025Jan 27, 2025

    • sc-leflib

      Public
      Cython
      •
      Apache License 2.0
      •0•0•0•2•Updated Jan 27, 2025Jan 27, 2025

    • sc-surelog

      Public
      Python
      •
      Apache License 2.0
      •0•1•0•2•Updated Jan 27, 2025Jan 27, 2025

    • siliconcompiler

      Public
      Modular hardware build system
      Python
      •
      Apache License 2.0
      •89•909•18•6•Updated Jan 27, 2025Jan 27, 2025

    • lambdalib

      Public
      Hardware abstraction library
      Verilog
      •
      MIT License
      •1•23•3•0•Updated Jan 26, 2025Jan 26, 2025

    • lambdapdk

      Public
      Library of open source Process Design Kits (PDKs)
      SourcePawn
      •
      Apache License 2.0
      •4•32•0•0•Updated Jan 24, 2025Jan 24, 2025

    • zerosoc

      Public
      Demo SoC for SiliconCompiler.
      SystemVerilog
      •8•56•5•0•Updated Jan 21, 2025Jan 21, 2025

    • OpenROAD-flow-scripts

      Public archive
      Verilog
      •
      Other
      •299•0•0•0•Updated Dec 11, 2023Dec 11, 2023

    • fossi-foundation.github.io

      Public archive
      FOSSi Foundation Website
      HTML
      •46•0•0•0•Updated Mar 2, 2023Mar 2, 2023

    • Surelog

      Public archive
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •68•0•0•0•Updated Nov 7, 2022Nov 7, 2022

    • sc-education

      Public
      Educational material
      0•3•0•0•Updated Jul 14, 2022Jul 14, 2022

    • cva6

      Public archive
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      C++
      •
      Other
      •717•1•0•0•Updated Jul 10, 2022Jul 10, 2022

    • common_cells

      Public archive
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •150•0•0•0•Updated Jun 30, 2022Jun 30, 2022

    • caravel_wrapper_heartbeat_example

      Public archive
      This repository is a clone of efabless' "caravel_user_project" template. It contains a netlist and GDS file produced by a SiliconCompiler build flow, in a format that allows the MPW pre-tapeout checks to be run on the design.
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated May 18, 2022May 18, 2022

    • sc-rfcs

      Public
      RFCs for changes to SiliconCompiler
      Apache License 2.0
      •0•7•0•0•Updated Oct 29, 2021Oct 29, 2021