diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv index 46caf24e9a..13a99cbbf3 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv @@ -70,14 +70,20 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `define IGNORE_BINS_NON_RD_F_INSTR \ ignore_bins non_rd_f_inst = !binsof(cp_curr_fpu_apu_op) intersect {`APU_INSTR_WITH_NO_FD}; + `define IGNORE_BINS_PREV_NON_FPU_OPCODE_WO_RD \ + ignore_bins prev_non_fpu_wo_rd = !binsof(cp_prev_is_non_fpu_opcode) intersect {`RV32_OPCODE_LIST1_WITH_RD}; + + `define IGNORE_BINS_CUR_FPU_OPCODE_WO_RS1 \ + ignore_bins cur_fpu_wo_rs1 = !binsof(cp_cur_is_fpu_instr) intersect {`RV32F_INSTR_WITH_RS1}; + `define IGNORE_BINS_NON_RS1_F_INSTR_IN_ID \ - ignore_bins non_rs_id_stage_f_inst = !binsof(cp_id_stage_f_inst) intersect {TB_INS_FCVTSW, TB_INS_FCVTSWU}; + ignore_bins non_rs_id_stage_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_RS1}; `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ - ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_INSTR_WITH_NO_RS2}; + ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_OPCODE_WITH_NO_RS2}; `define IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE \ ignore_bins non_stalled_contention_wr_state = binsof(cp_contention_state) intersect {0,1}; @@ -182,7 +188,7 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op_multicycle : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff (`COVIF_CB.apu_busy == 1) { `FPU_OP_BINS - ignore_bins cfg_0cyclat_insns = {`RV32F_OP_WITHOUT_FDIV_FSQRT} with (fpu_latency == 0); + ignore_bins cfg_0cyclat_insns = {`RV32F_OP_WITHOUT_FDIV_FSQRT} with ((item >= 0) && (fpu_latency == 0)); option.weight = 5; } @@ -283,27 +289,44 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 5; } - // from bhv_logic_2 -- only for 1cyclat + // from bhv_logic_1a + // f-ext instr only uses rs1 for xreg + cp_cur_fp_rs1_match_prev_nonfp_rd : coverpoint (cntxt.cov_vif.current_instr_rdata[19:15] == cntxt.cov_vif.previous_instr_rdata[11:7]) + iff (cntxt.cov_vif.current_instr_rdata inside {`RV32F_INSTR_WITH_RS1} && + cntxt.cov_vif.previous_instr_rdata[6:0] inside {`RV32_OPCODE_LIST1_WITH_RD} && + cntxt.cov_vif.current_instr_rdata != cntxt.cov_vif.previous_instr_rdata) { + bins cur_rs1_match_prev_rd = {1}; + } + cp_cur_is_fpu_instr : coverpoint cntxt.cov_vif.current_instr_rdata { + `RV32F_INSTR_BINS + } + cp_prev_is_non_fpu_opcode : coverpoint cntxt.cov_vif.previous_instr_rdata[6:0] { + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_F + } + cp_prev_is_non_fpu_rd : coverpoint cntxt.cov_vif.previous_instr_rdata[11:7] { + bins rd[] = {[0:31]}; + } + + // from bhv_logic_2 cp_last_fpu_apu_op_at_contention : coverpoint cntxt.cov_vif.o_last_fpu_apu_op_if { - bins curr_apu_op_fmadd = {APU_OP_FMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fadd = {APU_OP_FADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fmul = {APU_OP_FMUL} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fdiv = {APU_OP_FDIV} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsqrt = {APU_OP_FSQRT} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fcmp = {APU_OP_FCMP} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_f2f = {APU_OP_F2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_f2i = {APU_OP_F2I} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_i2f = {APU_OP_I2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsub = {APU_OP_FSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmadd = {APU_OP_FMADD} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fadd = {APU_OP_FADD} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fmul = {APU_OP_FMUL} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fdiv = {APU_OP_FDIV} ; + bins curr_apu_op_fsqrt = {APU_OP_FSQRT} ; + bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fcmp = {APU_OP_FCMP} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_f2i = {APU_OP_F2I} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_i2f = {APU_OP_I2F} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fsub = {APU_OP_FSUB} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ((item >= 0) && (fpu_latency != 0)); option.weight = 5; } @@ -392,13 +415,13 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // from bhv_logic_2 (revised) // [optional] this cp is optional as contention has no relation with rd/fd - // note: retain this cp and 100% on cp is not necessary cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { bins rd[] = {[1:31]}; bins fd[] = {[32:63]}; ignore_bins zero = {0}; } + // from bhv_logic_2 cp_contention_state : coverpoint cntxt.cov_vif.contention_state { bins no_contention = {0}; bins contention_1st_cyc_done = {1}; @@ -511,7 +534,7 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 5; `IGNORE_BINS_ZERO_LAT_FPU_OP // only apply in 0cyclat - ignore insn except div and sqrt `IGNORE_BINS_NON_RD_F_INSTR // ignore insn except APU_OP_FCMP, APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_F2I_U in ex_state - `IGNORE_BINS_NON_RS1_F_INSTR_IN_ID // ignore insn except TB_INS_FCVTSW, TB_INS_FCVTSWU in dec_state + `IGNORE_BINS_NON_RS1_F_INSTR_IN_ID // ignore insn except TB_INS_FLW, TB_INS_FSW, TB_INS_FMVSX, TB_INS_FCVTSW, TB_INS_FCVTSWU in dec_state } // cross coverage for Non F-instr following F-instr with rd to rs1 dependency @@ -538,19 +561,30 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `IGNORE_BINS_NON_RS2_CV32E40P_INSTR } + // cross coverage for F-instr following Non F-instr with rd to rs1 dependency + // e.g prev.non_fp(rd) == cur.fp(rs1) + cr_non_rv32f_rd_rv32f_rs1 : cross cp_cur_fp_rs1_match_prev_nonfp_rd, + cp_cur_is_fpu_instr, + cp_prev_is_non_fpu_opcode, + cp_prev_is_non_fpu_rd { + + option.weight = 5; + `IGNORE_BINS_PREV_NON_FPU_OPCODE_WO_RD + `IGNORE_BINS_CUR_FPU_OPCODE_WO_RS1 + } + // cross coverage for contention case 2nd cycle with ALU regfile write cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, cp_contention_state, cp_apu_contention { - bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention with (fpu_latency != 1); - ignore_bins skip_if_other_cfg = cr_waddr_rd_apu_alu_ex_contention with (fpu_latency == 1); + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention with ((cp_contention_state < 3) && (fpu_latency != 1)); + ignore_bins skip_if_other_cfg = cr_waddr_rd_apu_alu_ex_contention with ((cp_contention_state < 3) && (fpu_latency == 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NO_CONTENTION } - //********************************************************************************************************* // CASES WITH/WITHOUT CONTENTION AT APU RESULT WRITE TO REGFILE. APU_LATENCY=0 PRIOIRTY APU WRITE WINS //********************************************************************************************************* @@ -562,8 +596,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_fd_fs1_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_fd_fs1_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_fd_fs1_eq_no_lat with ((cp_fd_fs1_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_fd_fs1_eq_no_lat with ((cp_fd_fs1_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_FD_F_INSTR `IGNORE_BINS_NON_FS1_F_INSTR } @@ -575,8 +609,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_fd_fs2_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_fd_fs2_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_fd_fs2_eq_no_lat with ((cp_fd_fs2_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_fd_fs2_eq_no_lat with ((cp_fd_fs2_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_FD_F_INSTR `IGNORE_BINS_NON_FS2_F_INSTR } @@ -588,8 +622,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_fd_fs3_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_fd_fs3_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_fd_fs3_eq_no_lat with ((cp_fd_fs3_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_fd_fs3_eq_no_lat with ((cp_fd_fs3_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_FD_F_INSTR `IGNORE_BINS_NON_FS3_F_INSTR } @@ -602,8 +636,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rd_rs1_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_RD_F_INSTR `IGNORE_BINS_NON_RS1_F_INSTR_IN_ID } @@ -615,8 +649,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_RD_F_INSTR `IGNORE_BINS_NON_RS1_CV32E40P_INSTR } @@ -627,8 +661,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with ((cp_rd_rs2_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with ((cp_rd_rs2_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_RD_F_INSTR `IGNORE_BINS_NON_RS2_CV32E40P_INSTR } @@ -650,8 +684,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_fd_fs1_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_fd_fs1_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_fd_fs1_eq_nonzero_lat_with_contention with ((cp_fd_fs1_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_fd_fs1_eq_nonzero_lat_with_contention with ((cp_fd_fs1_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_FS1_F_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION @@ -668,8 +702,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_fd_fs2_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_fd_fs2_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_fd_fs2_eq_nonzero_lat_with_contention with ((cp_fd_fs2_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_fd_fs2_eq_nonzero_lat_with_contention with ((cp_fd_fs2_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_FS2_F_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION @@ -686,8 +720,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_fd_fs3_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_fd_fs3_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_fd_fs3_eq_nonzero_lat_with_contention with ((cp_fd_fs3_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_fd_fs3_eq_nonzero_lat_with_contention with ((cp_fd_fs3_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_FS3_F_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION @@ -704,8 +738,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_FS1_F_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR @@ -722,8 +756,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_RS1_CV32E40P_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR @@ -740,8 +774,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with ((cp_rd_rs2_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with ((cp_rd_rs2_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_RS2_CV32E40P_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR @@ -755,8 +789,8 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cp_lsu_apu_contention_wr_rd, cp_apu_contention { - bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_waddr_rd_lsu_apu_wb_contention with (fpu_latency != 1); + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention with ((cp_apu_rvalid == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_waddr_rd_lsu_apu_wb_contention with ((cp_apu_rvalid == 1) && (fpu_latency != 1)); `IGNORE_BINS_NO_CONTENTION_LSU } diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv index 9ba7dd981f..36951e00bd 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv @@ -55,11 +55,20 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; ignore_bins in_contention_lsu_wr = ( binsof(cp_apu_contention) intersect {1} ) \ with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 1)) != 0 ); + `define IGNORE_BINS_PREV_NON_FPU_OPCODE_WO_RD \ + ignore_bins prev_non_fpu_wo_rd = !binsof(cp_prev_is_non_fpu_opcode) intersect {`RV32_OPCODE_LIST1_WITH_RD}; + + `define IGNORE_BINS_CUR_FPU_OPCODE_WO_RS2 \ + ignore_bins cur_fpu_wo_rs2 = !binsof(cp_cur_is_fpu_instr) intersect {`RV32ZFINX_INSTR_W_RS2}; + + `define IGNORE_BINS_CUR_FPU_OPCODE_WO_RS3 \ + ignore_bins cur_fpu_wo_rs3 = !binsof(cp_cur_is_fpu_instr) intersect {`RV32ZFINX_INSTR_W_RS3}; + `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ - ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_INSTR_WITH_NO_RS2}; + ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_OPCODE_WITH_NO_RS2}; `define IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE \ ignore_bins non_stalled_contention_wr_state = binsof(cp_contention_state) intersect {0,1}; @@ -71,10 +80,10 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; ignore_bins no_contention = binsof(cp_apu_contention) intersect {1}; `define IGNORE_BINS_NON_RS2_ZFINX_INSTR \ - ignore_bins non_rs2_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_FS2}; + ignore_bins non_rs2_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32ZFINX_INSTR_W_RS2}; `define IGNORE_BINS_NON_RS3_ZFINX_INSTR \ - ignore_bins non_rs3_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_FS3}; + ignore_bins non_rs3_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32ZFINX_INSTR_W_RS3}; `define IGNORE_BINS_NO_CONTENTION_LSU \ ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; @@ -102,6 +111,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; option.weight = 5; } + // from bhv_logic_1 cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window iff ((`COVIF_CB.is_mulh_ex == 0) && (`COVIF_CB.is_misaligned_data_req_ex == 0) && (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && @@ -154,11 +164,13 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins apu_busy_high = {1'b1}; } + // from bhv_logic_1 cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { `ZFINX_OP_BINS option.weight = 5; } + // from bhv_logic_1 cp_curr_fpu_apu_op_at_apu_req : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff ( (`COVIF_CB.apu_req == 1) && (`COVIF_CB.apu_gnt == 1) ) { @@ -166,6 +178,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; option.weight = 5; } + // from bhv_logic_1 cp_curr_fpu_apu_op_multicycle : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff (`COVIF_CB.apu_busy == 1) { `ZFINX_OP_BINS @@ -288,31 +301,61 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins has_contention = {1}; } + // from bhv_logic_1 cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { `ZFINX_OP_BINS option.weight = 5; } + // from bhv_logic_1a + // all instr in zfinx with rs1/2/3 + cp_cur_fp_rs1_match_prev_nonfp_rd : coverpoint (cntxt.cov_vif.current_instr_rdata[19:15] == cntxt.cov_vif.previous_instr_rdata[11:7]) + iff (cntxt.cov_vif.previous_instr_rdata[6:0] inside {`RV32_OPCODE_LIST1_WITH_RD} && + cntxt.cov_vif.current_instr_rdata != cntxt.cov_vif.previous_instr_rdata) { + bins cur_rs1_match_prev_rd = {1}; + } + cp_cur_fp_rs2_match_prev_nonfp_rd : coverpoint (cntxt.cov_vif.current_instr_rdata[24:20] == cntxt.cov_vif.previous_instr_rdata[11:7]) + iff (cntxt.cov_vif.current_instr_rdata inside {`RV32ZFINX_INSTR_W_RS2} && + cntxt.cov_vif.previous_instr_rdata[6:0] inside {`RV32_OPCODE_LIST1_WITH_RD} && + cntxt.cov_vif.current_instr_rdata != cntxt.cov_vif.previous_instr_rdata) { + bins cur_rs2_match_prev_rd = {1}; + } + cp_cur_fp_rs3_match_prev_nonfp_rd : coverpoint (cntxt.cov_vif.current_instr_rdata[31:27] == cntxt.cov_vif.previous_instr_rdata[11:7]) + iff (cntxt.cov_vif.current_instr_rdata inside {`RV32ZFINX_INSTR_W_RS3} && + cntxt.cov_vif.previous_instr_rdata[6:0] inside {`RV32_OPCODE_LIST1_WITH_RD} && + cntxt.cov_vif.current_instr_rdata != cntxt.cov_vif.previous_instr_rdata) { + bins cur_rs3_match_prev_rd = {1}; + } + cp_cur_is_fpu_instr : coverpoint cntxt.cov_vif.current_instr_rdata { + `ZFINX_INSTR_BINS + } + cp_prev_is_non_fpu_opcode : coverpoint cntxt.cov_vif.previous_instr_rdata[6:0] { + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_F + } + cp_prev_is_non_fpu_rd : coverpoint cntxt.cov_vif.previous_instr_rdata[11:7] { + bins rd[] = {[0:31]}; + } + + // from bhv_logic_2 cp_last_fpu_apu_op_at_contention : coverpoint cntxt.cov_vif.o_last_fpu_apu_op_if { - bins curr_apu_op_fmadd = {APU_OP_FMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fadd = {APU_OP_FADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fmul = {APU_OP_FMUL} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fdiv = {APU_OP_FDIV} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsqrt = {APU_OP_FSQRT} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fcmp = {APU_OP_FCMP} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_f2f = {APU_OP_F2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_f2i = {APU_OP_F2I} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_i2f = {APU_OP_I2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsub = {APU_OP_FSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); - bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmadd = {APU_OP_FMADD} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fadd = {APU_OP_FADD} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fmul = {APU_OP_FMUL} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fdiv = {APU_OP_FDIV} ; + bins curr_apu_op_fsqrt = {APU_OP_FSQRT} ; + bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fcmp = {APU_OP_FCMP} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_f2i = {APU_OP_F2I} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_i2f = {APU_OP_I2F} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fsub = {APU_OP_FSUB} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ((item >= 0) && (fpu_latency != 0)); + bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ((item >= 0) && (fpu_latency != 0)); option.weight = 5; } @@ -344,21 +387,25 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins fs2[] = {[0:31]}; } + // from bhv_logic_3 cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { bins fd[] = {[0:31]}; } + // from bhv_logic_3 cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { bins rd[] = {[0:31]}; } + // from bhv_logic_3 cp_curr_fpu_inst_rd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd iff ( (`COVIF_CB.apu_req == 1) && (`COVIF_CB.apu_gnt == 1) && (`COVIF_CB.apu_rvalid_i == 1) ) { - bins rd[] = {[0:31]} with (fpu_latency == 0); + bins rd[] = {[0:31]} with ((item >= 0) && (fpu_latency == 0)); } + // from bhv_logic_3 cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd iff ( (`COVIF_CB.apu_busy == 1) && (`COVIF_CB.apu_rvalid_i == 1) ) { @@ -371,11 +418,14 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; illegal_bins rd_addr_32_63 = {[32:63]}; } + // from bhv_logic_3 cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency == 1) ); illegal_bins rd_addr_32_63 = {[32:63]}; } + // from bhv_logic_2 (revised) + // [optional] this cp is optional as contention has no relation with rd/fd cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { bins rd[] = {[0:31]}; illegal_bins rd_addr_32_63 = {[32:63]}; //for zfinx only 32 gprs available @@ -393,18 +443,24 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins b2b_contention_true = {1}; } + // from bhv_logic_3 + // next fp_insn rs1 is rd of current fp_insn cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) iff (`COVIF_CB.id_stage_instr_valid_i == 1) { bins rd_rs1_equal = {1}; } + // from bhv_logic_3 + // next fp_insn rs2 is rd of current fp_insn cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) iff (`COVIF_CB.id_stage_instr_valid_i == 1) { bins rd_rs2_equal = {1}; } + // from bhv_logic_3 + // next fp_insn rs3 is rd of current fp_insn cp_rd_rs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_rd) iff (`COVIF_CB.id_stage_instr_valid_i == 1) { @@ -483,13 +539,44 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; `IGNORE_BINS_NON_RS2_CV32E40P_INSTR } + // cross coverage for F-instr following Non F-instr with rd to rs dependency + // e.g prev.non_fp(rd) == cur.fp(rs1/2/3) + cr_non_rv32f_rd_rv32f_rs1 : cross cp_cur_fp_rs1_match_prev_nonfp_rd, + cp_cur_is_fpu_instr, + cp_prev_is_non_fpu_opcode, + cp_prev_is_non_fpu_rd { + + option.weight = 5; + // e.g bin that ignore combination of cur and prev instr (this can reduce cross bins number drastically) + // bins op_fwd_xreg0 = binsof(cp_prev_is_non_fpu_rd) intersect {0} && binsof(cp_cur_fp_rs1_match_prev_nonfp_rd); + `IGNORE_BINS_PREV_NON_FPU_OPCODE_WO_RD + } + cr_non_rv32f_rd_rv32f_rs2 : cross cp_cur_fp_rs2_match_prev_nonfp_rd, + cp_cur_is_fpu_instr, + cp_prev_is_non_fpu_opcode, + cp_prev_is_non_fpu_rd { + + option.weight = 5; + `IGNORE_BINS_PREV_NON_FPU_OPCODE_WO_RD + `IGNORE_BINS_CUR_FPU_OPCODE_WO_RS2 + } + cr_non_rv32f_rd_rv32f_rs3 : cross cp_cur_fp_rs3_match_prev_nonfp_rd, + cp_cur_is_fpu_instr, + cp_prev_is_non_fpu_opcode, + cp_prev_is_non_fpu_rd { + + option.weight = 5; + `IGNORE_BINS_PREV_NON_FPU_OPCODE_WO_RD + `IGNORE_BINS_CUR_FPU_OPCODE_WO_RS3 + } + // cross coverage for contention case 2nd cycle with ALU regfile write cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, cp_contention_state, cp_apu_contention { - bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention with (fpu_latency != 1); - ignore_bins skip_if_other_cfg = cr_waddr_rd_apu_alu_ex_contention with (fpu_latency == 1); + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention with ((cp_contention_state < 3) && (fpu_latency != 1)); + ignore_bins skip_if_other_cfg = cr_waddr_rd_apu_alu_ex_contention with ((cp_contention_state < 3) && (fpu_latency == 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NO_CONTENTION @@ -500,8 +587,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_contention_state, cp_apu_contention { - bins main_cr_bin = cr_contention_rd_rd_eq with (fpu_latency != 1); - ignore_bins skip_if_other_cfg = cr_contention_rd_rd_eq with (fpu_latency == 1); + bins main_cr_bin = cr_contention_rd_rd_eq with ((cp_contention_state < 3) && (fpu_latency != 1)); + ignore_bins skip_if_other_cfg = cr_contention_rd_rd_eq with ((cp_contention_state < 3) && (fpu_latency == 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NO_CONTENTION @@ -513,8 +600,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_contention_state, cp_apu_contention { - bins main_cr_bin = cr_contention_rd_rd_eq_fpu_lat_1 with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_contention_rd_rd_eq_fpu_lat_1 with (fpu_latency != 1); + bins main_cr_bin = cr_contention_rd_rd_eq_fpu_lat_1 with ((cp_contention_state < 3) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_contention_rd_rd_eq_fpu_lat_1 with ((cp_contention_state < 3) && (fpu_latency != 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NO_CONTENTION @@ -531,8 +618,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rd_rs1_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency != 0)); } // cross coverage for F-instr following F-instr with rd to rs2 dependency - 0 Latency @@ -542,8 +629,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rd_rs2_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rd_rs2_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rd_rs2_eq_no_lat with ((cp_rd_rs2_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rd_rs2_eq_no_lat with ((cp_rd_rs2_eq == 1) && (fpu_latency != 0)); } // cross coverage for F-instr following F-instr with rd to rs3 dependency - 0 Latency @@ -553,8 +640,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rd_rs3_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rd_rs3_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rd_rs3_eq_no_lat with ((cp_rd_rs3_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rd_rs3_eq_no_lat with ((cp_rd_rs3_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_RS3_ZFINX_INSTR } @@ -565,8 +652,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with ((cp_rd_rs1_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_RS1_CV32E40P_INSTR } // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - 0 Latency @@ -576,8 +663,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_curr_fpu_apu_op { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with (fpu_latency == 0); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with (fpu_latency != 0); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with ((cp_rd_rs2_eq == 1) && (fpu_latency == 0)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with ((cp_rd_rs2_eq == 1) && (fpu_latency != 0)); `IGNORE_BINS_NON_RS2_CV32E40P_INSTR } @@ -595,8 +682,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rd_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR } @@ -611,8 +698,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rd_rs2_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rd_rs2_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rd_rs2_eq_nonzero_lat_with_contention with ((cp_rd_rs2_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rd_rs2_eq_nonzero_lat_with_contention with ((cp_rd_rs2_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR } @@ -627,8 +714,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rd_rs3_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rd_rs3_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rd_rs3_eq_nonzero_lat_with_contention with ((cp_rd_rs3_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rd_rs3_eq_nonzero_lat_with_contention with ((cp_rd_rs3_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR } @@ -643,8 +730,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention with ((cp_rd_rs1_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_RS1_CV32E40P_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR @@ -660,8 +747,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_apu_contention { option.weight = 5; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with (fpu_latency != 1); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with ((cp_rd_rs2_eq == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention with ((cp_rd_rs2_eq == 1) && (fpu_latency != 1)); `IGNORE_BINS_NON_RS2_CV32E40P_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR @@ -674,8 +761,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_lsu_apu_contention_wr_rd, cp_apu_contention { - bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention with (fpu_latency == 1); - ignore_bins skip_if_other_cfg = cr_waddr_rd_lsu_apu_wb_contention with (fpu_latency != 1); + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention with ((cp_apu_rvalid == 1) && (fpu_latency == 1)); + ignore_bins skip_if_other_cfg = cr_waddr_rd_lsu_apu_wb_contention with ((cp_apu_rvalid == 1) && (fpu_latency != 1)); `IGNORE_BINS_NO_CONTENTION_LSU } endgroup : cg_zfinx_inst_reg diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index a9be725755..a2acffa133 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -788,7 +788,7 @@ class uvme_rv32x_hwloop_covg # ( endfunction : check_ebreakm_entry function void check_exception_exit(); - if (cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET) begin + if (cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET && !cv32e40p_rvvi_vif.trap) begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Exit"), UVM_DEBUG); end @@ -880,7 +880,7 @@ class uvme_rv32x_hwloop_covg # ( discarded_insn = insn_list_in_hwloop_main[j].pop_back(); assert(discarded_insn == INSN_EBREAKM); void'(hwloop_evt_loc_main[j][DBG_EBREAKM].pop_back()); - hwloop_stat_main.track_lp_cnt[j]++; lpend_has_pending_irq_main[j] = 0; + hwloop_stat_main.track_lp_cnt[j]++; lpend_has_pending_irq_main[j] = 0; end end // for end @@ -986,6 +986,8 @@ class uvme_rv32x_hwloop_covg # ( `IF_CURRENT_IS_MAIN_HWLOOP(1, IS_IRQ) update_prev_irq_onehot_priority(); `uvm_info(_header, $sformatf("DEBUG - IRQ Entry"), UVM_DEBUG); + if (lpend_has_pending_irq_main[0]) begin hwloop_stat_main.track_lp_cnt[0]++; lpend_has_pending_irq_main[0] = 0; end + if (lpend_has_pending_irq_main[1]) begin hwloop_stat_main.track_lp_cnt[1]++; lpend_has_pending_irq_main[1] = 0; end is_irq = 1; wait (!is_irq); continue; end end // IRQ_ENTRY @@ -1021,7 +1023,7 @@ class uvme_rv32x_hwloop_covg # ( `uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_DEBUG); end else begin - `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); // fixme: to be commented out + `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); end endfunction : final_phase diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv index 6eee3ebbec..ccb29cce97 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv @@ -27,8 +27,13 @@ `define APU_INSTR_WITH_NO_FD \ APU_OP_FCMP, APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_F2I_U -`define RV32_INSTR_WITH_NO_RS2 \ - TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM + // LIST1 is CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_F +`define RV32_OPCODE_LIST1_WITH_RD \ + TB_OPCODE_OP, TB_OPCODE_OPIMM, TB_OPCODE_LOAD, TB_OPCODE_JALR, TB_OPCODE_JAL, TB_OPCODE_AUIPC, TB_OPCODE_LUI, \ + OPCODE_CUSTOM_0, OPCODE_CUSTOM_1, OPCODE_CUSTOM_2, OPCODE_CUSTOM_3 + +`define RV32_OPCODE_WITH_NO_RS2 \ + TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM `define RV32F_INSTR_WITH_FS1 \ TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB, TB_INS_FADD, TB_INS_FSUB, TB_INS_FMUL, TB_INS_FDIV, TB_INS_FSQRT, \ @@ -43,6 +48,13 @@ `define RV32F_INSTR_WITH_FS3 \ TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB +`define RV32F_INSTR_WITH_RS1 \ + TB_INS_FLW, TB_INS_FSW, TB_INS_FMVSX, TB_INS_FCVTSW, TB_INS_FCVTSWU + +// `define RV32ZFINX_INSTR_W_RS1 `RV32F_INSTR_WITH_FS1 +`define RV32ZFINX_INSTR_W_RS2 `RV32F_INSTR_WITH_FS2 +`define RV32ZFINX_INSTR_W_RS3 `RV32F_INSTR_WITH_FS3 + `define RV32F_OP_WITHOUT_FDIV_FSQRT \ APU_OP_FMADD, APU_OP_FNMSUB, APU_OP_FADD, APU_OP_FMUL, APU_OP_FSGNJ, APU_OP_FMINMAX, APU_OP_FCMP, \ APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_I2F, APU_OP_FMSUB, APU_OP_FNMADD, APU_OP_FSUB, APU_OP_FSGNJ_SE, \ @@ -61,14 +73,14 @@ wildcard bins fmax = {TB_INS_FMAX}; \ wildcard bins fcvtws = {TB_INS_FCVTWS}; \ wildcard bins fcvtwus = {TB_INS_FCVTWUS}; \ - wildcard bins fmvxs = {TB_INS_FMVXS}; \ + wildcard bins fmvxw = {TB_INS_FMVXS}; \ wildcard bins feqs = {TB_INS_FEQS}; \ wildcard bins flts = {TB_INS_FLTS}; \ wildcard bins fles = {TB_INS_FLES}; \ wildcard bins fclass = {TB_INS_FCLASS}; \ wildcard bins fcvtsw = {TB_INS_FCVTSW}; \ wildcard bins fcvtswu = {TB_INS_FCVTSWU}; \ - wildcard bins fmvsw = {TB_INS_FMVSX}; \ + wildcard bins fmvwx = {TB_INS_FMVSX}; \ wildcard bins fmadd = {TB_INS_FMADD}; \ wildcard bins fmsub = {TB_INS_FMSUB}; \ wildcard bins fnmsub = {TB_INS_FNMSUB}; \ @@ -234,6 +246,7 @@ // bins apu_op_fsgnj_se = {APU_OP_FSGNJ_SE}; \ exclude this from macro because it is fmv for RV32F // bins apu_op_f2f = {APU_OP_F2F}; \ exclude this from above macro because it is for RV32D +// cv32e40p opcode (exclude compress and f-compress) `define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC \ bins system_opcode = {TB_OPCODE_SYSTEM}; \ bins fence_opcode = {TB_OPCODE_FENCE}; \ @@ -258,6 +271,7 @@ bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \ bins xpulp_custom_3 = {OPCODE_CUSTOM_3}; +// cv32e40p opcode (exclude compress, f-compress, f-load/store) `define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_FPLS \ bins system_opcode = {TB_OPCODE_SYSTEM}; \ bins fence_opcode = {TB_OPCODE_FENCE}; \ @@ -280,6 +294,24 @@ bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \ bins xpulp_custom_3 = {OPCODE_CUSTOM_3}; +// cv32e40p opcode (exclude compress, f-compress and f) +`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_F \ + bins system_opcode = {TB_OPCODE_SYSTEM}; \ + bins fence_opcode = {TB_OPCODE_FENCE}; \ + bins op_opcode = {TB_OPCODE_OP}; \ + bins opimm_opcode = {TB_OPCODE_OPIMM}; \ + bins store_opcode = {TB_OPCODE_STORE}; \ + bins load_opcode = {TB_OPCODE_LOAD}; \ + bins branch_opcode = {TB_OPCODE_BRANCH}; \ + bins jalr_opcode = {TB_OPCODE_JALR}; \ + bins jal_opcode = {TB_OPCODE_JAL}; \ + bins auipc_opcode = {TB_OPCODE_AUIPC}; \ + bins lui_opcode = {TB_OPCODE_LUI}; \ + bins xpulp_custom_0 = {OPCODE_CUSTOM_0}; \ + bins xpulp_custom_1 = {OPCODE_CUSTOM_1}; \ + bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \ + bins xpulp_custom_3 = {OPCODE_CUSTOM_3}; + `define RV32X_PULP_INSTR_BINS \ wildcard bins cv_lb_pi_ri = {INSTR_CV_LB_PI_RI}; \ wildcard bins cv_lh_pi_ri = {INSTR_CV_LH_PI_RI}; \ diff --git a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml index 5d02f3f7d2..7924e8d991 100644 --- a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml +++ b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml @@ -26,6 +26,7 @@ tests: description: This test is to improve func coverage holes in uvme_interrupt_covg_v2 dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_directed_for_interrupt_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + skip_sim: pulp num: 5 corev_directed_for_hwloop_covg_test: diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index f16decb345..d82dbac2a0 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -437,3 +437,47 @@ tests: dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=riscv_ebreak_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 + + + # fixme: temporary park here for regression purpose. need to reloacate again once below tests are stable + corev_directed_for_interrupt_covg_test: + build: uvmt_cv32e40p + description: This test is to improve func coverage holes in uvme_interrupt_covg_v2 + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_directed_for_interrupt_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + skip_sim: pulp + num: 5 + + corev_directed_for_hwloop_covg_test: + description: This test is to improve func coverage holes in uvme_rv32x_hwloop_covg + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_for_hwloop_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=60000000" + num: 5 + + corev_directed_fp_mulcyc_interleave_illegal_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: This test is to improve func coverage holes in uvme_debug_covg + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" VSIM_USER_FLAGS=+add_b2b_illegal_insn + test_cfg: gen_rand_int + skip_sim: pulp + num: 1 + + corev_directed_fp_mulcyc_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: This test is to improve func coverage holes in uvme_debug_covg + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int + skip_sim: pulp + num: 5 + + debug_test_trigger: + build: uvmt_cv32e40p + description: This custom legacy test is needed to improve func coverage holes in uvme_debug_covg + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=debug_test_trigger + num: 1 diff --git a/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml b/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml new file mode 100644 index 0000000000..512c98ee33 --- /dev/null +++ b/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml @@ -0,0 +1,209 @@ +name: cv32e40pv2_legacy_v1 +description: regression for CV32E40Pv2, containing all tests not in any of other v2 files, which focus mainly on legacy + +# List of builds +builds: + clean_fw: + cmd: make clean-bsp clean_test_programs + dir: cv32e40p/sim/uvmt + clean_corev-dv: + cmd: make clean_riscv-dv clone_riscv-dv + dir: cv32e40p/sim/uvmt + uvmt_cv32e40p: + cmd: make comp comp_corev-dv + dir: cv32e40p/sim/uvmt + cfg: pulp + +# List of tests +tests: +################################################################################################### +############ START List of tests that are not in any of the 4 files mentionned above + + hello-world: + build: uvmt_cv32e40p + description: world + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=hello-world CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + corev_rand_arithmetic_base_test: + build: uvmt_cv32e40p + description: corev_rand_arithmetic_base_test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_arithmetic_base_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + corev_rand_illegal_instr_test: + build: uvmt_cv32e40p + description: corev_rand_illegal_instr_test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_illegal_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + corev_rand_instr_long_stall: + build: uvmt_cv32e40p + description: corev_rand_instr_long_stall + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_long_stall CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + corev_rand_instr_test: + build: uvmt_cv32e40p + description: corev_rand_instr_test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + corev_rand_jump_stress_test: + build: uvmt_cv32e40p + description: corev_rand_jump_stress_test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_jump_stress_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + all_csr_por: + build: uvmt_cv32e40p + description: all_csr_por + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=all_csr_por CFG_PLUSARGS="+UVM_TIMEOUT=300000000" + + branch_zero: + build: uvmt_cv32e40p + description: branch_zero + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=branch_zero CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + csr_instr_asm: + build: uvmt_cv32e40p + description: csr_instr_asm + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=csr_instr_asm CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + coremark: + build: uvmt_cv32e40p + description: coremark + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=coremark CFG_PLUSARGS="+UVM_TIMEOUT=3000000000" + + cv32e40p_readonly_csr_access_test: + build: uvmt_cv32e40p + description: cv32e40p_readonly_csr_access_test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=cv32e40p_readonly_csr_access_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + debug_test_trigger: + build: uvmt_cv32e40p + description: debug_test_trigger + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=debug_test_trigger CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + dhrystone: + build: uvmt_cv32e40p + description: dhrystone + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=dhrystone CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + fibonacci: + build: uvmt_cv32e40p + description: fibonacci + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=fibonacci CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + generic_exception_test: + build: uvmt_cv32e40p + description: generic_exception_test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=generic_exception_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + hpmcounter_basic_test: + build: uvmt_cv32e40p + description: hpmcounter_basic_test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=hpmcounter_basic_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + hpmcounter_hazard_test: + build: uvmt_cv32e40p + description: hpmcounter_hazard_test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=hpmcounter_hazard_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + illegal: + build: uvmt_cv32e40p + description: illegal + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=illegal CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + illegal_instr_test: + build: uvmt_cv32e40p + description: illegal_instr_test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=illegal_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=3000000000" + + isa_fcov_holes: + build: uvmt_cv32e40p + description: isa_fcov_holes + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=isa_fcov_holes CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + load_store_rs1_zero: + build: uvmt_cv32e40p + description: load_store_rs1_zero + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=load_store_rs1_zero CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + matmul_32b_float: + build: uvmt_cv32e40p + description: matmul_32b_float + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=matmul_32b_float CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + matmul_32b_int: + build: uvmt_cv32e40p + description: matmul_32b_int + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=matmul_32b_int CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + mhpmcounter29_csr_access_test_1: + build: uvmt_cv32e40p + description: mhpmcounter29_csr_access_test_1 + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1 CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + mhpmcounter29_csr_access_test_2: + build: uvmt_cv32e40p + description: mhpmcounter29_csr_access_test_2 + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2 CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + misalign: + build: uvmt_cv32e40p + description: misalign + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=misalign CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + modeled_csr_por: + build: uvmt_cv32e40p + description: modeled_csr_por + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=modeled_csr_por CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + perf_counters_instructions: + build: uvmt_cv32e40p + description: perf_counters_instructions + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=perf_counters_instructions CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + requested_csr_por: + build: uvmt_cv32e40p + description: requested_csr_por + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=requested_csr_por CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + riscv_arithmetic_basic_test_0: + build: uvmt_cv32e40p + description: riscv_arithmetic_basic_test_0 + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=riscv_arithmetic_basic_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + riscv_arithmetic_basic_test_1: + build: uvmt_cv32e40p + description: riscv_arithmetic_basic_test_1 + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=riscv_arithmetic_basic_test_1 CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + +############ END List of tests that are not in any of the v2 regress list +################################################################################################### diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 01a5c52dc3..74aaeb8897 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -127,12 +127,31 @@ tests: cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" VSIM_USER_FLAGS="+random_instr_stall +random_data_stall +tb_hack_1_obi_gnt_signal" num: 1 - # pulp_hardware_loop_debug_test: - # build: uvmt_cv32e40p - # description: pulp_hardware_loop directed test - # dir: cv32e40p/sim/uvmt - # cmd: make test COREV=YES TEST=pulp_hardware_loop_debug_test - # num: 1 + jalr_test: + build: uvmt_cv32e40p + description: directed test to cover all stall case for JALR + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=jalr_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 + + pulp_hardware_loop_debug_test: + build: uvmt_cv32e40p + description: pulp_hardware_loop directed test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=pulp_hardware_loop_debug_test + num: 1 + skip_sim: + - pulp + - pulp_fpu + - pulp_fpu_1cyclat + - pulp_fpu_2cyclat + - pulp_cluster + - pulp_cluster_fpu + - pulp_cluster_fpu_1cyclat + - pulp_cluster_fpu_2cyclat + - default + - no_pulp + # ==================================================================================== # V1 legacy pulp tests diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index 7be759d809..3a989338f0 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -7,3 +7,271 @@ coverage exclude -line 1280 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 1300 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} coverage exclude -line 1301 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} coverage exclude -line 1302 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 150 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 201 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 202 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 203 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 209 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 210 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 211 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 213 -code b -allfalse -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 213 -code b -item 1 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 214 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 215 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 215 -code b -item 1 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 215 -code b -allfalse -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 216 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 217 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 226 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 227 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 228 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 229 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 292 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 416 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 424 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 425 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} +coverage exclude -line 458 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {flush_i set to 1'b0} +coverage exclude -line 458 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {flush_i set to 1'b0} +coverage exclude -line 460 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {reg_ena_i is stuck to 0} +coverage exclude -line 464 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {Tag is stuck at 0} +coverage exclude -line 465 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {Mask is stuck at 0} +coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} +coverage exclude -line 59 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} +coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} +coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} +coverage exclude -line 59 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} +coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} +coverage exclude -line 148 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.} +coverage exclude -line 149 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.} +coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {idu_fpu_ex1_eu_sel is 0 or 4. idu_fpu_ex1_eu_sel[1] is always 0.} +coverage exclude -line 155 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_src2_vld never asserted. This is expression 151.} +coverage exclude -line 240 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0001. ex1_result_qnan_op0. This is always 0, comes from fdsu_special lines 282 and 294.} +coverage exclude -line 240 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0001. ex1_result_qnan_op0. This is always 0, comes from fdsu_special lines 282 and 294.} +coverage exclude -line 241 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0010. ex1_result_qnan_op1. This is always 0, comes from fdsu_special lines 289 and 301.} +coverage exclude -line 241 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0010. ex1_result_qnan_op1. This is always 0, comes from fdsu_special lines 289 and 301.} +coverage exclude -line 242 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0100. ex1_special_sel[7] is stuck to 0.} +coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0100. ex1_special_sel[7] is stuck to 0.} +coverage exclude -line 266 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Never stall and never warm up. Stuck to 0.} +coverage exclude -line 282 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is ex1_special_sel[0] which is stuck to 0.} +coverage exclude -line 282 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is ex1_special_sel[0] which is stuck to 0.} +coverage exclude -line 285 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is ex1_special_sel[3] ex1_result_lfn which is stuck to 0 in fdsu_special.} +coverage exclude -line 285 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is ex1_special_sel[3] ex1_result_lfn which is stuck to 0 in fdsu_special.} +coverage exclude -line 287 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is |ex1_special_sel[7:5]. 7 is stuck to 0. 6 is ex1_result_qnan_op1. 5 is ex1_result_qnan_op0. This will always be 0.} +coverage exclude -line 287 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is |ex1_special_sel[7:5]. 7 is stuck to 0. 6 is ex1_result_qnan_op1. 5 is ex1_result_qnan_op0. This will always be 0.} +coverage exclude -line 288 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is ex1_special_sel[8] which is stuck to 0.} +coverage exclude -line 288 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {Missing some ex2_special_sel. This is ex1_special_sel[8] which is stuck to 0.} +coverage exclude -line 359 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 360 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 397 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never ctrl_sm_start when in PACK state. We start when operand is ready. Core is waiting for result before sending new instruction and new operand.} +coverage exclude -line 398 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never ctrl_sm_start when in PACK state. We start when operand is ready. Core is waiting for result before sending new instruction and new operand.} +coverage exclude -line 399 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never ctrl_sm_start when in PACK state. We start when operand is ready. Core is waiting for result before sending new instruction and new operand.} +coverage exclude -line 400 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never ctrl_sm_start when in PACK state. We start when operand is ready. Core is waiting for result before sending new instruction and new operand.} +coverage exclude -line 401 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never ctrl_sm_start when in PACK state. We start when operand is ready. Core is waiting for result before sending new instruction and new operand.} +coverage exclude -line 404 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {fdsu_wb_grant always asserted in PACK state. With the way things are looped back, we will always have this asserted during PACK. We will never go to WFWB state.} +coverage exclude -line 405 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {fdsu_wb_grant always asserted in PACK state. With the way things are looped back, we will always have this asserted during PACK. We will never go to WFWB state.} +coverage exclude -line 407 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 409 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 410 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 411 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 412 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 413 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 414 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 416 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 417 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 418 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 431 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 433 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} +coverage exclude -line 443 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 444 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 464 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 465 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 483 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 484 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} +coverage exclude -line 540 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Both signal are acctually the same via external connection.} +coverage exclude -line 637 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {async_flush is stuck to 0. warm_up is stuck to 0. ex1_cancel is suck to 0. ex2_cancel is stuck to 0. We will never flush.} +coverage exclude -line 648 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {rtu_yy_xx_flush stuck to 0. fdsu_busy cannot be low if ctrl_sm_idle is low.} +coverage exclude -line 754 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} +coverage exclude -line 755 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} +coverage exclude -line 756 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} +coverage exclude -line 757 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} +coverage exclude -line 280 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 280 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 282 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 283 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 284 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 286 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 286 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 288 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 289 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 290 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 292 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 292 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 294 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 295 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 296 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 298 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 298 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 300 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 301 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 301 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 302 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 302 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 294 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 296 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} +coverage exclude -line 63 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 63 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 64 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 64 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 65 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 65 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 66 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 66 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 67 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 67 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 68 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 68 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 69 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 69 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 70 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 70 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 71 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 71 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 72 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 72 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 73 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 73 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 74 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 74 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 75 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 75 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 76 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 76 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 77 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 77 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 78 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 78 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 79 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 79 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 80 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 80 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 81 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 81 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 82 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 83 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 83 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 84 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 84 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 85 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 85 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 86 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 86 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 87 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 87 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 88 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 88 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 89 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 89 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 90 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 90 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 91 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 91 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 125 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 125 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 126 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 126 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 127 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 127 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 128 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 128 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 129 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 129 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 130 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 130 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 131 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 131 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 132 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 132 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 133 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 133 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 134 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 134 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 135 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 135 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 136 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 136 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 137 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 137 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 138 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 138 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 139 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 139 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 140 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 140 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 141 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 141 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 142 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 142 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 143 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 143 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 144 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 144 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 145 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 145 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 146 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 146 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 147 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 147 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 148 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 148 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 149 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 149 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 150 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 150 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 151 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 151 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 152 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 152 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 153 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 153 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} +coverage exclude -line 93 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {Default is unreachble. Case is already complete.} +coverage exclude -line 93 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {Default is unreachble. Case is already complete.} +coverage exclude -line 155 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {Default is unreachble. Case is already complete.} +coverage exclude -line 155 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {Default is unreachble. Case is already complete.} +coverage exclude -line 139 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_pack} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 139 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_pack} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 218 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_pack} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 218 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_pack} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 410 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default case never reached. This is looking at rounding mode. We always have 3'b000, 3'b001, 3'b010, 3'b011, 3'b100. Those are all the legal value.} +coverage exclude -line 412 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default case never reached. This is looking at rounding mode. We always have 3'b000, 3'b001, 3'b010, 3'b011, 3'b100. Those are all the legal value.} +coverage exclude -line 413 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default case never reached. This is looking at rounding mode. We always have 3'b000, 3'b001, 3'b010, 3'b011, 3'b100. Those are all the legal value.} +coverage exclude -line 414 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default case never reached. This is looking at rounding mode. We always have 3'b000, 3'b001, 3'b010, 3'b011, 3'b100. Those are all the legal value.} +coverage exclude -line 415 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default case never reached. This is looking at rounding mode. We always have 3'b000, 3'b001, 3'b010, 3'b011, 3'b100. Those are all the legal value.} +coverage exclude -line 435 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 437 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 438 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_round} -comment {Default is unreachable. Case is already complete.} +coverage exclude -line 279 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/gen_parallel_slices[0]/active_format/i_fmt_slice} -comment {No vector floating point.} +coverage exclude -line 139 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/conv_target} -comment {We never use cast and pack.} +coverage exclude -line 207 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} +coverage exclude -line 207 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} +coverage exclude -line 208 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} +coverage exclude -line 208 -code b -allfalse -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} +coverage exclude -line 209 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} +coverage exclude -line 213 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {We never use cast and pack.} +coverage exclude -line 458 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/target_regs} -comment {No vector floating point operation.} +coverage exclude -line 476 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/target_regs} -comment {No vector floating point operation.} +coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 242 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 243 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr -comment {We never flush. Flush is stuck to 0.} diff --git a/cv32e40p/tb/uvmt/imperas_dv.flist b/cv32e40p/tb/uvmt/imperas_dv.flist index ea7f2cd08c..1d4e6a685b 100644 --- a/cv32e40p/tb/uvmt/imperas_dv.flist +++ b/cv32e40p/tb/uvmt/imperas_dv.flist @@ -24,6 +24,7 @@ +incdir+${IMPERAS_HOME} +incdir+${IMPERAS_HOME}/ImpProprietary/include/host +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/CV32E40Pv2_riscvISACOV/source +// +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source ${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv index 8db6c816f2..ef7069366c 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv @@ -320,10 +320,71 @@ module uvmt_cv32e40p_imperas_dv_wrap `RVVI_SET_CSR( `CSR_MCAUSE_ADDR, mcause ) // `RVVI_SET_CSR( `CSR_MTVAL_ADDR, mtval ) `RVVI_SET_CSR( `CSR_MIP_ADDR, mip ) - // `RVVI_SET_CSR( `CSR_MCYCLE_ADDR, mcycle ) + // `RVVI_SET_CSR( `CSR_MCYCLE_ADDR, mcycle ) `RVVI_SET_CSR( `CSR_MINSTRET_ADDR, minstret ) // `RVVI_SET_CSR( `CSR_MCYCLEH_ADDR, mcycleh ) - // `RVVI_SET_CSR( `CSR_MINSTRETH_ADDR, minstreth ) + `RVVI_SET_CSR( `CSR_MINSTRETH_ADDR, minstreth ) + `RVVI_SET_CSR( `CSR_INSTRET_ADDR, instret ) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER3_ADDR, mhpmcounter, 3) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER3H_ADDR, mhpmcounterh, 3) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER4_ADDR, mhpmcounter, 4) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER4H_ADDR, mhpmcounterh, 4) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER5_ADDR, mhpmcounter, 5) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER5H_ADDR, mhpmcounterh, 5) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER6_ADDR, mhpmcounter, 6) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER6H_ADDR, mhpmcounterh, 6) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER7_ADDR, mhpmcounter, 7) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER7H_ADDR, mhpmcounterh, 7) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER8_ADDR, mhpmcounter, 8) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER8H_ADDR, mhpmcounterh, 8) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER9_ADDR, mhpmcounter, 9) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER9H_ADDR, mhpmcounterh, 9) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER10_ADDR, mhpmcounter, 10) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER10H_ADDR, mhpmcounterh, 10) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER11_ADDR, mhpmcounter, 11) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER11H_ADDR, mhpmcounterh, 11) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER12_ADDR, mhpmcounter, 12) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER12H_ADDR, mhpmcounterh, 12) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER13_ADDR, mhpmcounter, 13) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER13H_ADDR, mhpmcounterh, 13) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER14_ADDR, mhpmcounter, 14) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER14H_ADDR, mhpmcounterh, 14) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER15_ADDR, mhpmcounter, 15) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER15H_ADDR, mhpmcounterh, 15) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER16_ADDR, mhpmcounter, 16) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER16H_ADDR, mhpmcounterh, 16) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER17_ADDR, mhpmcounter, 17) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER17H_ADDR, mhpmcounterh, 17) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER18_ADDR, mhpmcounter, 18) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER18H_ADDR, mhpmcounterh, 18) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER19_ADDR, mhpmcounter, 19) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER19H_ADDR, mhpmcounterh, 19) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER20_ADDR, mhpmcounter, 20) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER20H_ADDR, mhpmcounterh, 20) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER21_ADDR, mhpmcounter, 21) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER21H_ADDR, mhpmcounterh, 21) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER22_ADDR, mhpmcounter, 22) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER22H_ADDR, mhpmcounterh, 22) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER23_ADDR, mhpmcounter, 23) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER23H_ADDR, mhpmcounterh, 23) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER24_ADDR, mhpmcounter, 24) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER24H_ADDR, mhpmcounterh, 24) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER25_ADDR, mhpmcounter, 25) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER25H_ADDR, mhpmcounterh, 25) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER26_ADDR, mhpmcounter, 26) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER26H_ADDR, mhpmcounterh, 26) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER27_ADDR, mhpmcounter, 27) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER27H_ADDR, mhpmcounterh, 27) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER28_ADDR, mhpmcounter, 28) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER28H_ADDR, mhpmcounterh, 28) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER29_ADDR, mhpmcounter, 29) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER29H_ADDR, mhpmcounterh, 29) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER30_ADDR, mhpmcounter, 30) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER30H_ADDR, mhpmcounterh, 30) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER31_ADDR, mhpmcounter, 31) + `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER31H_ADDR, mhpmcounterh, 31) + + `RVVI_SET_CSR( `CSR_INSTRETH_ADDR, instreth ) `RVVI_SET_CSR( `CSR_MVENDORID_ADDR, mvendorid ) `RVVI_SET_CSR( `CSR_MARCHID_ADDR, marchid ) // `RVVI_SET_CSR( `CSR_MIMPID_ADDR, mimpid ) @@ -486,10 +547,14 @@ module uvmt_cv32e40p_imperas_dv_wrap hart_id = 32'h0000_0000; void'(rvviRefCsrSetVolatile(hart_id, `CSR_CYCLE_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_CYCLEH_ADDR )); void'(rvviRefCsrSetVolatile(hart_id, `CSR_INSTRET_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3H_ADDR )); void'(rvviRefCsrSetVolatile(hart_id, `CSR_MCYCLE_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MCYCLEH_ADDR )); // cannot predict this register due to latency between // pending and taken diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index f72ad3888f..d933a09ae9 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -511,22 +511,28 @@ module uvmt_cv32e40p_tb; uvmt_cv32e40p_cov_if cov_if( .clk_i(clknrst_if.clk), .rst_ni(clknrst_if.reset_n), + .if_stage_instr_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rvalid_i), .if_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rdata_i), + .id_stage_instr_valid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_valid_i), .id_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_rdata_i), + .id_stage_id_valid_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.id_valid_o), + .id_stage_apu_op_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_op_ex_o), + .id_stage_apu_en_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_en_ex_o), + .apu_req(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_req_o), .apu_gnt(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_gnt_i), .apu_busy(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_busy_i), .apu_op(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_op_o), .apu_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_rvalid_i), .apu_perf_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_perf_wb_o), - .id_stage_apu_op_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_op_ex_o), - .id_stage_apu_en_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_en_ex_o), + .regfile_waddr_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_waddr_wb_o), .regfile_we_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_we_wb_o), .regfile_alu_waddr_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_waddr_fw_o), .regfile_alu_we_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_fw_o), + .ex_mulh_active(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.mulh_active), .ex_mult_op_ex(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.mult_operator_i), .ex_data_misaligned_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_misaligned_i), @@ -536,6 +542,7 @@ module uvmt_cv32e40p_tb; .ex_regfile_alu_we_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_i), .ex_apu_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_valid), .ex_apu_rvalid_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_rvalid_q), + .debug_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_req_pending), .debug_mode_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_mode_q), .dcsr_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.dcsr_q), diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index bc8b211890..38480a893a 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -492,6 +492,7 @@ interface uvmt_cv32e40p_cov_if input if_stage_instr_rvalid_i, input [31:0] if_stage_instr_rdata_i, input id_stage_instr_valid_i, + input id_stage_id_valid_o, input [31:0] id_stage_instr_rdata_i, input apu_req, input apu_gnt, @@ -553,6 +554,8 @@ interface uvmt_cv32e40p_cov_if logic [5:0] regfile_waddr_wb_contention; logic [1:0] contention_valid; logic b2b_contention_valid; + logic [31:0] current_instr_rdata; + logic [31:0] previous_instr_rdata; initial begin clk_cycle_window = 0; @@ -572,6 +575,7 @@ interface uvmt_cv32e40p_cov_if input if_stage_instr_rvalid_i; input if_stage_instr_rdata_i; input id_stage_instr_valid_i; + input id_stage_id_valid_o; input id_stage_instr_rdata_i; input apu_req; input apu_gnt; @@ -617,6 +621,24 @@ interface uvmt_cv32e40p_cov_if end end + // bhv_logic_1a + // sample decoded instr that execute in progress + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + previous_instr_rdata <= 0; + current_instr_rdata <= 0; + end + else begin + if (id_stage_instr_valid_i && id_stage_id_valid_o) begin + previous_instr_rdata <= current_instr_rdata; + current_instr_rdata <= id_stage_instr_rdata_i; + end + else begin + previous_instr_rdata <= current_instr_rdata; + end + end + end + // bhv_logic_2 (revised) // Model APU contention state in EX/WB for functional coverage // input(s): apu_perf_wb_o, regfile_waddr_wb_o, regfile_alu_waddr_ex_o @@ -631,11 +653,7 @@ interface uvmt_cv32e40p_cov_if if (((contention_valid == 0) || (contention_valid == 2)) && (apu_perf_wb_o)) begin contention_valid <= 1; //set contention_valid b2b_contention_valid <= 0; - if (FPU_LAT_1_CYC != 1) begin // IS_0_OR_2_CYCLAT - end - else begin // IS_1_CYCLAT - last_fpu_contention_op_if <= curr_fpu_apu_op_if; - end + last_fpu_contention_op_if <= curr_fpu_apu_op_if; end else if((contention_valid == 1) && (apu_perf_wb_o)) begin contention_valid <= 1; //reset contention_valid diff --git a/cv32e40p/tests/programs/custom/cv32e40p_csr_access_test/cv32e40p_csr_access_test.S b/cv32e40p/tests/programs/custom/cv32e40p_csr_access_test/cv32e40p_csr_access_test.S index 1e6ad8822c..ed4cfc292f 100644 --- a/cv32e40p/tests/programs/custom/cv32e40p_csr_access_test/cv32e40p_csr_access_test.S +++ b/cv32e40p/tests/programs/custom/cv32e40p_csr_access_test/cv32e40p_csr_access_test.S @@ -11,15 +11,29 @@ .section .text .global u_sw_irq_handler - #ifdef PULP - #if defined(FPU) && !defined(ZFINX) +#define MSTATUS_HARDWIRED 0x00001800 + +#if defined(PULP) + #if defined(FPU) && !defined(ZFINX) + #define HAS_FPU 1 #define EXP_MISA 0x40801124 - #else - #define EXP_MISA 0x40801104 - #endif + #define MSTATUS_MASK 0x00006088 #else - #define EXP_MISA 0x40001104 + #define HAS_FPU 0 + #define EXP_MISA 0x40801104 + #define MSTATUS_MASK 0x00000088 #endif +#else +#define HAS_FPU 0 +#define EXP_MISA 0x40001104 +#define MSTATUS_MASK 0x00000088 +#endif + +# for mstatus, value will be : +# csrr_w(i)_ : (MSTATUS_HARDWIRED | (write_value & MSTATUS_MASK)) +# csrr_s(i)_ : (MSTATUS_HARDWIRED | ((previous_value | write_value) & MSTATUS_MASK)) +# csrr_c(i)_ : (MSTATUS_HARDWIRED | ((previous_value & ~(write_value)) & MSTATUS_MASK)) +# Only the first group of mstatus accesses will be self-checked. For subsequent accesses to mstatus bne instructions will not be executed if F ext is present ############################################################################### # @@ -545,42 +559,42 @@ main: # mstatus li x7, 0xa5a5a5a5 csrrw x12, 768, x7 - li x7, 0x00001800 + li x7, (MSTATUS_HARDWIRED | (0x00001800 & MSTATUS_MASK)) bne x7, x12, csr_fail li x7, 0x5a5a5a5a csrrw x12, 768, x7 - li x7, 0x00001880 + li x7, (MSTATUS_HARDWIRED | (0xa5a5a5a5 & MSTATUS_MASK)) bne x7, x12, csr_fail li x7, 0x197aa0ad csrrw x12, 768, x7 - li x7, 0x00001808 + li x7, (MSTATUS_HARDWIRED | (0x5a5a5a5a & MSTATUS_MASK)) bne x7, x12, csr_fail li x7, 0xa5a5a5a5 csrrs x12, 768, x7 - li x7, 0x00001888 + li x7, (MSTATUS_HARDWIRED | (0x197aa0ad & MSTATUS_MASK)) # (= x1888 or x3888 if FPU) bne x7, x12, csr_fail li x7, 0x5a5a5a5a csrrs x12, 768, x7 - li x7, 0x00001888 + li x7, (MSTATUS_HARDWIRED | ((0x00003888 | 0xa5a5a5a5) & MSTATUS_MASK)) # (= x1888 or x3888 if FPU, 3888 & MSTATUS_MASK for no FPU = 0x1888) bne x7, x12, csr_fail li x7, 0xd3d179f8 csrrs x12, 768, x7 - li x7, 0x00001888 + li x7, (MSTATUS_HARDWIRED | ((0x80007888 | 0x5a5a5a5a) & (MSTATUS_MASK | (HAS_FPU<<31) )) ) # (= x1888 or x80007888 if FPU, 80007888 & MSTATUS_MASK for no FPU = 0x1888) bne x7, x12, csr_fail li x7, 0xa5a5a5a5 csrrc x12, 768, x7 - li x7, 0x00001888 + li x7, (MSTATUS_HARDWIRED | ((0x80007888 | 0xd3d179f8) & (MSTATUS_MASK | (HAS_FPU<<31) )) ) # (= x1888 or x80007888 if FPU, 80007888 & MSTATUS_MASK for no FPU = 0x1888) bne x7, x12, csr_fail li x7, 0x5a5a5a5a csrrc x12, 768, x7 - li x7, 0x00001808 + li x7, (MSTATUS_HARDWIRED | ((0x80007888 & ~(0xa5a5a5a5)) & MSTATUS_MASK)) bne x7, x12, csr_fail li x7, 0x111776a9 csrrc x12, 768, x7 - li x7, 0x00001800 + li x7, (MSTATUS_HARDWIRED | ((0x00005808 & ~(0x5a5a5a5a)) & MSTATUS_MASK)) bne x7, x12, csr_fail csrrwi x12, 768, 0b00101 - li x7, 0x00001800 + li x7, (MSTATUS_HARDWIRED | ((0x00001800 & ~(0x111776a9)) & MSTATUS_MASK)) bne x7, x12, csr_fail csrrwi x12, 768, 0b11010 li x7, 0x00001800 @@ -1843,66 +1857,102 @@ _start1: li x14, 0xa5a5a5a5 csrrw x1, 768, x14 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0x5a5a5a5a csrrw x1, 768, x14 li x14, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0x42b2dbf7 csrrw x1, 768, x14 li x14, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0xa5a5a5a5 csrrs x1, 768, x14 li x14, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0x5a5a5a5a csrrs x1, 768, x14 li x14, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0xdbaded82 csrrs x1, 768, x14 li x14, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0xa5a5a5a5 csrrc x1, 768, x14 li x14, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0x5a5a5a5a csrrc x1, 768, x14 li x14, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif li x14, 0x3b29374d csrrc x1, 768, x14 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrwi x1, 768, 0b00101 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrwi x1, 768, 0b11010 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrwi x1, 768, 0b10100 li x14, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrsi x1, 768, 0b00101 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrsi x1, 768, 0b11010 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrsi x1, 768, 0b10010 li x14, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrci x1, 768, 0b00101 li x14, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrci x1, 768, 0b11010 li x14, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif csrrci x1, 768, 0b10111 li x14, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x14, x1, csr_fail + #endif # misa li x15, 0xa5a5a5a5 csrrw x2, 769, x15 @@ -3140,66 +3190,102 @@ _start2: li x8, 0xa5a5a5a5 csrrw x1, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0x5a5a5a5a csrrw x1, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0xa0e19a2b csrrw x1, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0xa5a5a5a5 csrrs x1, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0x5a5a5a5a csrrs x1, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0x746ea947 csrrs x1, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0xa5a5a5a5 csrrc x1, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0x5a5a5a5a csrrc x1, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif li x8, 0x6d45688c csrrc x1, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrwi x1, 768, 0b00101 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrwi x1, 768, 0b11010 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrwi x1, 768, 0b01100 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrsi x1, 768, 0b00101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrsi x1, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrsi x1, 768, 0b01000 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrci x1, 768, 0b00101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrci x1, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif csrrci x1, 768, 0b01100 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x1, csr_fail + #endif # misa li x8, 0xa5a5a5a5 csrrw x1, 769, x8 @@ -4437,66 +4523,102 @@ _start3: li x8, 0xa5a5a5a5 csrrw x12, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0x5a5a5a5a csrrw x12, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0xb511a673 csrrw x12, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0xa5a5a5a5 csrrs x12, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0x5a5a5a5a csrrs x12, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0x3975286f csrrs x12, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0xa5a5a5a5 csrrc x12, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0x5a5a5a5a csrrc x12, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif li x8, 0x62ce8bf5 csrrc x12, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrwi x12, 768, 0b00101 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrwi x12, 768, 0b11010 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrwi x12, 768, 0b00011 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrsi x12, 768, 0b00101 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrsi x12, 768, 0b11010 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrsi x12, 768, 0b10110 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrci x12, 768, 0b00101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrci x12, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif csrrci x12, 768, 0b10000 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x12, csr_fail + #endif # misa li x8, 0xa5a5a5a5 csrrw x12, 769, x8 @@ -5734,66 +5856,102 @@ _start4: li x2, 0xa5a5a5a5 csrrw x4, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0x5a5a5a5a csrrw x4, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0x8a0e21a3 csrrw x4, 768, x2 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0xa5a5a5a5 csrrs x4, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0x5a5a5a5a csrrs x4, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0x2e7c6e7a csrrs x4, 768, x2 li x2, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0xa5a5a5a5 csrrc x4, 768, x2 li x2, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0x5a5a5a5a csrrc x4, 768, x2 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif li x2, 0x94dda6f3 csrrc x4, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrwi x4, 768, 0b00101 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrwi x4, 768, 0b11010 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrwi x4, 768, 0b11010 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrsi x4, 768, 0b00101 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrsi x4, 768, 0b11010 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrsi x4, 768, 0b00001 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrci x4, 768, 0b00101 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrci x4, 768, 0b11010 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif csrrci x4, 768, 0b00101 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x4, csr_fail + #endif # misa li x2, 0xa5a5a5a5 csrrw x4, 769, x2 @@ -7031,66 +7189,102 @@ _start5: li x13, 0xa5a5a5a5 csrrw x6, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0x5a5a5a5a csrrw x6, 768, x13 li x13, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0x68c7c730 csrrw x6, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0xa5a5a5a5 csrrs x6, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0x5a5a5a5a csrrs x6, 768, x13 li x13, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0xe711d08f csrrs x6, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0xa5a5a5a5 csrrc x6, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0x5a5a5a5a csrrc x6, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif li x13, 0xe6277d3f csrrc x6, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrwi x6, 768, 0b00101 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrwi x6, 768, 0b11010 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrwi x6, 768, 0b01111 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrsi x6, 768, 0b00101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrsi x6, 768, 0b11010 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrsi x6, 768, 0b01101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrci x6, 768, 0b00101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrci x6, 768, 0b11010 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif csrrci x6, 768, 0b11110 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x6, csr_fail + #endif # misa li x13, 0xa5a5a5a5 csrrw x6, 769, x13 @@ -8328,66 +8522,102 @@ _start6: li x13, 0xa5a5a5a5 csrrw x1, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0x5a5a5a5a csrrw x1, 768, x13 li x13, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0x522ce33d csrrw x1, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0xa5a5a5a5 csrrs x1, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0x5a5a5a5a csrrs x1, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0x3f5b7b72 csrrs x1, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0xa5a5a5a5 csrrc x1, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0x5a5a5a5a csrrc x1, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif li x13, 0x2961b1fd csrrc x1, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrwi x1, 768, 0b00101 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrwi x1, 768, 0b11010 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrwi x1, 768, 0b11001 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrsi x1, 768, 0b00101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrsi x1, 768, 0b11010 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrsi x1, 768, 0b11001 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrci x1, 768, 0b00101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrci x1, 768, 0b11010 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif csrrci x1, 768, 0b10101 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x1, csr_fail + #endif # misa li x13, 0xa5a5a5a5 csrrw x1, 769, x13 @@ -9625,66 +9855,102 @@ _start7: li x15, 0xa5a5a5a5 csrrw x11, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0x5a5a5a5a csrrw x11, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0x539d6068 csrrw x11, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0xa5a5a5a5 csrrs x11, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0x5a5a5a5a csrrs x11, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0xb61f748a csrrs x11, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0xa5a5a5a5 csrrc x11, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0x5a5a5a5a csrrc x11, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif li x15, 0x6beadff6 csrrc x11, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrwi x11, 768, 0b00101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrwi x11, 768, 0b11010 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrwi x11, 768, 0b01000 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrsi x11, 768, 0b00101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrsi x11, 768, 0b11010 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrsi x11, 768, 0b00111 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrci x11, 768, 0b00101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrci x11, 768, 0b11010 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif csrrci x11, 768, 0b11110 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x11, csr_fail + #endif # misa li x15, 0xa5a5a5a5 csrrw x11, 769, x15 @@ -10922,66 +11188,102 @@ _start8: li x3, 0xa5a5a5a5 csrrw x11, 768, x3 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0x5a5a5a5a csrrw x11, 768, x3 li x3, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0x670734ed csrrw x11, 768, x3 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0xa5a5a5a5 csrrs x11, 768, x3 li x3, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0x5a5a5a5a csrrs x11, 768, x3 li x3, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0xc7016933 csrrs x11, 768, x3 li x3, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0xa5a5a5a5 csrrc x11, 768, x3 li x3, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0x5a5a5a5a csrrc x11, 768, x3 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif li x3, 0xb65d115a csrrc x11, 768, x3 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrwi x11, 768, 0b00101 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrwi x11, 768, 0b11010 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrwi x11, 768, 0b11111 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrsi x11, 768, 0b00101 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrsi x11, 768, 0b11010 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrsi x11, 768, 0b10100 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrci x11, 768, 0b00101 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrci x11, 768, 0b11010 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif csrrci x11, 768, 0b11010 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x11, csr_fail + #endif # misa li x3, 0xa5a5a5a5 csrrw x11, 769, x3 @@ -12219,66 +12521,102 @@ _start9: li x13, 0xa5a5a5a5 csrrw x10, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0x5a5a5a5a csrrw x10, 768, x13 li x13, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0x102c239f csrrw x10, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0xa5a5a5a5 csrrs x10, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0x5a5a5a5a csrrs x10, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0x90d9af7c csrrs x10, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0xa5a5a5a5 csrrc x10, 768, x13 li x13, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0x5a5a5a5a csrrc x10, 768, x13 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif li x13, 0x9e3c631e csrrc x10, 768, x13 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrwi x10, 768, 0b00101 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrwi x10, 768, 0b11010 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrwi x10, 768, 0b10100 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrsi x10, 768, 0b00101 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrsi x10, 768, 0b11010 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrsi x10, 768, 0b10101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrci x10, 768, 0b00101 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrci x10, 768, 0b11010 li x13, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif csrrci x10, 768, 0b10110 li x13, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x13, x10, csr_fail + #endif # misa li x13, 0xa5a5a5a5 csrrw x10, 769, x13 @@ -13516,66 +13854,102 @@ _start10: li x5, 0xa5a5a5a5 csrrw x6, 768, x5 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0x5a5a5a5a csrrw x6, 768, x5 li x5, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0xd6188de4 csrrw x6, 768, x5 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0xa5a5a5a5 csrrs x6, 768, x5 li x5, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0x5a5a5a5a csrrs x6, 768, x5 li x5, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0xb52760c4 csrrs x6, 768, x5 li x5, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0xa5a5a5a5 csrrc x6, 768, x5 li x5, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0x5a5a5a5a csrrc x6, 768, x5 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif li x5, 0x6f721966 csrrc x6, 768, x5 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrwi x6, 768, 0b00101 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrwi x6, 768, 0b11010 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrwi x6, 768, 0b00000 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrsi x6, 768, 0b00101 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrsi x6, 768, 0b11010 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrsi x6, 768, 0b00001 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrci x6, 768, 0b00101 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrci x6, 768, 0b11010 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif csrrci x6, 768, 0b10101 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x6, csr_fail + #endif # misa li x5, 0xa5a5a5a5 csrrw x6, 769, x5 @@ -14813,66 +15187,102 @@ _start11: li x11, 0xa5a5a5a5 csrrw x3, 768, x11 li x11, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0x5a5a5a5a csrrw x3, 768, x11 li x11, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0xa703f9b2 csrrw x3, 768, x11 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0xa5a5a5a5 csrrs x3, 768, x11 li x11, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0x5a5a5a5a csrrs x3, 768, x11 li x11, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0x1ebf86c5 csrrs x3, 768, x11 li x11, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0xa5a5a5a5 csrrc x3, 768, x11 li x11, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0x5a5a5a5a csrrc x3, 768, x11 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif li x11, 0xd5c5f1ac csrrc x3, 768, x11 li x11, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrwi x3, 768, 0b00101 li x11, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrwi x3, 768, 0b11010 li x11, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrwi x3, 768, 0b11010 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrsi x3, 768, 0b00101 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrsi x3, 768, 0b11010 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrsi x3, 768, 0b11111 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrci x3, 768, 0b00101 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrci x3, 768, 0b11010 li x11, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif csrrci x3, 768, 0b01000 li x11, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x11, x3, csr_fail + #endif # misa li x11, 0xa5a5a5a5 csrrw x3, 769, x11 @@ -16110,66 +16520,102 @@ _start12: li x15, 0xa5a5a5a5 csrrw x12, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x5a5a5a5a csrrw x12, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x1c1fa688 csrrw x12, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0xa5a5a5a5 csrrs x12, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x5a5a5a5a csrrs x12, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x929e21d8 csrrs x12, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0xa5a5a5a5 csrrc x12, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x5a5a5a5a csrrc x12, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x22e459c1 csrrc x12, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrwi x12, 768, 0b00101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrwi x12, 768, 0b11010 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrwi x12, 768, 0b00110 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrsi x12, 768, 0b00101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrsi x12, 768, 0b11010 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrsi x12, 768, 0b11100 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrci x12, 768, 0b00101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrci x12, 768, 0b11010 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrci x12, 768, 0b00111 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif # misa li x15, 0xa5a5a5a5 csrrw x12, 769, x15 @@ -17407,66 +17853,102 @@ _start13: li x15, 0xa5a5a5a5 csrrw x9, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0x5a5a5a5a csrrw x9, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0xe3bb0b51 csrrw x9, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0xa5a5a5a5 csrrs x9, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0x5a5a5a5a csrrs x9, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0xe2bd3b59 csrrs x9, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0xa5a5a5a5 csrrc x9, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0x5a5a5a5a csrrc x9, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif li x15, 0x741c3cdb csrrc x9, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrwi x9, 768, 0b00101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrwi x9, 768, 0b11010 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrwi x9, 768, 0b10100 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrsi x9, 768, 0b00101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrsi x9, 768, 0b11010 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrsi x9, 768, 0b01101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrci x9, 768, 0b00101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrci x9, 768, 0b11010 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif csrrci x9, 768, 0b01110 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x9, csr_fail + #endif # misa li x15, 0xa5a5a5a5 csrrw x9, 769, x15 @@ -18704,66 +19186,102 @@ _start14: li x10, 0xa5a5a5a5 csrrw x12, 768, x10 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x5a5a5a5a csrrw x12, 768, x10 li x10, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xcb257085 csrrw x12, 768, x10 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xa5a5a5a5 csrrs x12, 768, x10 li x10, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x5a5a5a5a csrrs x12, 768, x10 li x10, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xeff062da csrrs x12, 768, x10 li x10, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xa5a5a5a5 csrrc x12, 768, x10 li x10, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x5a5a5a5a csrrc x12, 768, x10 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xbe546676 csrrc x12, 768, x10 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrwi x12, 768, 0b00101 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrwi x12, 768, 0b11010 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrwi x12, 768, 0b11101 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrsi x12, 768, 0b00101 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrsi x12, 768, 0b11010 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrsi x12, 768, 0b10011 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrci x12, 768, 0b00101 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrci x12, 768, 0b11010 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrci x12, 768, 0b10001 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif # misa li x10, 0xa5a5a5a5 csrrw x12, 769, x10 @@ -20001,66 +20519,102 @@ _start15: li x12, 0xa5a5a5a5 csrrw x14, 768, x12 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0x5a5a5a5a csrrw x14, 768, x12 li x12, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0x4c01bfc7 csrrw x14, 768, x12 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0xa5a5a5a5 csrrs x14, 768, x12 li x12, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0x5a5a5a5a csrrs x14, 768, x12 li x12, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0x20b8ac50 csrrs x14, 768, x12 li x12, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0xa5a5a5a5 csrrc x14, 768, x12 li x12, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0x5a5a5a5a csrrc x14, 768, x12 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif li x12, 0x97f831b8 csrrc x14, 768, x12 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrwi x14, 768, 0b00101 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrwi x14, 768, 0b11010 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrwi x14, 768, 0b11011 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrsi x14, 768, 0b00101 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrsi x14, 768, 0b11010 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrsi x14, 768, 0b00110 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrci x14, 768, 0b00101 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrci x14, 768, 0b11010 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif csrrci x14, 768, 0b01101 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x14, csr_fail + #endif # misa li x12, 0xa5a5a5a5 csrrw x14, 769, x12 @@ -21298,66 +21852,102 @@ _start16: li x3, 0xa5a5a5a5 csrrw x14, 768, x3 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0x5a5a5a5a csrrw x14, 768, x3 li x3, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0x50aed442 csrrw x14, 768, x3 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0xa5a5a5a5 csrrs x14, 768, x3 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0x5a5a5a5a csrrs x14, 768, x3 li x3, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0xdc758590 csrrs x14, 768, x3 li x3, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0xa5a5a5a5 csrrc x14, 768, x3 li x3, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0x5a5a5a5a csrrc x14, 768, x3 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif li x3, 0x309c3de2 csrrc x14, 768, x3 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrwi x14, 768, 0b00101 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrwi x14, 768, 0b11010 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrwi x14, 768, 0b01011 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrsi x14, 768, 0b00101 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrsi x14, 768, 0b11010 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrsi x14, 768, 0b11110 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrci x14, 768, 0b00101 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrci x14, 768, 0b11010 li x3, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif csrrci x14, 768, 0b11011 li x3, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x3, x14, csr_fail + #endif # misa li x3, 0xa5a5a5a5 csrrw x14, 769, x3 @@ -22595,66 +23185,102 @@ _start17: li x1, 0xa5a5a5a5 csrrw x15, 768, x1 li x1, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0x5a5a5a5a csrrw x15, 768, x1 li x1, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0xe3382eb6 csrrw x15, 768, x1 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0xa5a5a5a5 csrrs x15, 768, x1 li x1, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0x5a5a5a5a csrrs x15, 768, x1 li x1, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0x6481fcaf csrrs x15, 768, x1 li x1, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0xa5a5a5a5 csrrc x15, 768, x1 li x1, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0x5a5a5a5a csrrc x15, 768, x1 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif li x1, 0x19d0d6a7 csrrc x15, 768, x1 li x1, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrwi x15, 768, 0b00101 li x1, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrwi x15, 768, 0b11010 li x1, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrwi x15, 768, 0b01110 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrsi x15, 768, 0b00101 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrsi x15, 768, 0b11010 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrsi x15, 768, 0b00011 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrci x15, 768, 0b00101 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrci x15, 768, 0b11010 li x1, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif csrrci x15, 768, 0b11111 li x1, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x1, x15, csr_fail + #endif # misa li x1, 0xa5a5a5a5 csrrw x15, 769, x1 @@ -23892,66 +24518,102 @@ _start18: li x15, 0xa5a5a5a5 csrrw x12, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x5a5a5a5a csrrw x12, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0xd3985593 csrrw x12, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0xa5a5a5a5 csrrs x12, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x5a5a5a5a csrrs x12, 768, x15 li x15, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x06338dee csrrs x12, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0xa5a5a5a5 csrrc x12, 768, x15 li x15, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x5a5a5a5a csrrc x12, 768, x15 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif li x15, 0x3f31406b csrrc x12, 768, x15 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrwi x12, 768, 0b00101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrwi x12, 768, 0b11010 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrwi x12, 768, 0b11100 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrsi x12, 768, 0b00101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrsi x12, 768, 0b11010 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrsi x12, 768, 0b10000 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrci x12, 768, 0b00101 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrci x12, 768, 0b11010 li x15, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif csrrci x12, 768, 0b10101 li x15, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x15, x12, csr_fail + #endif # misa li x15, 0xa5a5a5a5 csrrw x12, 769, x15 @@ -25189,66 +25851,102 @@ _start19: li x2, 0xa5a5a5a5 csrrw x6, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0x5a5a5a5a csrrw x6, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0x750b4706 csrrw x6, 768, x2 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0xa5a5a5a5 csrrs x6, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0x5a5a5a5a csrrs x6, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0x76e5e534 csrrs x6, 768, x2 li x2, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0xa5a5a5a5 csrrc x6, 768, x2 li x2, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0x5a5a5a5a csrrc x6, 768, x2 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif li x2, 0xc5522492 csrrc x6, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrwi x6, 768, 0b00101 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrwi x6, 768, 0b11010 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrwi x6, 768, 0b00011 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrsi x6, 768, 0b00101 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrsi x6, 768, 0b11010 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrsi x6, 768, 0b11001 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrci x6, 768, 0b00101 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrci x6, 768, 0b11010 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif csrrci x6, 768, 0b00100 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x6, csr_fail + #endif # misa li x2, 0xa5a5a5a5 csrrw x6, 769, x2 @@ -26486,66 +27184,102 @@ _start20: li x10, 0xa5a5a5a5 csrrw x12, 768, x10 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x5a5a5a5a csrrw x12, 768, x10 li x10, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xf9ae7874 csrrw x12, 768, x10 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xa5a5a5a5 csrrs x12, 768, x10 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x5a5a5a5a csrrs x12, 768, x10 li x10, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x25e2d17c csrrs x12, 768, x10 li x10, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xa5a5a5a5 csrrc x12, 768, x10 li x10, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0x5a5a5a5a csrrc x12, 768, x10 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif li x10, 0xacedb31b csrrc x12, 768, x10 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrwi x12, 768, 0b00101 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrwi x12, 768, 0b11010 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrwi x12, 768, 0b01000 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrsi x12, 768, 0b00101 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrsi x12, 768, 0b11010 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrsi x12, 768, 0b11111 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrci x12, 768, 0b00101 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrci x12, 768, 0b11010 li x10, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif csrrci x12, 768, 0b11010 li x10, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x10, x12, csr_fail + #endif # misa li x10, 0xa5a5a5a5 csrrw x12, 769, x10 @@ -27783,66 +28517,102 @@ _start21: li x2, 0xa5a5a5a5 csrrw x5, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0x5a5a5a5a csrrw x5, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0xfc0955c6 csrrw x5, 768, x2 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0xa5a5a5a5 csrrs x5, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0x5a5a5a5a csrrs x5, 768, x2 li x2, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0x039b5889 csrrs x5, 768, x2 li x2, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0xa5a5a5a5 csrrc x5, 768, x2 li x2, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0x5a5a5a5a csrrc x5, 768, x2 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif li x2, 0xe70a7e6d csrrc x5, 768, x2 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrwi x5, 768, 0b00101 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrwi x5, 768, 0b11010 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrwi x5, 768, 0b11111 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrsi x5, 768, 0b00101 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrsi x5, 768, 0b11010 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrsi x5, 768, 0b00100 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrci x5, 768, 0b00101 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrci x5, 768, 0b11010 li x2, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif csrrci x5, 768, 0b10100 li x2, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x2, x5, csr_fail + #endif # misa li x2, 0xa5a5a5a5 csrrw x5, 769, x2 @@ -29080,66 +29850,102 @@ _start22: li x9, 0xa5a5a5a5 csrrw x3, 768, x9 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0x5a5a5a5a csrrw x3, 768, x9 li x9, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0xe9d662de csrrw x3, 768, x9 li x9, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0xa5a5a5a5 csrrs x3, 768, x9 li x9, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0x5a5a5a5a csrrs x3, 768, x9 li x9, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0xd225a1b6 csrrs x3, 768, x9 li x9, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0xa5a5a5a5 csrrc x3, 768, x9 li x9, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0x5a5a5a5a csrrc x3, 768, x9 li x9, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif li x9, 0x01fe75a5 csrrc x3, 768, x9 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrwi x3, 768, 0b00101 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrwi x3, 768, 0b11010 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrwi x3, 768, 0b10100 li x9, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrsi x3, 768, 0b00101 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrsi x3, 768, 0b11010 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrsi x3, 768, 0b10111 li x9, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrci x3, 768, 0b00101 li x9, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrci x3, 768, 0b11010 li x9, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif csrrci x3, 768, 0b11110 li x9, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x9, x3, csr_fail + #endif # misa li x9, 0xa5a5a5a5 csrrw x3, 769, x9 @@ -30377,66 +31183,102 @@ _start23: li x5, 0xa5a5a5a5 csrrw x4, 768, x5 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0x5a5a5a5a csrrw x4, 768, x5 li x5, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0x573b1953 csrrw x4, 768, x5 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0xa5a5a5a5 csrrs x4, 768, x5 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0x5a5a5a5a csrrs x4, 768, x5 li x5, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0x88b0531b csrrs x4, 768, x5 li x5, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0xa5a5a5a5 csrrc x4, 768, x5 li x5, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0x5a5a5a5a csrrc x4, 768, x5 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif li x5, 0x886425d0 csrrc x4, 768, x5 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrwi x4, 768, 0b00101 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrwi x4, 768, 0b11010 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrwi x4, 768, 0b11000 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrsi x4, 768, 0b00101 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrsi x4, 768, 0b11010 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrsi x4, 768, 0b10000 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrci x4, 768, 0b00101 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrci x4, 768, 0b11010 li x5, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif csrrci x4, 768, 0b01101 li x5, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x5, x4, csr_fail + #endif # misa li x5, 0xa5a5a5a5 csrrw x4, 769, x5 @@ -31674,66 +32516,102 @@ _start24: li x7, 0xa5a5a5a5 csrrw x15, 768, x7 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0x5a5a5a5a csrrw x15, 768, x7 li x7, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0x7d1c3f82 csrrw x15, 768, x7 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0xa5a5a5a5 csrrs x15, 768, x7 li x7, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0x5a5a5a5a csrrs x15, 768, x7 li x7, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0xd6aa8f2d csrrs x15, 768, x7 li x7, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0xa5a5a5a5 csrrc x15, 768, x7 li x7, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0x5a5a5a5a csrrc x15, 768, x7 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif li x7, 0x0cb8549b csrrc x15, 768, x7 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrwi x15, 768, 0b00101 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrwi x15, 768, 0b11010 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrwi x15, 768, 0b01010 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrsi x15, 768, 0b00101 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrsi x15, 768, 0b11010 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrsi x15, 768, 0b10011 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrci x15, 768, 0b00101 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrci x15, 768, 0b11010 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif csrrci x15, 768, 0b11011 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x15, csr_fail + #endif # misa li x7, 0xa5a5a5a5 csrrw x15, 769, x7 @@ -32971,66 +33849,102 @@ _start25: li x7, 0xa5a5a5a5 csrrw x2, 768, x7 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0x5a5a5a5a csrrw x2, 768, x7 li x7, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0x627c6f93 csrrw x2, 768, x7 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0xa5a5a5a5 csrrs x2, 768, x7 li x7, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0x5a5a5a5a csrrs x2, 768, x7 li x7, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0x55ef2b06 csrrs x2, 768, x7 li x7, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0xa5a5a5a5 csrrc x2, 768, x7 li x7, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0x5a5a5a5a csrrc x2, 768, x7 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif li x7, 0xf8cad51f csrrc x2, 768, x7 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrwi x2, 768, 0b00101 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrwi x2, 768, 0b11010 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrwi x2, 768, 0b01111 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrsi x2, 768, 0b00101 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrsi x2, 768, 0b11010 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrsi x2, 768, 0b11001 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrci x2, 768, 0b00101 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrci x2, 768, 0b11010 li x7, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif csrrci x2, 768, 0b00111 li x7, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x7, x2, csr_fail + #endif # misa li x7, 0xa5a5a5a5 csrrw x2, 769, x7 @@ -34268,66 +35182,102 @@ _start26: li x12, 0xa5a5a5a5 csrrw x15, 768, x12 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0x5a5a5a5a csrrw x15, 768, x12 li x12, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0x8a0e612a csrrw x15, 768, x12 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0xa5a5a5a5 csrrs x15, 768, x12 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0x5a5a5a5a csrrs x15, 768, x12 li x12, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0xc82366ed csrrs x15, 768, x12 li x12, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0xa5a5a5a5 csrrc x15, 768, x12 li x12, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0x5a5a5a5a csrrc x15, 768, x12 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif li x12, 0xdf9f73bc csrrc x15, 768, x12 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrwi x15, 768, 0b00101 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrwi x15, 768, 0b11010 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrwi x15, 768, 0b00001 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrsi x15, 768, 0b00101 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrsi x15, 768, 0b11010 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrsi x15, 768, 0b11101 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrci x15, 768, 0b00101 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrci x15, 768, 0b11010 li x12, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif csrrci x15, 768, 0b10011 li x12, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x12, x15, csr_fail + #endif # misa li x12, 0xa5a5a5a5 csrrw x15, 769, x12 @@ -35565,66 +36515,102 @@ _start27: li x4, 0xa5a5a5a5 csrrw x1, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0x5a5a5a5a csrrw x1, 768, x4 li x4, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0x1e189333 csrrw x1, 768, x4 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0xa5a5a5a5 csrrs x1, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0x5a5a5a5a csrrs x1, 768, x4 li x4, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0x2b045e01 csrrs x1, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0xa5a5a5a5 csrrc x1, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0x5a5a5a5a csrrc x1, 768, x4 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif li x4, 0x42ff4fc9 csrrc x1, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrwi x1, 768, 0b00101 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrwi x1, 768, 0b11010 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrwi x1, 768, 0b11101 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrsi x1, 768, 0b00101 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrsi x1, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrsi x1, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrci x1, 768, 0b00101 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrci x1, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif csrrci x1, 768, 0b11111 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x1, csr_fail + #endif # misa li x4, 0xa5a5a5a5 csrrw x1, 769, x4 @@ -36862,66 +37848,102 @@ _start28: li x8, 0xa5a5a5a5 csrrw x9, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0x5a5a5a5a csrrw x9, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0xe09dcf14 csrrw x9, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0xa5a5a5a5 csrrs x9, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0x5a5a5a5a csrrs x9, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0x77d56a3f csrrs x9, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0xa5a5a5a5 csrrc x9, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0x5a5a5a5a csrrc x9, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif li x8, 0xb88d8aa4 csrrc x9, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrwi x9, 768, 0b00101 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrwi x9, 768, 0b11010 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrwi x9, 768, 0b01100 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrsi x9, 768, 0b00101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrsi x9, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrsi x9, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrci x9, 768, 0b00101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrci x9, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif csrrci x9, 768, 0b11100 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x9, csr_fail + #endif # misa li x8, 0xa5a5a5a5 csrrw x9, 769, x8 @@ -38159,66 +39181,102 @@ _start29: li x4, 0xa5a5a5a5 csrrw x6, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0x5a5a5a5a csrrw x6, 768, x4 li x4, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0x34168d30 csrrw x6, 768, x4 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0xa5a5a5a5 csrrs x6, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0x5a5a5a5a csrrs x6, 768, x4 li x4, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0x9b0e3263 csrrs x6, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0xa5a5a5a5 csrrc x6, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0x5a5a5a5a csrrc x6, 768, x4 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif li x4, 0xa7ae12e7 csrrc x6, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrwi x6, 768, 0b00101 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrwi x6, 768, 0b11010 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrwi x6, 768, 0b10010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrsi x6, 768, 0b00101 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrsi x6, 768, 0b11010 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrsi x6, 768, 0b11110 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrci x6, 768, 0b00101 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrci x6, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif csrrci x6, 768, 0b01001 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x6, csr_fail + #endif # misa li x4, 0xa5a5a5a5 csrrw x6, 769, x4 @@ -39456,66 +40514,102 @@ _start30: li x4, 0xa5a5a5a5 csrrw x10, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0x5a5a5a5a csrrw x10, 768, x4 li x4, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0xa6705d8b csrrw x10, 768, x4 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0xa5a5a5a5 csrrs x10, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0x5a5a5a5a csrrs x10, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0x3fbb2441 csrrs x10, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0xa5a5a5a5 csrrc x10, 768, x4 li x4, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0x5a5a5a5a csrrc x10, 768, x4 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif li x4, 0xd9ee192e csrrc x10, 768, x4 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrwi x10, 768, 0b00101 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrwi x10, 768, 0b11010 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrwi x10, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrsi x10, 768, 0b00101 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrsi x10, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrsi x10, 768, 0b00111 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrci x10, 768, 0b00101 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrci x10, 768, 0b11010 li x4, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif csrrci x10, 768, 0b00010 li x4, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x4, x10, csr_fail + #endif # misa li x4, 0xa5a5a5a5 csrrw x10, 769, x4 @@ -40753,66 +41847,102 @@ _start31: li x8, 0xa5a5a5a5 csrrw x14, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0x5a5a5a5a csrrw x14, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0x32245727 csrrw x14, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0xa5a5a5a5 csrrs x14, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0x5a5a5a5a csrrs x14, 768, x8 li x8, 0x00001880 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0x7ddc0d5e csrrs x14, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0xa5a5a5a5 csrrc x14, 768, x8 li x8, 0x00001888 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0x5a5a5a5a csrrc x14, 768, x8 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif li x8, 0x3ec76a76 csrrc x14, 768, x8 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrwi x14, 768, 0b00101 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrwi x14, 768, 0b11010 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrwi x14, 768, 0b00001 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrsi x14, 768, 0b00101 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrsi x14, 768, 0b11010 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrsi x14, 768, 0b11101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrci x14, 768, 0b00101 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrci x14, 768, 0b11010 li x8, 0x00001808 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif csrrci x14, 768, 0b01111 li x8, 0x00001800 + #if !defined(FPU) || defined(ZFINX) bne x8, x14, csr_fail + #endif # misa li x8, 0xa5a5a5a5 csrrw x14, 769, x8 diff --git a/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S b/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S index 0ed1a40caa..c8c31141a5 100644 --- a/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S +++ b/cv32e40p/tests/programs/custom/cv32e40p_readonly_csr_access_test/cv32e40p_readonly_csr_access_test.S @@ -31,8 +31,12 @@ #define TEST_PASS 123456789 #define TEST_FAIL 1 -#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 +#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 +#if defined(PULP) +#define EXPECTED_ILLEGAL_INSTRUCTIONS 78 +#else #define EXPECTED_ILLEGAL_INSTRUCTIONS 80 +#endif main: li t0, (0x1 << 3) @@ -133,7 +137,11 @@ main: csrrwi x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR csrrc x5, 3859, x0 # not illegal +#if defined(FPU) || defined(PULP) || defined(CLUSTER) + li x30, 0x00000001 +#else li x30, 0x00000000 +#endif bne x5, x30, fail # mhartid @@ -291,7 +299,7 @@ u_sw_irq_handler: csrrw x0, mepc, x27 c.addi x31, 1 mret - + _exit: j _exit diff --git a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c index 94a994e431..9b9d156902 100644 --- a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c +++ b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c @@ -51,9 +51,9 @@ int main() { unsigned int i = 0, j = 0, error = 0; - float *P_INPUT = INPUT; - float *P_EXP_RES = EXP_RES; - float *P_RES = RES; + float *P_INPUT = (float *)INPUT; + float *P_EXP_RES = (float *)EXP_RES; + float *P_RES = (float *)RES; // Floating Point enable fp_enable(); diff --git a/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S b/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S index 9043fcb589..99d601fe61 100644 --- a/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S +++ b/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S @@ -1,18 +1,18 @@ # # Copyright (C) 2020 by EM Microelectronic US Inc. -# +# # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # https://solderpad.org/licenses/ -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. -# +# # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 # ############################################################################### @@ -24,10 +24,10 @@ # # The pass/fail criteria is determined by checking x26 against MAGIC_NUMBER, # the value of which is determined by summing the following: -# - Exception code 2 (Illegal Instruction Exceptions (IIE)): 0x1 -# - Exception code 3 (Breakpoint): 0x10 -# - Exception code 11 (Environment call): 0x100 -# If the test has one of each exception code, MAGIC_NUMBER is 0x111 +# - Exception code 2 (Illegal Instruction Exceptions (IIE)): 0x1 +# - Exception code 3 (Breakpoint): 0x100 +# - Exception code 11 (Environment call): 0x1000 +# If the test has one of each exception code, MAGIC_NUMBER is 0x11001. It allows up to 255 IIE # ############################################################################### @@ -39,7 +39,12 @@ .global test_results .global u_sw_irq_handler - #define MAGIC_NUMBER 0x2f3 +# there are 2 env calls in the code +# there are 5 breakpoints in the code +# there are 129 unknown encodings (minus 2 because of 2 last instructions unused fields in fence), 2 unimp corresponding to .word 00000000, 1 (uret), 29 illegal CSR access = 9d +# For FPU-enabled configuration, letting mstatus_FS at default value lead to the same number of illegal instrucions + +#define MAGIC_NUMBER 0x259d test_results: .word 123456789 @@ -208,15 +213,15 @@ main: csrrc x14, mstatus, x0 nop nop - + added_by_mike: ############################################################################### -# Randomly generated illegal instructions. Each one adds 0x1 to MAGIC_NUMBER +# Randomly generated illegal instructions. Each one adds 0x1 to MAGIC_NUMBER (except for v2 and the one mentionned below that are legal encodings) .word(0x3bc6f92f) .word(0x5dd26da7) .word(0xe5607a57) .word(0x958e4a67) - .word(0x6159607b) + .word(0x6159607b) # for v2 it corresponds to cv.xor.sci.h zero,s2,-22 (not illegal anymore) .word(0x6c6b7433) .word(0x1a6a2b33) .word(0xd9067c3b) @@ -231,7 +236,7 @@ added_by_mike: .word(0x5dd26da7) .word(0xe5607a57) .word(0x958e4a67) - .word(0x6159607b) + .word(0x6159607b) # for v2 it corresponds to cv.xor.sci.h zero,s2,-22 (not illegal anymore) .word(0x6c6b7433) .word(0x1a6a2b33) .word(0xd9067c3b) @@ -240,7 +245,7 @@ added_by_mike: .word(0x6fcbc273) .word(0x395dd7e7) .word(0x079f0c07) -# + .word(0x57f0f043) .word(0xc06d0abb) .word(0x75d8b2fb) @@ -257,7 +262,7 @@ added_by_mike: .word(0x1d4d43ab) .word(0xb7aecccf) .word(0x1ac1e077) -# + .word(0x25ffc977) .word(0xceb61647) .word(0x4284de0f) @@ -274,21 +279,21 @@ added_by_mike: .word(0xc964b70f) .word(0x58ff393b) .word(0xaf9ac3a7) -# + .word(0x70f6bf03) .word(0x9da18a53) .word(0x6738ef8f) - .word(0xf4f4ba5b) + .word(0xf4f4ba5b) # for v2 it corresponds to cv.suburn s4,s1,a5,26 (not illegal anymore) .word(0xb4208057) .word(0x72857967) .word(0x64599d9b) .word(0x7328b2bb) .word(0x9fddb933) - .word(0x60628efb) + .word(0x60628efb) # for v2 it corresponds to cv.xor.h t4,t0,t1 (not illegal anymore) .word(0xaec951bb) .word(0xc56f4a27) .word(0x2e266467) - .word(0xa847620b) + .word(0xa847620b) # for v2 it corresponds to cv.beqimm a4,4,fffff5b0 (not illegal anymore) .word(0x5dd26c27) .word(0xb8ba7523) # @@ -307,7 +312,7 @@ added_by_mike: .word(0x427706f7) .word(0xbcd64e2f) .word(0x17f9256b) - .word(0x4c9cb05b) + .word(0x4c9cb05b) # for v2 it corresponds to cv.subun zero,s9,s1,6 (not illegal anymore) # .word(0x2ec14d9b) .word(0x974ffc9b) @@ -369,24 +374,24 @@ added_by_mike: csrrw x0, 0x040, x0 #USCRATCH csrrw x0, 0x043, x0 #UTVAL csrrw x0, 0x044, x0 #UIP -# p.elw - .word(0x00006003) # add 0x1 to MAGIC_NUMBER - .word(0x00106003) # add 0x1 to MAGIC_NUMBER - .word(0x00206003) # add 0x1 to MAGIC_NUMBER - .word(0x00406003) # add 0x1 to MAGIC_NUMBER - .word(0x00806003) # add 0x1 to MAGIC_NUMBER - .word(0x01006003) # add 0x1 to MAGIC_NUMBER +# cv.elw + .word(0x0000300B) # add 0x1 to MAGIC_NUMBER + .word(0x0000308B) # add 0x1 to MAGIC_NUMBER + .word(0x0000310B) # add 0x1 to MAGIC_NUMBER + .word(0x0000320B) # add 0x1 to MAGIC_NUMBER + .word(0x0000340B) # add 0x1 to MAGIC_NUMBER + .word(0x0000380B) # add 0x1 to MAGIC_NUMBER # uret uret # add 0x1 to MAGIC_NUMBER -# p.elw - .word(0x02006003) # add 0x1 to MAGIC_NUMBER - .word(0x04006003) # add 0x1 to MAGIC_NUMBER - .word(0x08006003) # add 0x1 to MAGIC_NUMBER - .word(0x10006003) # add 0x1 to MAGIC_NUMBER - .word(0x20006003) # add 0x1 to MAGIC_NUMBER - .word(0x40006003) # add 0x1 to MAGIC_NUMBER - .word(0x80006003) # add 0x1 to MAGIC_NUMBER -# unused fields in fence (these should _not_ add to MAGIC_NUMBER +# cv.elw + .word(0x0000B00B) # add 0x1 to MAGIC_NUMBER + .word(0x0000300B) # add 0x1 to MAGIC_NUMBER + .word(0x0001300B) # add 0x1 to MAGIC_NUMBER + .word(0x0002300B) # add 0x1 to MAGIC_NUMBER + .word(0x0004300B) # add 0x1 to MAGIC_NUMBER + .word(0x0008300B) # add 0x1 to MAGIC_NUMBER + .word(0x0010300B) # add 0x1 to MAGIC_NUMBER +# unused fields in fence (these should _not_ add to MAGIC_NUMBER) .word(0x00000F8F) # rd/imm5 =0b11111 .word(0x000F800F) # rs1 =0b11111 exit: @@ -449,7 +454,8 @@ continue_check: _check_3: li t4, 3 bne t6, t4, _check_11 - addi x26, x26, 0x10 # ebreak: add 0x10 to x26 + li x29, 0x100 + add x26, x26, x29 # ebreak: add 0x100 to x26 csrrc s0, mepc, x0 c.addi s0, 2 csrrw x0, mepc, s0 @@ -457,7 +463,8 @@ _check_3: _check_11: li t4, 11 bne t6, t4, _end_trap_Generic_Handler_ASM - addi x26, x26, 0x100 # ecall: add 0x100 to x26 + li x29, 0x1000 + add x26, x26, x29 # ecall: add 0x1000 to x26 csrrc s0, mepc, x0 c.addi s0, 4 csrrw x0, mepc, s0 @@ -493,7 +500,7 @@ _end_trap_Generic_Handler_ASM: lw x31,4(sp) addi sp,sp,120 mret - + _exit: j _exit diff --git a/cv32e40p/tests/programs/custom/jalr_test/test.c b/cv32e40p/tests/programs/custom/jalr_test/test.c new file mode 100644 index 0000000000..fc93ce3e80 --- /dev/null +++ b/cv32e40p/tests/programs/custom/jalr_test/test.c @@ -0,0 +1,95 @@ +// Copyright 2020 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 +// +// Description : Higlights unecessary Register File multiple writes +// + +#include + +int main() +{ + int error = 0; + + volatile unsigned int pc_save, check_result, pc_save_mem, pc_save_2; + + + __asm__ volatile("nop"); + __asm__ volatile("nop"); + + + pc_save_mem = 0; + +// Simple jalr use + __asm__ volatile("addi %0, x0, 0x0\n\t\ + auipc %1, 0x0\n\t\ + jalr x0, %1, 0xC\n\t\ + addi %1, %1, 0x01\n\t\ + addi %1, %1, 0x01\n\t\ + addi %1, %1, 0x01\n\t\ + addi %1, %1, 0x01\n\t\ + addi %1, %1, 0x01\n\t\ + addi %1, %1, 0x01" + : "=r"(check_result), "=r"(pc_save), "=r"(check_result) + : "r"(check_result) ); + +// Create dependence between ALU and jalr + __asm__ volatile("addi %0, x0, 0x0\n\t\ + auipc %1, 0x0\n\t\ + addi %1, %1, 0x08\n\t\ + jalr x0, %1, 0x4\n\t\ + addi %2, %2, 0x01\n\t\ + addi %2, %2, 0x01\n\t\ + addi %2, %2, 0x01\n\t\ + addi %2, %2, 0x01\n\t\ + addi %2, %2, 0x01\n\t\ + addi %2, %2, 0x01" + : "=r"(check_result), "=r"(pc_save), "=r"(check_result) + : "r"(pc_save), "r"(check_result) ); + +// Create dependence between load and jalr + __asm__ volatile("addi %0, x0, 0x0\n\t\ + auipc %1, 0x0\n\t\ + sw %1, 0(%2)\n\t\ + lw %3, 0(%2)\n\t\ + jalr x0, %3, 0x14\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01" + : "=r"(check_result), "=r"(pc_save), "=r"(pc_save_mem), "=r"(pc_save_2) + : "r"(check_result), "r"(pc_save), "r"(pc_save_mem), "r"(pc_save_2) ); + +// Load before jalr without dependency + __asm__ volatile("addi %0, x0, 0x0\n\t\ + auipc %1, 0x0\n\t\ + sw %1, 0(%2)\n\t\ + lw %3, 0(%2)\n\t\ + jalr x0, %1, 0x14\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01\n\t\ + addi %0, %0, 0x01" + : "=r"(check_result), "=r"(pc_save), "=r"(pc_save_mem), "=r"(pc_save_2) + : "r"(check_result), "r"(pc_save), "r"(pc_save_mem), "r"(pc_save_2) ); + + + return error; +} \ No newline at end of file diff --git a/cv32e40p/tests/programs/custom/jalr_test/test.yaml b/cv32e40p/tests/programs/custom/jalr_test/test.yaml new file mode 100644 index 0000000000..43262de5fb --- /dev/null +++ b/cv32e40p/tests/programs/custom/jalr_test/test.yaml @@ -0,0 +1,23 @@ +# Copyright 2020 OpenHW Group +# Copyright 2023 Dolphin Design +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +name: jalr_test +uvm_test: uvmt_cv32e40p_firmware_test_c +default_cflags: > + -O3 -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic +description: > + Directed test to cover all stall du to jalr \ No newline at end of file diff --git a/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S b/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S index f38ef49694..9774d7e607 100644 --- a/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S +++ b/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S @@ -34,9 +34,15 @@ #define TEST_PASS 123456789 #define TEST_FAIL 1 -#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 +#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 #define EXPECTED_ILLEGAL_INSTRUCTIONS 24 +#if defined(FPU) || defined(PULP) || defined(CLUSTER) +#define MIMPID_RESET_VALUE 0x00000001 +#else +#define MIMPID_RESET_VALUE 0x00000000 +#endif + main: li t0, (0x1 << 3) csrs mstatus, t0 @@ -102,282 +108,282 @@ main: # mhpmevent4 csrrci x5, 0x324, 0x0a - csrrc x5, 0x324, x0 - csrrc x0, 0x324, x5 + csrrc x5, 0x324, x0 + csrrc x0, 0x324, x5 csrrci x5, 0x324, 0x0a - csrrs x0, 0x324, x5 + csrrs x0, 0x324, x5 csrrsi x0, 0x324, 0x0a - csrrw x0, 0x324, x0 + csrrw x0, 0x324, x0 csrrwi x0, 0x324, 0x0a # mhpmevent5 csrrci x5, 0x325, 0x0a - csrrc x5, 0x325, x0 - csrrc x0, 0x325, x5 + csrrc x5, 0x325, x0 + csrrc x0, 0x325, x5 csrrci x5, 0x325, 0x0a - csrrs x0, 0x325, x5 + csrrs x0, 0x325, x5 csrrsi x0, 0x325, 0x0a - csrrw x0, 0x325, x0 + csrrw x0, 0x325, x0 csrrwi x0, 0x325, 0x0a # mhpmevent6 csrrci x5, 0x326, 0x0a - csrrc x5, 0x326, x0 - csrrc x0, 0x326, x5 + csrrc x5, 0x326, x0 + csrrc x0, 0x326, x5 csrrci x5, 0x326, 0x0a - csrrs x0, 0x326, x5 + csrrs x0, 0x326, x5 csrrsi x0, 0x326, 0x0a - csrrw x0, 0x326, x0 + csrrw x0, 0x326, x0 csrrwi x0, 0x326, 0x0a # mhpmevent7 csrrci x5, 0x327, 0x0a - csrrc x5, 0x327, x0 - csrrc x0, 0x327, x5 + csrrc x5, 0x327, x0 + csrrc x0, 0x327, x5 csrrci x5, 0x327, 0x0a - csrrs x0, 0x327, x5 + csrrs x0, 0x327, x5 csrrsi x0, 0x327, 0x0a - csrrw x0, 0x327, x0 + csrrw x0, 0x327, x0 csrrwi x0, 0x327, 0x0a # mhpmevent8 csrrci x5, 0x328, 0x0a - csrrc x5, 0x328, x0 - csrrc x0, 0x328, x5 + csrrc x5, 0x328, x0 + csrrc x0, 0x328, x5 csrrci x5, 0x328, 0x0a - csrrs x0, 0x328, x5 + csrrs x0, 0x328, x5 csrrsi x0, 0x328, 0x0a - csrrw x0, 0x328, x0 + csrrw x0, 0x328, x0 csrrwi x0, 0x328, 0x0a # mhpmevent9 csrrci x5, 0x329, 0x0a - csrrc x5, 0x329, x0 - csrrc x0, 0x329, x5 + csrrc x5, 0x329, x0 + csrrc x0, 0x329, x5 csrrci x5, 0x329, 0x0a - csrrs x0, 0x329, x5 + csrrs x0, 0x329, x5 csrrsi x0, 0x329, 0x0a - csrrw x0, 0x329, x0 + csrrw x0, 0x329, x0 csrrwi x0, 0x329, 0x0a # mhpmevent10 csrrci x5, 0x32a, 0x0a - csrrc x5, 0x32a, x0 - csrrc x0, 0x32a, x5 + csrrc x5, 0x32a, x0 + csrrc x0, 0x32a, x5 csrrci x5, 0x32a, 0x0a - csrrs x0, 0x32a, x5 + csrrs x0, 0x32a, x5 csrrsi x0, 0x32a, 0x0a - csrrw x0, 0x32a, x0 + csrrw x0, 0x32a, x0 csrrwi x0, 0x32a, 0x0a # mhpmevent11 csrrci x5, 0x32b, 0x0a - csrrc x5, 0x32b, x0 - csrrc x0, 0x32b, x5 + csrrc x5, 0x32b, x0 + csrrc x0, 0x32b, x5 csrrci x5, 0x32b, 0x0a - csrrs x0, 0x32b, x5 + csrrs x0, 0x32b, x5 csrrsi x0, 0x32b, 0x0a - csrrw x0, 0x32b, x0 + csrrw x0, 0x32b, x0 csrrwi x0, 0x32b, 0x0a # mhpmevent12 csrrci x5, 0x32c, 0x0a - csrrc x5, 0x32c, x0 - csrrc x0, 0x32c, x5 + csrrc x5, 0x32c, x0 + csrrc x0, 0x32c, x5 csrrci x5, 0x32c, 0x0a - csrrs x0, 0x32c, x5 + csrrs x0, 0x32c, x5 csrrsi x0, 0x32c, 0x0a - csrrw x0, 0x32c, x0 + csrrw x0, 0x32c, x0 csrrwi x0, 0x32c, 0x0a # mhpmevent13 csrrci x5, 0x32d, 0x0a - csrrc x5, 0x32d, x0 - csrrc x0, 0x32d, x5 + csrrc x5, 0x32d, x0 + csrrc x0, 0x32d, x5 csrrci x5, 0x32d, 0x0a - csrrs x0, 0x32d, x5 + csrrs x0, 0x32d, x5 csrrsi x0, 0x32d, 0x0a - csrrw x0, 0x32d, x0 + csrrw x0, 0x32d, x0 csrrwi x0, 0x32d, 0x0a # mhpmevent14 csrrci x5, 0x32e, 0x0a - csrrc x5, 0x32e, x0 - csrrc x0, 0x32e, x5 + csrrc x5, 0x32e, x0 + csrrc x0, 0x32e, x5 csrrci x5, 0x32e, 0x0a - csrrs x0, 0x32e, x5 + csrrs x0, 0x32e, x5 csrrsi x0, 0x32e, 0x0a - csrrw x0, 0x32e, x0 + csrrw x0, 0x32e, x0 csrrwi x0, 0x32e, 0x0a # mhpmevent15 csrrci x5, 0x32f, 0x0a - csrrc x5, 0x32f, x0 - csrrc x0, 0x32f, x5 + csrrc x5, 0x32f, x0 + csrrc x0, 0x32f, x5 csrrci x5, 0x32f, 0x0a - csrrs x0, 0x32f, x5 + csrrs x0, 0x32f, x5 csrrsi x0, 0x32f, 0x0a - csrrw x0, 0x32f, x0 + csrrw x0, 0x32f, x0 csrrwi x0, 0x32f, 0x0a # mhpmevent16 csrrci x5, 0x330, 0x0a - csrrc x5, 0x330, x0 - csrrc x0, 0x330, x5 + csrrc x5, 0x330, x0 + csrrc x0, 0x330, x5 csrrci x5, 0x330, 0x0a - csrrs x0, 0x330, x5 + csrrs x0, 0x330, x5 csrrsi x0, 0x330, 0x0a - csrrw x0, 0x330, x0 + csrrw x0, 0x330, x0 csrrwi x0, 0x330, 0x0a # mhpmevent17 csrrci x5, 0x331, 0x0a - csrrc x5, 0x331, x0 - csrrc x0, 0x331, x5 + csrrc x5, 0x331, x0 + csrrc x0, 0x331, x5 csrrci x5, 0x331, 0x0a - csrrs x0, 0x331, x5 + csrrs x0, 0x331, x5 csrrsi x0, 0x331, 0x0a - csrrw x0, 0x331, x0 + csrrw x0, 0x331, x0 csrrwi x0, 0x331, 0x0a # mhpmevent18 csrrci x5, 0x332, 0x0a - csrrc x5, 0x332, x0 - csrrc x0, 0x332, x5 + csrrc x5, 0x332, x0 + csrrc x0, 0x332, x5 csrrci x5, 0x332, 0x0a - csrrs x0, 0x332, x5 + csrrs x0, 0x332, x5 csrrsi x0, 0x332, 0x0a - csrrw x0, 0x332, x0 + csrrw x0, 0x332, x0 csrrwi x0, 0x332, 0x0a # mhpmevent19 csrrci x5, 0x333, 0x0a - csrrc x5, 0x333, x0 - csrrc x0, 0x333, x5 + csrrc x5, 0x333, x0 + csrrc x0, 0x333, x5 csrrci x5, 0x333, 0x0a - csrrs x0, 0x333, x5 + csrrs x0, 0x333, x5 csrrsi x0, 0x333, 0x0a - csrrw x0, 0x333, x0 + csrrw x0, 0x333, x0 csrrwi x0, 0x333, 0x0a # mhpmevent20 csrrci x5, 0x334, 0x0a - csrrc x5, 0x334, x0 - csrrc x0, 0x334, x5 + csrrc x5, 0x334, x0 + csrrc x0, 0x334, x5 csrrci x5, 0x334, 0x0a - csrrs x0, 0x334, x5 + csrrs x0, 0x334, x5 csrrsi x0, 0x334, 0x0a - csrrw x0, 0x334, x0 + csrrw x0, 0x334, x0 csrrwi x0, 0x334, 0x0a # mhpmevent21 csrrci x5, 0x335, 0x0a - csrrc x5, 0x335, x0 - csrrc x0, 0x335, x5 + csrrc x5, 0x335, x0 + csrrc x0, 0x335, x5 csrrci x5, 0x335, 0x0a - csrrs x0, 0x335, x5 + csrrs x0, 0x335, x5 csrrsi x0, 0x335, 0x0a - csrrw x0, 0x335, x0 + csrrw x0, 0x335, x0 csrrwi x0, 0x335, 0x0a # mhpmevent22 csrrci x5, 0x336, 0x0a - csrrc x5, 0x336, x0 - csrrc x0, 0x336, x5 + csrrc x5, 0x336, x0 + csrrc x0, 0x336, x5 csrrci x5, 0x336, 0x0a - csrrs x0, 0x336, x5 + csrrs x0, 0x336, x5 csrrsi x0, 0x336, 0x0a - csrrw x0, 0x336, x0 + csrrw x0, 0x336, x0 csrrwi x0, 0x336, 0x0a # mhpmevent23 csrrci x5, 0x337, 0x0a - csrrc x5, 0x337, x0 - csrrc x0, 0x337, x5 + csrrc x5, 0x337, x0 + csrrc x0, 0x337, x5 csrrci x5, 0x337, 0x0a - csrrs x0, 0x337, x5 + csrrs x0, 0x337, x5 csrrsi x0, 0x337, 0x0a - csrrw x0, 0x337, x0 + csrrw x0, 0x337, x0 csrrwi x0, 0x337, 0x0a # mhpmevent24 csrrci x5, 0x338, 0x0a - csrrc x5, 0x338, x0 - csrrc x0, 0x338, x5 + csrrc x5, 0x338, x0 + csrrc x0, 0x338, x5 csrrci x5, 0x338, 0x0a - csrrs x0, 0x338, x5 + csrrs x0, 0x338, x5 csrrsi x0, 0x338, 0x0a - csrrw x0, 0x338, x0 + csrrw x0, 0x338, x0 csrrwi x0, 0x338, 0x0a # mhpmevent25 csrrci x5, 0x339, 0x0a - csrrc x5, 0x339, x0 - csrrc x0, 0x339, x5 + csrrc x5, 0x339, x0 + csrrc x0, 0x339, x5 csrrci x5, 0x339, 0x0a - csrrs x0, 0x339, x5 + csrrs x0, 0x339, x5 csrrsi x0, 0x339, 0x0a - csrrw x0, 0x339, x0 + csrrw x0, 0x339, x0 csrrwi x0, 0x339, 0x0a # mhpmevent26 csrrci x5, 0x33a, 0x0a - csrrc x5, 0x33a, x0 - csrrc x0, 0x33a, x5 + csrrc x5, 0x33a, x0 + csrrc x0, 0x33a, x5 csrrci x5, 0x33a, 0x0a - csrrs x0, 0x33a, x5 + csrrs x0, 0x33a, x5 csrrsi x0, 0x33a, 0x0a - csrrw x0, 0x33a, x0 + csrrw x0, 0x33a, x0 csrrwi x0, 0x33a, 0x0a # mhpmevent27 csrrci x5, 0x33b, 0x0a - csrrc x5, 0x33b, x0 - csrrc x0, 0x33b, x5 + csrrc x5, 0x33b, x0 + csrrc x0, 0x33b, x5 csrrci x5, 0x33b, 0x0a - csrrs x0, 0x33b, x5 + csrrs x0, 0x33b, x5 csrrsi x0, 0x33b, 0x0a - csrrw x0, 0x33b, x0 + csrrw x0, 0x33b, x0 csrrwi x0, 0x33b, 0x0a # mhpmevent28 csrrci x5, 0x33c, 0x0a - csrrc x5, 0x33c, x0 - csrrc x0, 0x33c, x5 + csrrc x5, 0x33c, x0 + csrrc x0, 0x33c, x5 csrrci x5, 0x33c, 0x0a - csrrs x0, 0x33c, x5 + csrrs x0, 0x33c, x5 csrrsi x0, 0x33c, 0x0a - csrrw x0, 0x33c, x0 + csrrw x0, 0x33c, x0 csrrwi x0, 0x33c, 0x0a # mhpmevent29 csrrci x5, 0x33d, 0x0a - csrrc x5, 0x33d, x0 - csrrc x0, 0x33d, x5 + csrrc x5, 0x33d, x0 + csrrc x0, 0x33d, x5 csrrci x5, 0x33d, 0x0a - csrrs x0, 0x33d, x5 + csrrs x0, 0x33d, x5 csrrsi x0, 0x33d, 0x0a - csrrw x0, 0x33d, x0 + csrrw x0, 0x33d, x0 csrrwi x0, 0x33d, 0x0a # mhpmevent30 csrrci x5, 0x33e, 0x0a - csrrc x5, 0x33e, x0 - csrrc x0, 0x33e, x5 + csrrc x5, 0x33e, x0 + csrrc x0, 0x33e, x5 csrrci x5, 0x33e, 0x0a - csrrs x0, 0x33e, x5 + csrrs x0, 0x33e, x5 csrrsi x0, 0x33e, 0x0a - csrrw x0, 0x33e, x0 + csrrw x0, 0x33e, x0 csrrwi x0, 0x33e, 0x0a # mhpmevent31 csrrci x5, 0x33f, 0x0a - csrrc x5, 0x33f, x0 - csrrc x0, 0x33f, x5 + csrrc x5, 0x33f, x0 + csrrc x0, 0x33f, x5 csrrci x5, 0x33f, 0x0a - csrrs x0, 0x33f, x5 + csrrs x0, 0x33f, x5 csrrsi x0, 0x33f, 0x0a - csrrw x0, 0x33f, x0 + csrrw x0, 0x33f, x0 csrrwi x0, 0x33f, 0x0a ################ @@ -394,282 +400,282 @@ main: # mhpmcounter4 csrrci x5, 0xB04, 0x0a - csrrc x5, 0xB04, x0 - csrrc x0, 0xB04, x5 + csrrc x5, 0xB04, x0 + csrrc x0, 0xB04, x5 csrrci x5, 0xB04, 0x0a - csrrs x0, 0xB04, x5 + csrrs x0, 0xB04, x5 csrrsi x0, 0xB04, 0x0a - csrrw x0, 0xB04, x0 + csrrw x0, 0xB04, x0 csrrwi x0, 0xB04, 0x0a # mhpmcounter5 csrrci x5, 0xB05, 0x0a - csrrc x5, 0xB05, x0 - csrrc x0, 0xB05, x5 + csrrc x5, 0xB05, x0 + csrrc x0, 0xB05, x5 csrrci x5, 0xB05, 0x0a - csrrs x0, 0xB05, x5 + csrrs x0, 0xB05, x5 csrrsi x0, 0xB05, 0x0a - csrrw x0, 0xB05, x0 + csrrw x0, 0xB05, x0 csrrwi x0, 0xB05, 0x0a # mhpmcounter6 csrrci x5, 0xB06, 0x0a - csrrc x5, 0xB06, x0 - csrrc x0, 0xB06, x5 + csrrc x5, 0xB06, x0 + csrrc x0, 0xB06, x5 csrrci x5, 0xB06, 0x0a - csrrs x0, 0xB06, x5 + csrrs x0, 0xB06, x5 csrrsi x0, 0xB06, 0x0a - csrrw x0, 0xB06, x0 + csrrw x0, 0xB06, x0 csrrwi x0, 0xB06, 0x0a # mhpmcounter7 csrrci x5, 0xB07, 0x0a - csrrc x5, 0xB07, x0 - csrrc x0, 0xB07, x5 + csrrc x5, 0xB07, x0 + csrrc x0, 0xB07, x5 csrrci x5, 0xB07, 0x0a - csrrs x0, 0xB07, x5 + csrrs x0, 0xB07, x5 csrrsi x0, 0xB07, 0x0a - csrrw x0, 0xB07, x0 + csrrw x0, 0xB07, x0 csrrwi x0, 0xB07, 0x0a # mhpmcounter8 csrrci x5, 0xB08, 0x0a - csrrc x5, 0xB08, x0 - csrrc x0, 0xB08, x5 + csrrc x5, 0xB08, x0 + csrrc x0, 0xB08, x5 csrrci x5, 0xB08, 0x0a - csrrs x0, 0xB08, x5 + csrrs x0, 0xB08, x5 csrrsi x0, 0xB08, 0x0a - csrrw x0, 0xB08, x0 + csrrw x0, 0xB08, x0 csrrwi x0, 0xB08, 0x0a # mhpmcounter9 csrrci x5, 0xB09, 0x0a - csrrc x5, 0xB09, x0 - csrrc x0, 0xB09, x5 + csrrc x5, 0xB09, x0 + csrrc x0, 0xB09, x5 csrrci x5, 0xB09, 0x0a - csrrs x0, 0xB09, x5 + csrrs x0, 0xB09, x5 csrrsi x0, 0xB09, 0x0a - csrrw x0, 0xB09, x0 + csrrw x0, 0xB09, x0 csrrwi x0, 0xB09, 0x0a # mhpmcounter10 csrrci x5, 0xB0A, 0x0a - csrrc x5, 0xB0A, x0 - csrrc x0, 0xB0A, x5 + csrrc x5, 0xB0A, x0 + csrrc x0, 0xB0A, x5 csrrci x5, 0xB0A, 0x0a - csrrs x0, 0xB0A, x5 + csrrs x0, 0xB0A, x5 csrrsi x0, 0xB0A, 0x0a - csrrw x0, 0xB0A, x0 + csrrw x0, 0xB0A, x0 csrrwi x0, 0xB0A, 0x0a # mhpmcounter11 csrrci x5, 0xB0B, 0x0a - csrrc x5, 0xB0B, x0 - csrrc x0, 0xB0B, x5 + csrrc x5, 0xB0B, x0 + csrrc x0, 0xB0B, x5 csrrci x5, 0xB0B, 0x0a - csrrs x0, 0xB0B, x5 + csrrs x0, 0xB0B, x5 csrrsi x0, 0xB0B, 0x0a - csrrw x0, 0xB0B, x0 + csrrw x0, 0xB0B, x0 csrrwi x0, 0xB0B, 0x0a # mhpmcounter12 csrrci x5, 0xB0C, 0x0a - csrrc x5, 0xB0C, x0 - csrrc x0, 0xB0C, x5 + csrrc x5, 0xB0C, x0 + csrrc x0, 0xB0C, x5 csrrci x5, 0xB0C, 0x0a - csrrs x0, 0xB0C, x5 + csrrs x0, 0xB0C, x5 csrrsi x0, 0xB0C, 0x0a - csrrw x0, 0xB0C, x0 + csrrw x0, 0xB0C, x0 csrrwi x0, 0xB0C, 0x0a # mhpmcounter13 csrrci x5, 0xB0D, 0x0a - csrrc x5, 0xB0D, x0 - csrrc x0, 0xB0D, x5 + csrrc x5, 0xB0D, x0 + csrrc x0, 0xB0D, x5 csrrci x5, 0xB0D, 0x0a - csrrs x0, 0xB0D, x5 + csrrs x0, 0xB0D, x5 csrrsi x0, 0xB0D, 0x0a - csrrw x0, 0xB0D, x0 + csrrw x0, 0xB0D, x0 csrrwi x0, 0xB0D, 0x0a # mhpmcounter14 csrrci x5, 0xB0E, 0x0a - csrrc x5, 0xB0E, x0 - csrrc x0, 0xB0E, x5 + csrrc x5, 0xB0E, x0 + csrrc x0, 0xB0E, x5 csrrci x5, 0xB0E, 0x0a - csrrs x0, 0xB0E, x5 + csrrs x0, 0xB0E, x5 csrrsi x0, 0xB0E, 0x0a - csrrw x0, 0xB0E, x0 + csrrw x0, 0xB0E, x0 csrrwi x0, 0xB0E, 0x0a # mhpmcounter15 csrrci x5, 0xB0F, 0x0a - csrrc x5, 0xB0F, x0 - csrrc x0, 0xB0F, x5 + csrrc x5, 0xB0F, x0 + csrrc x0, 0xB0F, x5 csrrci x5, 0xB0F, 0x0a - csrrs x0, 0xB0F, x5 + csrrs x0, 0xB0F, x5 csrrsi x0, 0xB0F, 0x0a - csrrw x0, 0xB0F, x0 + csrrw x0, 0xB0F, x0 csrrwi x0, 0xB0F, 0x0a # mhpmcounter16 csrrci x5, 0xB10, 0x0a - csrrc x5, 0xB10, x0 - csrrc x0, 0xB10, x5 + csrrc x5, 0xB10, x0 + csrrc x0, 0xB10, x5 csrrci x5, 0xB10, 0x0a - csrrs x0, 0xB10, x5 + csrrs x0, 0xB10, x5 csrrsi x0, 0xB10, 0x0a - csrrw x0, 0xB10, x0 + csrrw x0, 0xB10, x0 csrrwi x0, 0xB10, 0x0a # mhpmcounter17 csrrci x5, 0xB11, 0x0a - csrrc x5, 0xB11, x0 - csrrc x0, 0xB11, x5 + csrrc x5, 0xB11, x0 + csrrc x0, 0xB11, x5 csrrci x5, 0xB11, 0x0a - csrrs x0, 0xB11, x5 + csrrs x0, 0xB11, x5 csrrsi x0, 0xB11, 0x0a - csrrw x0, 0xB11, x0 + csrrw x0, 0xB11, x0 csrrwi x0, 0xB11, 0x0a # mhpmcounter18 csrrci x5, 0xB12, 0x0a - csrrc x5, 0xB12, x0 - csrrc x0, 0xB12, x5 + csrrc x5, 0xB12, x0 + csrrc x0, 0xB12, x5 csrrci x5, 0xB12, 0x0a - csrrs x0, 0xB12, x5 + csrrs x0, 0xB12, x5 csrrsi x0, 0xB12, 0x0a - csrrw x0, 0xB12, x0 + csrrw x0, 0xB12, x0 csrrwi x0, 0xB12, 0x0a # mhpmcounter19 csrrci x5, 0xB13, 0x0a - csrrc x5, 0xB13, x0 - csrrc x0, 0xB13, x5 + csrrc x5, 0xB13, x0 + csrrc x0, 0xB13, x5 csrrci x5, 0xB13, 0x0a - csrrs x0, 0xB13, x5 + csrrs x0, 0xB13, x5 csrrsi x0, 0xB13, 0x0a - csrrw x0, 0xB13, x0 + csrrw x0, 0xB13, x0 csrrwi x0, 0xB13, 0x0a # mhpmcounter20 csrrci x5, 0xB14, 0x0a - csrrc x5, 0xB14, x0 - csrrc x0, 0xB14, x5 + csrrc x5, 0xB14, x0 + csrrc x0, 0xB14, x5 csrrci x5, 0xB14, 0x0a - csrrs x0, 0xB14, x5 + csrrs x0, 0xB14, x5 csrrsi x0, 0xB14, 0x0a - csrrw x0, 0xB14, x0 + csrrw x0, 0xB14, x0 csrrwi x0, 0xB14, 0x0a # mhpmcounter21 csrrci x5, 0xB15, 0x0a - csrrc x5, 0xB15, x0 - csrrc x0, 0xB15, x5 + csrrc x5, 0xB15, x0 + csrrc x0, 0xB15, x5 csrrci x5, 0xB15, 0x0a - csrrs x0, 0xB15, x5 + csrrs x0, 0xB15, x5 csrrsi x0, 0xB15, 0x0a - csrrw x0, 0xB15, x0 + csrrw x0, 0xB15, x0 csrrwi x0, 0xB15, 0x0a # mhpmcounter22 csrrci x5, 0xB16, 0x0a - csrrc x5, 0xB16, x0 - csrrc x0, 0xB16, x5 + csrrc x5, 0xB16, x0 + csrrc x0, 0xB16, x5 csrrci x5, 0xB16, 0x0a - csrrs x0, 0xB16, x5 + csrrs x0, 0xB16, x5 csrrsi x0, 0xB16, 0x0a - csrrw x0, 0xB16, x0 + csrrw x0, 0xB16, x0 csrrwi x0, 0xB16, 0x0a # mhpmcounter23 csrrci x5, 0xB17, 0x0a - csrrc x5, 0xB17, x0 - csrrc x0, 0xB17, x5 + csrrc x5, 0xB17, x0 + csrrc x0, 0xB17, x5 csrrci x5, 0xB17, 0x0a - csrrs x0, 0xB17, x5 + csrrs x0, 0xB17, x5 csrrsi x0, 0xB17, 0x0a - csrrw x0, 0xB17, x0 + csrrw x0, 0xB17, x0 csrrwi x0, 0xB17, 0x0a # mhpmcounter24 csrrci x5, 0xB18, 0x0a - csrrc x5, 0xB18, x0 - csrrc x0, 0xB18, x5 + csrrc x5, 0xB18, x0 + csrrc x0, 0xB18, x5 csrrci x5, 0xB18, 0x0a - csrrs x0, 0xB18, x5 + csrrs x0, 0xB18, x5 csrrsi x0, 0xB18, 0x0a - csrrw x0, 0xB18, x0 + csrrw x0, 0xB18, x0 csrrwi x0, 0xB18, 0x0a # mhpmcounter25 csrrci x5, 0xB19, 0x0a - csrrc x5, 0xB19, x0 - csrrc x0, 0xB19, x5 + csrrc x5, 0xB19, x0 + csrrc x0, 0xB19, x5 csrrci x5, 0xB19, 0x0a - csrrs x0, 0xB19, x5 + csrrs x0, 0xB19, x5 csrrsi x0, 0xB19, 0x0a - csrrw x0, 0xB19, x0 + csrrw x0, 0xB19, x0 csrrwi x0, 0xB19, 0x0a # mhpmcounter26 csrrci x5, 0xB1A, 0x0a - csrrc x5, 0xB1A, x0 - csrrc x0, 0xB1A, x5 + csrrc x5, 0xB1A, x0 + csrrc x0, 0xB1A, x5 csrrci x5, 0xB1A, 0x0a - csrrs x0, 0xB1A, x5 + csrrs x0, 0xB1A, x5 csrrsi x0, 0xB1A, 0x0a - csrrw x0, 0xB1A, x0 + csrrw x0, 0xB1A, x0 csrrwi x0, 0xB1A, 0x0a # mhpmcounter27 csrrci x5, 0xB1B, 0x0a - csrrc x5, 0xB1B, x0 - csrrc x0, 0xB1B, x5 + csrrc x5, 0xB1B, x0 + csrrc x0, 0xB1B, x5 csrrci x5, 0xB1B, 0x0a - csrrs x0, 0xB1B, x5 + csrrs x0, 0xB1B, x5 csrrsi x0, 0xB1B, 0x0a - csrrw x0, 0xB1B, x0 + csrrw x0, 0xB1B, x0 csrrwi x0, 0xB1B, 0x0a # mhpmcounter28 csrrci x5, 0xB1C, 0x0a - csrrc x5, 0xB1C, x0 - csrrc x0, 0xB1C, x5 + csrrc x5, 0xB1C, x0 + csrrc x0, 0xB1C, x5 csrrci x5, 0xB1C, 0x0a - csrrs x0, 0xB1C, x5 + csrrs x0, 0xB1C, x5 csrrsi x0, 0xB1C, 0x0a - csrrw x0, 0xB1C, x0 + csrrw x0, 0xB1C, x0 csrrwi x0, 0xB1C, 0x0a # mhpmcounter29 csrrci x5, 0xB1D, 0x0a - csrrc x5, 0xB1D, x0 - csrrc x0, 0xB1D, x5 + csrrc x5, 0xB1D, x0 + csrrc x0, 0xB1D, x5 csrrci x5, 0xB1D, 0x0a - csrrs x0, 0xB1D, x5 + csrrs x0, 0xB1D, x5 csrrsi x0, 0xB1D, 0x0a - csrrw x0, 0xB1D, x0 + csrrw x0, 0xB1D, x0 csrrwi x0, 0xB1D, 0x0a # mhpmcounter30 csrrci x5, 0xB1E, 0x0a - csrrc x5, 0xB1E, x0 - csrrc x0, 0xB1E, x5 + csrrc x5, 0xB1E, x0 + csrrc x0, 0xB1E, x5 csrrci x5, 0xB1E, 0x0a - csrrs x0, 0xB1E, x5 + csrrs x0, 0xB1E, x5 csrrsi x0, 0xB1E, 0x0a - csrrw x0, 0xB1E, x0 + csrrw x0, 0xB1E, x0 csrrwi x0, 0xB1E, 0x0a # mhpmcounter31 csrrci x5, 0xB1F, 0x0a - csrrc x5, 0xB1F, x0 - csrrc x0, 0xB1F, x5 + csrrc x5, 0xB1F, x0 + csrrc x0, 0xB1F, x5 csrrci x5, 0xB1F, 0x0a - csrrs x0, 0xB1F, x5 + csrrs x0, 0xB1F, x5 csrrsi x0, 0xB1F, 0x0a - csrrw x0, 0xB1F, x0 + csrrw x0, 0xB1F, x0 csrrwi x0, 0xB1F, 0x0a ################ @@ -696,272 +702,272 @@ main: # mhpmcounterh5 csrrci x5, 0xB85, 0x0a - csrrc x5, 0xB85, x0 - csrrc x0, 0xB85, x5 + csrrc x5, 0xB85, x0 + csrrc x0, 0xB85, x5 csrrci x5, 0xB85, 0x0a - csrrs x0, 0xB85, x5 + csrrs x0, 0xB85, x5 csrrsi x0, 0xB85, 0x0a - csrrw x0, 0xB85, x0 + csrrw x0, 0xB85, x0 csrrwi x0, 0xB85, 0x0a # mhpmcounterh6 csrrci x5, 0xB86, 0x0a - csrrc x5, 0xB86, x0 - csrrc x0, 0xB86, x5 + csrrc x5, 0xB86, x0 + csrrc x0, 0xB86, x5 csrrci x5, 0xB86, 0x0a - csrrs x0, 0xB86, x5 + csrrs x0, 0xB86, x5 csrrsi x0, 0xB86, 0x0a - csrrw x0, 0xB86, x0 + csrrw x0, 0xB86, x0 csrrwi x0, 0xB86, 0x0a # mhpmcounterh7 csrrci x5, 0xB87, 0x0a - csrrc x5, 0xB87, x0 - csrrc x0, 0xB87, x5 + csrrc x5, 0xB87, x0 + csrrc x0, 0xB87, x5 csrrci x5, 0xB87, 0x0a - csrrs x0, 0xB87, x5 + csrrs x0, 0xB87, x5 csrrsi x0, 0xB87, 0x0a - csrrw x0, 0xB87, x0 + csrrw x0, 0xB87, x0 csrrwi x0, 0xB87, 0x0a # mhpmcounterh8 csrrci x5, 0xB88, 0x0a - csrrc x5, 0xB88, x0 - csrrc x0, 0xB88, x5 + csrrc x5, 0xB88, x0 + csrrc x0, 0xB88, x5 csrrci x5, 0xB88, 0x0a - csrrs x0, 0xB88, x5 + csrrs x0, 0xB88, x5 csrrsi x0, 0xB88, 0x0a - csrrw x0, 0xB88, x0 + csrrw x0, 0xB88, x0 csrrwi x0, 0xB88, 0x0a # mhpmcounterh9 csrrci x5, 0xB89, 0x0a - csrrc x5, 0xB89, x0 - csrrc x0, 0xB89, x5 + csrrc x5, 0xB89, x0 + csrrc x0, 0xB89, x5 csrrci x5, 0xB89, 0x0a - csrrs x0, 0xB89, x5 + csrrs x0, 0xB89, x5 csrrsi x0, 0xB89, 0x0a - csrrw x0, 0xB89, x0 + csrrw x0, 0xB89, x0 csrrwi x0, 0xB89, 0x0a # mhpmcounterh10 csrrci x5, 0xB8A, 0x0a - csrrc x5, 0xB8A, x0 - csrrc x0, 0xB8A, x5 + csrrc x5, 0xB8A, x0 + csrrc x0, 0xB8A, x5 csrrci x5, 0xB8A, 0x0a - csrrs x0, 0xB8A, x5 + csrrs x0, 0xB8A, x5 csrrsi x0, 0xB8A, 0x0a - csrrw x0, 0xB8A, x0 + csrrw x0, 0xB8A, x0 csrrwi x0, 0xB8A, 0x0a # mhpmcounterh11 csrrci x5, 0xB8B, 0x0a - csrrc x5, 0xB8B, x0 - csrrc x0, 0xB8B, x5 + csrrc x5, 0xB8B, x0 + csrrc x0, 0xB8B, x5 csrrci x5, 0xB8B, 0x0a - csrrs x0, 0xB8B, x5 + csrrs x0, 0xB8B, x5 csrrsi x0, 0xB8B, 0x0a - csrrw x0, 0xB8B, x0 + csrrw x0, 0xB8B, x0 csrrwi x0, 0xB8B, 0x0a # mhpmcounterh12 csrrci x5, 0xB8C, 0x0a - csrrc x5, 0xB8C, x0 - csrrc x0, 0xB8C, x5 + csrrc x5, 0xB8C, x0 + csrrc x0, 0xB8C, x5 csrrci x5, 0xB8C, 0x0a - csrrs x0, 0xB8C, x5 + csrrs x0, 0xB8C, x5 csrrsi x0, 0xB8C, 0x0a - csrrw x0, 0xB8C, x0 + csrrw x0, 0xB8C, x0 csrrwi x0, 0xB8C, 0x0a # mhpmcounterh13 csrrci x5, 0xB8D, 0x0a - csrrc x5, 0xB8D, x0 - csrrc x0, 0xB8D, x5 + csrrc x5, 0xB8D, x0 + csrrc x0, 0xB8D, x5 csrrci x5, 0xB8D, 0x0a - csrrs x0, 0xB8D, x5 + csrrs x0, 0xB8D, x5 csrrsi x0, 0xB8D, 0x0a - csrrw x0, 0xB8D, x0 + csrrw x0, 0xB8D, x0 csrrwi x0, 0xB8D, 0x0a # mhpmcounterh14 csrrci x5, 0xB8E, 0x0a - csrrc x5, 0xB8E, x0 - csrrc x0, 0xB8E, x5 + csrrc x5, 0xB8E, x0 + csrrc x0, 0xB8E, x5 csrrci x5, 0xB8E, 0x0a - csrrs x0, 0xB8E, x5 + csrrs x0, 0xB8E, x5 csrrsi x0, 0xB8E, 0x0a - csrrw x0, 0xB8E, x0 + csrrw x0, 0xB8E, x0 csrrwi x0, 0xB8E, 0x0a # mhpmcounterh15 csrrci x5, 0xB8F, 0x0a - csrrc x5, 0xB8F, x0 - csrrc x0, 0xB8F, x5 + csrrc x5, 0xB8F, x0 + csrrc x0, 0xB8F, x5 csrrci x5, 0xB8F, 0x0a - csrrs x0, 0xB8F, x5 + csrrs x0, 0xB8F, x5 csrrsi x0, 0xB8F, 0x0a - csrrw x0, 0xB8F, x0 + csrrw x0, 0xB8F, x0 csrrwi x0, 0xB8F, 0x0a # mhpmcounterh16 csrrci x5, 0xB90, 0x0a - csrrc x5, 0xB90, x0 - csrrc x0, 0xB90, x5 + csrrc x5, 0xB90, x0 + csrrc x0, 0xB90, x5 csrrci x5, 0xB90, 0x0a - csrrs x0, 0xB90, x5 + csrrs x0, 0xB90, x5 csrrsi x0, 0xB90, 0x0a - csrrw x0, 0xB90, x0 + csrrw x0, 0xB90, x0 csrrwi x0, 0xB90, 0x0a # mhpmcounterh17 csrrci x5, 0xB91, 0x0a - csrrc x5, 0xB91, x0 - csrrc x0, 0xB91, x5 + csrrc x5, 0xB91, x0 + csrrc x0, 0xB91, x5 csrrci x5, 0xB91, 0x0a - csrrs x0, 0xB91, x5 + csrrs x0, 0xB91, x5 csrrsi x0, 0xB91, 0x0a - csrrw x0, 0xB91, x0 + csrrw x0, 0xB91, x0 csrrwi x0, 0xB91, 0x0a # mhpmcounterh18 csrrci x5, 0xB92, 0x0a - csrrc x5, 0xB92, x0 - csrrc x0, 0xB92, x5 + csrrc x5, 0xB92, x0 + csrrc x0, 0xB92, x5 csrrci x5, 0xB92, 0x0a - csrrs x0, 0xB92, x5 + csrrs x0, 0xB92, x5 csrrsi x0, 0xB92, 0x0a - csrrw x0, 0xB92, x0 + csrrw x0, 0xB92, x0 csrrwi x0, 0xB92, 0x0a # mhpmcounterh19 csrrci x5, 0xB93, 0x0a - csrrc x5, 0xB93, x0 - csrrc x0, 0xB93, x5 + csrrc x5, 0xB93, x0 + csrrc x0, 0xB93, x5 csrrci x5, 0xB93, 0x0a - csrrs x0, 0xB93, x5 + csrrs x0, 0xB93, x5 csrrsi x0, 0xB93, 0x0a - csrrw x0, 0xB93, x0 + csrrw x0, 0xB93, x0 csrrwi x0, 0xB93, 0x0a # mhpmcounterh20 csrrci x5, 0xB94, 0x0a - csrrc x5, 0xB94, x0 - csrrc x0, 0xB94, x5 + csrrc x5, 0xB94, x0 + csrrc x0, 0xB94, x5 csrrci x5, 0xB94, 0x0a - csrrs x0, 0xB94, x5 + csrrs x0, 0xB94, x5 csrrsi x0, 0xB94, 0x0a - csrrw x0, 0xB94, x0 + csrrw x0, 0xB94, x0 csrrwi x0, 0xB94, 0x0a # mhpmcounterh21 csrrci x5, 0xB95, 0x0a - csrrc x5, 0xB95, x0 - csrrc x0, 0xB95, x5 + csrrc x5, 0xB95, x0 + csrrc x0, 0xB95, x5 csrrci x5, 0xB95, 0x0a - csrrs x0, 0xB95, x5 + csrrs x0, 0xB95, x5 csrrsi x0, 0xB95, 0x0a - csrrw x0, 0xB95, x0 + csrrw x0, 0xB95, x0 csrrwi x0, 0xB95, 0x0a # mhpmcounterh22 csrrci x5, 0xB96, 0x0a - csrrc x5, 0xB96, x0 - csrrc x0, 0xB96, x5 + csrrc x5, 0xB96, x0 + csrrc x0, 0xB96, x5 csrrci x5, 0xB96, 0x0a - csrrs x0, 0xB96, x5 + csrrs x0, 0xB96, x5 csrrsi x0, 0xB96, 0x0a - csrrw x0, 0xB96, x0 + csrrw x0, 0xB96, x0 csrrwi x0, 0xB96, 0x0a # mhpmcounterh23 csrrci x5, 0xB97, 0x0a - csrrc x5, 0xB97, x0 - csrrc x0, 0xB97, x5 + csrrc x5, 0xB97, x0 + csrrc x0, 0xB97, x5 csrrci x5, 0xB97, 0x0a - csrrs x0, 0xB97, x5 + csrrs x0, 0xB97, x5 csrrsi x0, 0xB97, 0x0a - csrrw x0, 0xB97, x0 + csrrw x0, 0xB97, x0 csrrwi x0, 0xB97, 0x0a # mhpmcounterh24 csrrci x5, 0xB98, 0x0a - csrrc x5, 0xB98, x0 - csrrc x0, 0xB98, x5 + csrrc x5, 0xB98, x0 + csrrc x0, 0xB98, x5 csrrci x5, 0xB98, 0x0a - csrrs x0, 0xB98, x5 + csrrs x0, 0xB98, x5 csrrsi x0, 0xB98, 0x0a - csrrw x0, 0xB98, x0 + csrrw x0, 0xB98, x0 csrrwi x0, 0xB98, 0x0a # mhpmcounterh25 csrrci x5, 0xB99, 0x0a - csrrc x5, 0xB99, x0 - csrrc x0, 0xB99, x5 + csrrc x5, 0xB99, x0 + csrrc x0, 0xB99, x5 csrrci x5, 0xB99, 0x0a - csrrs x0, 0xB99, x5 + csrrs x0, 0xB99, x5 csrrsi x0, 0xB99, 0x0a - csrrw x0, 0xB99, x0 + csrrw x0, 0xB99, x0 csrrwi x0, 0xB99, 0x0a # mhpmcounterh26 csrrci x5, 0xB9A, 0x0a - csrrc x5, 0xB9A, x0 - csrrc x0, 0xB9A, x5 + csrrc x5, 0xB9A, x0 + csrrc x0, 0xB9A, x5 csrrci x5, 0xB9A, 0x0a - csrrs x0, 0xB9A, x5 + csrrs x0, 0xB9A, x5 csrrsi x0, 0xB9A, 0x0a - csrrw x0, 0xB9A, x0 + csrrw x0, 0xB9A, x0 csrrwi x0, 0xB9A, 0x0a # mhpmcounterh27 csrrci x5, 0xB9B, 0x0a - csrrc x5, 0xB9B, x0 - csrrc x0, 0xB9B, x5 + csrrc x5, 0xB9B, x0 + csrrc x0, 0xB9B, x5 csrrci x5, 0xB9B, 0x0a - csrrs x0, 0xB9B, x5 + csrrs x0, 0xB9B, x5 csrrsi x0, 0xB9B, 0x0a - csrrw x0, 0xB9B, x0 + csrrw x0, 0xB9B, x0 csrrwi x0, 0xB9B, 0x0a # mhpmcounterh28 csrrci x5, 0xB9C, 0x0a - csrrc x5, 0xB9C, x0 - csrrc x0, 0xB9C, x5 + csrrc x5, 0xB9C, x0 + csrrc x0, 0xB9C, x5 csrrci x5, 0xB9C, 0x0a - csrrs x0, 0xB9C, x5 + csrrs x0, 0xB9C, x5 csrrsi x0, 0xB9C, 0x0a - csrrw x0, 0xB9C, x0 + csrrw x0, 0xB9C, x0 csrrwi x0, 0xB9C, 0x0a # mhpmcounterh29 csrrci x5, 0xB9D, 0x0a - csrrc x5, 0xB9D, x0 - csrrc x0, 0xB9D, x5 + csrrc x5, 0xB9D, x0 + csrrc x0, 0xB9D, x5 csrrci x5, 0xB9D, 0x0a - csrrs x0, 0xB9D, x5 + csrrs x0, 0xB9D, x5 csrrsi x0, 0xB9D, 0x0a - csrrw x0, 0xB9D, x0 + csrrw x0, 0xB9D, x0 csrrwi x0, 0xB9D, 0x0a # mhpmcounterh30 csrrci x5, 0xB9E, 0x0a - csrrc x5, 0xB9E, x0 - csrrc x0, 0xB9E, x5 + csrrc x5, 0xB9E, x0 + csrrc x0, 0xB9E, x5 csrrci x5, 0xB9E, 0x0a - csrrs x0, 0xB9E, x5 + csrrs x0, 0xB9E, x5 csrrsi x0, 0xB9E, 0x0a - csrrw x0, 0xB9E, x0 + csrrw x0, 0xB9E, x0 csrrwi x0, 0xB9E, 0x0a # mhpmcounterh31 csrrci x5, 0xB9F, 0x0a - csrrc x5, 0xB9F, x0 - csrrc x0, 0xB9F, x5 + csrrc x5, 0xB9F, x0 + csrrc x0, 0xB9F, x5 csrrci x5, 0xB9F, 0x0a - csrrs x0, 0xB9F, x5 + csrrs x0, 0xB9F, x5 csrrsi x0, 0xB9F, 0x0a - csrrw x0, 0xB9F, x0 + csrrw x0, 0xB9F, x0 csrrwi x0, 0xB9F, 0x0a ############################################################################### @@ -1004,7 +1010,7 @@ main: csrrwi x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR csrrc x5, 3859, x0 # not illegal - li x30, 0x00000000 + li x30, MIMPID_RESET_VALUE bne x5, x30, fail # mhartid @@ -1086,7 +1092,7 @@ u_sw_irq_handler: csrrw x0, mepc, x27 c.addi x31, 1 mret - + _exit: j _exit diff --git a/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S b/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S index 51fa2b5853..1b6e3284d4 100644 --- a/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S +++ b/cv32e40p/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S @@ -39,12 +39,24 @@ _start: .section .text _start_main: - #ifdef NO_PULP - #define EXP_MISA 0x40001104 - #else - #define EXP_MISA 0x40801104 - #endif +#define ADD_X(val) ((val) | (1 << 23)) +#define ADD_F(val) ((val) | (1 << 5)) +#define BASE_MISA 0x40001104 + +#if defined(NO_PULP) +#define EXP_MISA BASE_MISA +#else + #if defined(PULP) && defined(FPU) && !defined(ZFINX) + #define EXP_MISA ADD_X(ADD_F(BASE_MISA)) + #elif defined(PULP) && defined(FPU) && defined(ZFINX) + #define EXP_MISA ADD_X((BASE_MISA)) + #elif defined(PULP) + #define EXP_MISA ADD_X((BASE_MISA)) + #else + #define EXP_MISA BASE_MISA + #endif +#endif ############################################################################### # Script generated code to verify write/read access of these CSRs. diff --git a/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c b/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c index 7eb84e8dfc..3fec29b971 100644 --- a/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c +++ b/cv32e40p/tests/programs/custom/modeled_csr_por/modeled_csr_por.c @@ -33,10 +33,23 @@ #include #include +#define ADD_X(val) ((val) | (1 << 23)) +#define ADD_F(val) ((val) | (1 << 5)) + +#define BASE_MISA 0x40001104 + #ifdef NO_PULP -#define EXP_MISA 0x40001104 +#define EXP_MISA BASE_MISA #else -#define EXP_MISA 0x40801104 + #if defined(PULP) && defined(FPU) && !defined(ZFINX) + #define EXP_MISA ADD_X(ADD_F(BASE_MISA)) + #elif defined(PULP) && defined(FPU) && defined(ZFINX) + #define EXP_MISA ADD_X((BASE_MISA)) + #elif defined(PULP) + #define EXP_MISA ADD_X((BASE_MISA)) + #else + #define EXP_MISA BASE_MISA + #endif #endif int main(int argc, char *argv[]) diff --git a/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c b/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c index d24756d75a..8c1ecef253 100644 --- a/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c +++ b/cv32e40p/tests/programs/custom/requested_csr_por/requested_csr_por.c @@ -31,10 +31,23 @@ #include #include +#define ADD_X(val) ((val) | (1 << 23)) +#define ADD_F(val) ((val) | (1 << 5)) + +#define BASE_MISA 0x40001104 + #ifdef NO_PULP -#define EXP_MISA 0x40001104 +#define EXP_MISA BASE_MISA #else -#define EXP_MISA 0x40801104 + #if defined(PULP) && defined(FPU) && !defined(ZFINX) + #define EXP_MISA ADD_X(ADD_F(BASE_MISA)) + #elif defined(PULP) && defined(FPU) && defined(ZFINX) + #define EXP_MISA ADD_X((BASE_MISA)) + #elif defined(PULP) + #define EXP_MISA ADD_X((BASE_MISA)) + #else + #define EXP_MISA BASE_MISA + #endif #endif int main(int argc, char *argv[])