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evg_VME-300-fout.subs
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##EVG Base
file "$(mrfioc2_TEMPLATES=db)/evg-vme-300.db"
{
{
DlyCompensation-Beacon-Sel=0, # 0 = Disable, 1 = Enable : Delay compensation beacon generator
DlyCompensation-Master-Sel=0, # 0 = Disable, 1 = Enable : Master enable for delay compensation
FCT-ClrVioSrc="SIN-TIMAST-TMA:EvmClrLnkVio-Cmd CP", # when a record referenced here is processed, link violations on all ports will be cleared.
# NOTE: The value of FCT-ClrVioSrc needs to include CP to ensure the value is updated when the source changes.
# The CP can not be hidden in the template file because this would lead to an invalid input link CP when no substitution value for FCT-ClrVioSrc is provided.
# Recommended setting for SwissFEL is SIN-TIMAST-TMA:EvmClrLnkVio-Cmd CP
AcTrig-Phase-SP=0.0, #0-25.5 : EVG AC Phase Shifter
AcTrig-Divider-SP=0, #0-255 : EVG AC Divider
AcTrig-Bypass-Sel=1, #0 = Off, 1 = On : Bypass AC divider and Phase shifter
AcTrig-SyncSrc-Sel=1, #0 = EvtClk, 1 = Mxc7, 2 = Front IN 1, 3 = Front IN 2 : Select what AC will be synced to
AcTrig-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
AcTrig-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
EvtClk-Source-Sel=3, #0 = FracSynth, 1 = External, 2 = PXIe 100 MHz, 3 = Recovered RX clock, 4 = PXIe 10 MHz, 5 = External source for fanouts, FractSynth for upstream port, 6 = Recovered RX clock / 2 : EVG Evt Clk Source
EvtClk-RFFreq-SP=500, #50-1600 : EVG RF Frequency [MHz]
EvtClk-RFDiv-SP=4, #0-32 : RF Divider
EvtClk-FracSynFreq-SP=142.8, #50-142.8 : Fractional Synthesizer Freq [MHz]
EvtClk-PLL-Bandwidth-Sel=4, #0 = HM, 1 = HL, 2 = MH, 3 = MM, 4 = ML: PLL Bandwidth Select (see Silicon Labs Si5317 datasheet)
## Distributed bus configuration
Dbus0-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 0, 3 = From upstream EVG : EVG DBUS Source
Dbus1-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 1, 3 = From upstream EVG : EVG DBUS Source
Dbus2-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 2, 3 = From upstream EVG : EVG DBUS Source
Dbus3-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 3, 3 = From upstream EVG : EVG DBUS Source
Dbus4-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 4, 3 = From upstream EVG : EVG DBUS Source
Dbus5-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 5, 3 = From upstream EVG : EVG DBUS Source
Dbus6-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 6, 3 = From upstream EVG : EVG DBUS Source
Dbus7-Map-Sel=0, #0 = Off, 1 = Front input, 2= Mxc 7, 3 = From upstream EVG : EVG DBUS Source
## Soft sequence masking / enable
SoftSeqMask-SP=0, # Masks soft sequence events (software)
SoftSeqEnable-SP=0, # Enables soft sequence events (software)
## Input configuration
# Front Inputs
FrontInp0-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
FrontInp0-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp0-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp0-SeqMask-SP=0, # Masks soft sequence events
FrontInp0-SeqEnable-SP=0, # Enables soft sequence events
FrontInp1-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
FrontInp1-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp1-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp1-SeqMask-SP=0, # Masks soft sequence events
FrontInp1-SeqEnable-SP=0, # Enables soft sequence events
FrontInp2-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
FrontInp2-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
FrontInp2-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
FrontInp2-SeqMask-SP=0, # Masks soft sequence events
FrontInp2-SeqEnable-SP=0, # Enables soft sequence events
# Front Inputs Phase Monitoring
FrontInp0-PhMonSRate="1 second", # Scan rate of monitoring records
FrontInp0-Ph-Sel=0, # 0=@0, 1=@90, 2=@180, 3=@270 degree : Phase for sampling input signal
FrontInp0-DBusPhSRate="1 second" # Scan rate of DBus phase status
FrontInp1-PhMonSRate="1 second", # Scan rate of monitoring records
FrontInp1-Ph-Sel=0, # 0=@0, 1=@90, 2=@180, 3=@270 degree : Phase for sampling input signal
FrontInp1-DBusPhSRate="1 second" # Scan rate of DBus phase status
FrontInp2-PhMonSRate="1 second", # Scan rate of monitoring records
FrontInp2-Ph-Sel=0, # 0=@0, 1=@90, 2=@180, 3=@270 degree : Phase for sampling input signal
FrontInp2-DBusPhSRate="1 second" # Scan rate of DBus phase status
# Rear Inputs
RearInp0-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp0-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp0-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp0-SeqMask-SP=0, # Masks soft sequence events
RearInp0-SeqEnable-SP=0, # Enables soft sequence events
RearInp1-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp1-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp1-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp1-SeqMask-SP=0, # Masks soft sequence events
RearInp1-SeqEnable-SP=0, # Enables soft sequence events
RearInp2-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp2-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp2-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp2-SeqMask-SP=0, # Masks soft sequence events
RearInp2-SeqEnable-SP=0, # Enables soft sequence events
RearInp3-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp3-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp3-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp3-SeqMask-SP=0, # Masks soft sequence events
RearInp3-SeqEnable-SP=0, # Enables soft sequence events
RearInp4-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp4-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp4-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp4-SeqMask-SP=0, # Masks soft sequence events
RearInp4-SeqEnable-SP=0, # Enables soft sequence events
RearInp5-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp5-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp5-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp5-SeqMask-SP=0, # Masks soft sequence events
RearInp5-SeqEnable-SP=0, # Enables soft sequence events
RearInp6-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp6-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp6-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp6-SeqMask-SP=0, # Masks soft sequence events
RearInp6-SeqEnable-SP=0, # Enables soft sequence events
RearInp7-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp7-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp7-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp7-SeqMask-SP=0, # Masks soft sequence events
RearInp7-SeqEnable-SP=0, # Enables soft sequence events
RearInp8-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp8-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp8-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp8-SeqMask-SP=0, # Masks soft sequence events
RearInp8-SeqEnable-SP=0, # Enables soft sequence events
RearInp9-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp9-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp9-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp9-SeqMask-SP=0, # Masks soft sequence events
RearInp9-SeqEnable-SP=0, # Enables soft sequence events
RearInp10-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp10-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp10-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp10-SeqMask-SP=0, # Masks soft sequence events
RearInp10-SeqEnable-SP=0, # Enables soft sequence events
RearInp11-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp11-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp11-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp11-SeqMask-SP=0, # Masks soft sequence events
RearInp11-SeqEnable-SP=0, # Enables soft sequence events
RearInp12-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp12-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp12-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp12-SeqMask-SP=0, # Masks soft sequence events
RearInp12-SeqEnable-SP=0, # Enables soft sequence events
RearInp13-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp13-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp13-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp13-SeqMask-SP=0, # Masks soft sequence events
RearInp13-SeqEnable-SP=0, # Enables soft sequence events
RearInp14-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp14-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp14-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp14-SeqMask-SP=0, # Masks soft sequence events
RearInp14-SeqEnable-SP=0, # Enables soft sequence events
RearInp15-EnaIrq-Sel=0, #0 = Disabled, 1 = Enabled : Enable External Input IRQ (1PPS input)
RearInp15-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
RearInp15-DbusSrc0-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc1-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc2-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc3-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc4-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc5-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc6-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-DbusSrc7-SP=0, #0 = Disable, 1 = Enable: Map to DBus bit
RearInp15-SeqMask-SP=0, # Masks soft sequence events
RearInp15-SeqEnable-SP=0, # Enables soft sequence events
## Output configuration
# Available -Src-SP choices:
# 32 DBus 0
# 33 DBus 1
# 34 DBus 2
# 35 DBus 3
# 36 DBus 4
# 37 DBus 5
# 38 DBus 6
# 39 Dbus 7
# 40 Mxc 0
# 41 Mxc 1
# 42 Mxc 2
# 43 Mxc 3
# 44 Mxc 4
# 45 Mxc 5
# 46 Mxc 6
# 47 Mxc 7
# 48 AC trigger logic output
# 63 Force Low
# 62 Force High
# Rear outputs (transition board)
RearOut0-Src-SP=63,
RearOut1-Src-SP=63,
RearOut2-Src-SP=63,
RearOut3-Src-SP=63,
RearOut4-Src-SP=63,
RearOut5-Src-SP=63,
RearOut6-Src-SP=63,
RearOut7-Src-SP=63,
RearOut8-Src-SP=63,
RearOut9-Src-SP=63,
RearOut10-Src-SP=63,
RearOut11-Src-SP=63,
RearOut12-Src-SP=63,
RearOut13-Src-SP=63,
RearOut14-Src-SP=63,
RearOut15-Src-SP=63,
## Event trigger configuration
TrigEvt0-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt0-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt1-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt1-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt2-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt2-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt3-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt3-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt4-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt4-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt5-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt5-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt6-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt6-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
TrigEvt7-Enable-Sel=1, #0 = Disabled, 1 = Enabled : EVG Trigger Event Enable
TrigEvt7-EvtCode-SP=0, #0-255 = Event code : EVG Trigger Event Code
## Multiplexed counters configuration
Mxc0-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc0-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc0-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc0-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc0-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc1-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc1-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc1-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc1-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc2-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc2-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc2-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc2-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc3-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc3-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc3-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc3-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc4-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc4-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc4-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc4-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc5-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc5-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc5-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc5-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc6-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc6-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc6-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc6-TrigSrc7-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-Polarity-Sel=0, #0 = Normal, 1 = Inverted : EVG Mux Output Polarity
Mxc7-Frequency-SP=1, #0.034-62500000 EVG Mux Frequency (Hz) - depends on event clock speed
Mxc7-Prescaler-SP=124920, # Overriden by Frequency-SP
Mxc7-TrigSrc0-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc1-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc2-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc3-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc4-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc5-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc6-SP=0, #0 = Disable, 1 = Enable: Map to event trigger
Mxc7-TrigSrc7-SP=0 #0 = Disable, 1 = Enable: Map to event trigger
}
}
##EVG soft sequences (we need 2 for ping-pong loader)
#file "$(mrfioc2_TEMPLATES=db)/evgSoftSeq.template"
#{
# {
# SEQNUM = 1,
# NELM = 2047,
# TSINPMODE = 0, ## 0 = EGU, 1 = Ticks
# TSRES = 2, ## 0 = Seconds, 1 = Miliseconds, 2 = Microseconds, 3 = Nanoseconds
# TRIGSRC = 1, ## 0 = None, 1-8 = Mxc0-7, 9 = AC, 10 = Soft, 11 = Front0, 12 = Front1, 13 = Univ0, 14 = Univ1, 15 = Univ2,
# RUNMODE = 2 ## 0 = Normal, 1 = Automatic, 2 = Single
# }
#
# {
# SEQNUM = 2,
# NELM = 2047,
# TSINPMODE = 0, ## 0 = EGU, 1 = Ticks
# TSRES = 2, ## 0 = Seconds, 1 = Miliseconds, 2 = Microseconds, 3 = Nanoseconds
# TRIGSRC = 1, ## 0 = None, 1-8 = Mxc0-7, 9 = AC, 10 = Soft, 11 = Front0, 12 = Front1, 13 = Univ0, 14 = Univ1, 15 = Univ2,
# RUNMODE = 2 ## 0 = Normal, 1 = Automatic, 2 = Single
# }
#}
## Health monitoring
## Template for monitoring health status of the device
#
# Macros:
# SYS = System name (auto expanded by parent)
# DEVICE = Event receiver / timing card name (same as mrmEvgSetupVME()) Eg. EVG0. (auto expanded by parent)
# MON-PORTS = Ports on the event generator (SFP 0 - SFP 8) to monitor. Binary selection. (auto expanded by parent)
# Examples:
# MON-PORTS = 0x00 -> do not monitor SFPs
# MON-PORTS = 0x01 -> monitor SFP 0
# MON-PORTS = 0x02 -> monitor SFP 1
# MON-PORTS = 0x03 -> monitor SFP 0 and SFP 1
# MON-PORTS = 0x04 -> monitor SFP 2
# MON-PORTS = 0x85 -> monitor SFP 0, SFP 2 and SFP 8
# MON-PORTS = 0x80 -> monitor SFP 8
#
file "$(mrfioc2_TEMPLATES=db)/evg-health.template"
{
{}
}
## Flash access support
## Uncomment this substitution to load records that expose read and write access to the flash chip on the device.
#
# Macros:
# SYS = System name (auto expanded by parent)
# DEVICE = Event receiver / timing card name (same as mrmEvgSetupVME()) Eg. EVG0. (auto expanded by parent)
#
#file "$(mrfioc2_TEMPLATES=db)/flash.template"
#{
# {}
#}