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optimizer.c
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// SPDX-License-Identifier: LGPL-2.1-or-later
/*
* Copyright (C) 2014-2021 Paul Cercueil <[email protected]>
*/
#include "constprop.h"
#include "lightrec-config.h"
#include "disassembler.h"
#include "lightrec.h"
#include "memmanager.h"
#include "optimizer.h"
#include "regcache.h"
#include <errno.h>
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
#define IF_OPT(opt, ptr) ((opt) ? (ptr) : NULL)
struct optimizer_list {
void (**optimizers)(struct opcode *);
unsigned int nb_optimizers;
};
static bool is_nop(union code op);
bool is_unconditional_jump(union code c)
{
switch (c.i.op) {
case OP_SPECIAL:
return c.r.op == OP_SPECIAL_JR || c.r.op == OP_SPECIAL_JALR;
case OP_J:
case OP_JAL:
return true;
case OP_BEQ:
case OP_BLEZ:
return c.i.rs == c.i.rt;
case OP_REGIMM:
return (c.r.rt == OP_REGIMM_BGEZ ||
c.r.rt == OP_REGIMM_BGEZAL) && c.i.rs == 0;
default:
return false;
}
}
bool is_syscall(union code c)
{
return (c.i.op == OP_SPECIAL && c.r.op == OP_SPECIAL_SYSCALL) ||
(c.i.op == OP_CP0 && (c.r.rs == OP_CP0_MTC0 ||
c.r.rs == OP_CP0_CTC0) &&
(c.r.rd == 12 || c.r.rd == 13));
}
static u64 opcode_read_mask(union code op)
{
switch (op.i.op) {
case OP_SPECIAL:
switch (op.r.op) {
case OP_SPECIAL_SYSCALL:
case OP_SPECIAL_BREAK:
return 0;
case OP_SPECIAL_JR:
case OP_SPECIAL_JALR:
case OP_SPECIAL_MTHI:
case OP_SPECIAL_MTLO:
return BIT(op.r.rs);
case OP_SPECIAL_MFHI:
return BIT(REG_HI);
case OP_SPECIAL_MFLO:
return BIT(REG_LO);
case OP_SPECIAL_SLL:
if (!op.r.imm)
return 0;
fallthrough;
case OP_SPECIAL_SRL:
case OP_SPECIAL_SRA:
return BIT(op.r.rt);
default:
return BIT(op.r.rs) | BIT(op.r.rt);
}
case OP_CP0:
switch (op.r.rs) {
case OP_CP0_MTC0:
case OP_CP0_CTC0:
return BIT(op.r.rt);
default:
return 0;
}
case OP_CP2:
if (op.r.op == OP_CP2_BASIC) {
switch (op.r.rs) {
case OP_CP2_BASIC_MTC2:
case OP_CP2_BASIC_CTC2:
return BIT(op.r.rt);
default:
break;
}
}
return 0;
case OP_J:
case OP_JAL:
case OP_LUI:
case OP_META_BIOS:
return 0;
case OP_BEQ:
if (op.i.rs == op.i.rt)
return 0;
fallthrough;
case OP_BNE:
case OP_LWL:
case OP_LWR:
case OP_SB:
case OP_SH:
case OP_SWL:
case OP_SW:
case OP_SWR:
case OP_META_LWU:
case OP_META_SWU:
return BIT(op.i.rs) | BIT(op.i.rt);
case OP_META:
return BIT(op.m.rs);
default:
return BIT(op.i.rs);
}
}
static u64 mult_div_write_mask(union code op)
{
u64 flags;
if (!OPT_FLAG_MULT_DIV)
return BIT(REG_LO) | BIT(REG_HI);
if (op.r.rd)
flags = BIT(op.r.rd);
else
flags = BIT(REG_LO);
if (op.r.imm)
flags |= BIT(op.r.imm);
else
flags |= BIT(REG_HI);
return flags;
}
u64 opcode_write_mask(union code op)
{
switch (op.i.op) {
case OP_META_MULT2:
case OP_META_MULTU2:
return mult_div_write_mask(op);
case OP_META:
return BIT(op.m.rd);
case OP_SPECIAL:
switch (op.r.op) {
case OP_SPECIAL_JR:
case OP_SPECIAL_SYSCALL:
case OP_SPECIAL_BREAK:
return 0;
case OP_SPECIAL_MULT:
case OP_SPECIAL_MULTU:
case OP_SPECIAL_DIV:
case OP_SPECIAL_DIVU:
return mult_div_write_mask(op);
case OP_SPECIAL_MTHI:
return BIT(REG_HI);
case OP_SPECIAL_MTLO:
return BIT(REG_LO);
case OP_SPECIAL_SLL:
if (!op.r.imm)
return 0;
fallthrough;
default:
return BIT(op.r.rd);
}
case OP_ADDI:
case OP_ADDIU:
case OP_SLTI:
case OP_SLTIU:
case OP_ANDI:
case OP_ORI:
case OP_XORI:
case OP_LUI:
case OP_LB:
case OP_LH:
case OP_LWL:
case OP_LW:
case OP_LBU:
case OP_LHU:
case OP_LWR:
case OP_META_LWU:
return BIT(op.i.rt);
case OP_JAL:
return BIT(31);
case OP_CP0:
switch (op.r.rs) {
case OP_CP0_MFC0:
case OP_CP0_CFC0:
return BIT(op.i.rt);
default:
return 0;
}
case OP_CP2:
if (op.r.op == OP_CP2_BASIC) {
switch (op.r.rs) {
case OP_CP2_BASIC_MFC2:
case OP_CP2_BASIC_CFC2:
return BIT(op.i.rt);
default:
break;
}
}
return 0;
case OP_REGIMM:
switch (op.r.rt) {
case OP_REGIMM_BLTZAL:
case OP_REGIMM_BGEZAL:
return BIT(31);
default:
return 0;
}
default:
return 0;
}
}
bool opcode_reads_register(union code op, u8 reg)
{
return opcode_read_mask(op) & BIT(reg);
}
bool opcode_writes_register(union code op, u8 reg)
{
return opcode_write_mask(op) & BIT(reg);
}
static int find_prev_writer(const struct opcode *list, unsigned int offset, u8 reg)
{
union code c;
unsigned int i;
if (op_flag_sync(list[offset].flags))
return -1;
for (i = offset; i > 0; i--) {
c = list[i - 1].c;
if (opcode_writes_register(c, reg)) {
if (i > 1 && has_delay_slot(list[i - 2].c))
break;
return i - 1;
}
if (op_flag_sync(list[i - 1].flags) ||
has_delay_slot(c) ||
opcode_reads_register(c, reg))
break;
}
return -1;
}
static int find_next_reader(const struct opcode *list, unsigned int offset, u8 reg)
{
unsigned int i;
union code c;
if (op_flag_sync(list[offset].flags))
return -1;
for (i = offset; ; i++) {
c = list[i].c;
if (opcode_reads_register(c, reg))
return i;
if (op_flag_sync(list[i].flags)
|| (op_flag_no_ds(list[i].flags) && has_delay_slot(c))
|| is_delay_slot(list, i)
|| opcode_writes_register(c, reg))
break;
}
return -1;
}
static bool reg_is_dead(const struct opcode *list, unsigned int offset, u8 reg)
{
unsigned int i;
if (op_flag_sync(list[offset].flags) || is_delay_slot(list, offset))
return false;
for (i = offset + 1; ; i++) {
if (opcode_reads_register(list[i].c, reg))
return false;
if (opcode_writes_register(list[i].c, reg))
return true;
if (is_syscall(list[i].c))
return false;
if (has_delay_slot(list[i].c)) {
if (op_flag_no_ds(list[i].flags) ||
opcode_reads_register(list[i + 1].c, reg))
return false;
return opcode_writes_register(list[i + 1].c, reg);
}
}
}
static bool reg_is_read(const struct opcode *list,
unsigned int a, unsigned int b, u8 reg)
{
/* Return true if reg is read in one of the opcodes of the interval
* [a, b[ */
for (; a < b; a++) {
if (!is_nop(list[a].c) && opcode_reads_register(list[a].c, reg))
return true;
}
return false;
}
static bool reg_is_written(const struct opcode *list,
unsigned int a, unsigned int b, u8 reg)
{
/* Return true if reg is written in one of the opcodes of the interval
* [a, b[ */
for (; a < b; a++) {
if (!is_nop(list[a].c) && opcode_writes_register(list[a].c, reg))
return true;
}
return false;
}
static bool reg_is_read_or_written(const struct opcode *list,
unsigned int a, unsigned int b, u8 reg)
{
return reg_is_read(list, a, b, reg) || reg_is_written(list, a, b, reg);
}
static bool opcode_is_mfc(union code op)
{
switch (op.i.op) {
case OP_CP0:
switch (op.r.rs) {
case OP_CP0_MFC0:
case OP_CP0_CFC0:
return true;
default:
break;
}
break;
case OP_CP2:
if (op.r.op == OP_CP2_BASIC) {
switch (op.r.rs) {
case OP_CP2_BASIC_MFC2:
case OP_CP2_BASIC_CFC2:
return true;
default:
break;
}
}
break;
default:
break;
}
return false;
}
static bool opcode_is_load(union code op)
{
switch (op.i.op) {
case OP_LB:
case OP_LH:
case OP_LWL:
case OP_LW:
case OP_LBU:
case OP_LHU:
case OP_LWR:
case OP_LWC2:
case OP_META_LWU:
return true;
default:
return false;
}
}
static bool opcode_is_store(union code op)
{
switch (op.i.op) {
case OP_SB:
case OP_SH:
case OP_SW:
case OP_SWL:
case OP_SWR:
case OP_SWC2:
case OP_META_SWU:
return true;
default:
return false;
}
}
bool opcode_has_load_delay(union code op)
{
return (opcode_is_load(op) && op.i.rt && op.i.op != OP_LWC2)
|| opcode_is_mfc(op);
}
static u8 opcode_get_io_size(union code op)
{
switch (op.i.op) {
case OP_LB:
case OP_LBU:
case OP_SB:
return 8;
case OP_LH:
case OP_LHU:
case OP_SH:
return 16;
default:
return 32;
}
}
bool opcode_is_io(union code op)
{
return opcode_is_load(op) || opcode_is_store(op);
}
/* TODO: Complete */
static bool is_nop(union code op)
{
if (opcode_writes_register(op, 0)) {
switch (op.i.op) {
case OP_CP0:
return op.r.rs != OP_CP0_MFC0;
case OP_LB:
case OP_LH:
case OP_LWL:
case OP_LW:
case OP_LBU:
case OP_LHU:
case OP_LWR:
case OP_META_LWU:
return false;
default:
return true;
}
}
switch (op.i.op) {
case OP_SPECIAL:
switch (op.r.op) {
case OP_SPECIAL_AND:
return op.r.rd == op.r.rt && op.r.rd == op.r.rs;
case OP_SPECIAL_ADD:
case OP_SPECIAL_ADDU:
return (op.r.rd == op.r.rt && op.r.rs == 0) ||
(op.r.rd == op.r.rs && op.r.rt == 0);
case OP_SPECIAL_SUB:
case OP_SPECIAL_SUBU:
return op.r.rd == op.r.rs && op.r.rt == 0;
case OP_SPECIAL_OR:
if (op.r.rd == op.r.rt)
return op.r.rd == op.r.rs || op.r.rs == 0;
else
return (op.r.rd == op.r.rs) && op.r.rt == 0;
case OP_SPECIAL_SLL:
case OP_SPECIAL_SRA:
case OP_SPECIAL_SRL:
return op.r.rd == op.r.rt && op.r.imm == 0;
case OP_SPECIAL_MFHI:
case OP_SPECIAL_MFLO:
return op.r.rd == 0;
default:
return false;
}
case OP_ORI:
case OP_ADDI:
case OP_ADDIU:
return op.i.rt == op.i.rs && op.i.imm == 0;
case OP_BGTZ:
return (op.i.rs == 0 || op.i.imm == 1);
case OP_REGIMM:
return (op.i.op == OP_REGIMM_BLTZ ||
op.i.op == OP_REGIMM_BLTZAL) &&
(op.i.rs == 0 || op.i.imm == 1);
case OP_BNE:
return (op.i.rs == op.i.rt || op.i.imm == 1);
default:
return false;
}
}
static void lightrec_optimize_sll_sra(struct opcode *list, unsigned int offset,
struct constprop_data *v)
{
struct opcode *ldop = NULL, *curr = &list[offset], *next;
struct opcode *to_change, *to_nop;
int idx, idx2;
if (curr->r.imm != 24 && curr->r.imm != 16)
return;
if (is_delay_slot(list, offset))
return;
idx = find_next_reader(list, offset + 1, curr->r.rd);
if (idx < 0)
return;
next = &list[idx];
if (next->i.op != OP_SPECIAL || next->r.op != OP_SPECIAL_SRA ||
next->r.imm != curr->r.imm || next->r.rt != curr->r.rd)
return;
if (curr->r.rd != curr->r.rt && next->r.rd != next->r.rt) {
/* sll rY, rX, 16
* ...
* sra rZ, rY, 16 */
if (!reg_is_dead(list, idx, curr->r.rd) ||
reg_is_read_or_written(list, offset, idx, next->r.rd))
return;
/* If rY is dead after the SRL, and rZ is not used after the SLL,
* we can change rY to rZ */
pr_debug("Detected SLL/SRA with middle temp register\n");
curr->r.rd = next->r.rd;
next->r.rt = curr->r.rd;
}
/* We got a SLL/SRA combo. If imm #16, that's a cast to s16.
* If imm #24 that's a cast to s8.
*
* First of all, make sure that the target register of the SLL is not
* read after the SRA. */
if (curr->r.rd == curr->r.rt) {
/* sll rX, rX, 16
* ...
* sra rY, rX, 16 */
to_change = next;
to_nop = curr;
/* rX is used after the SRA - we cannot convert it. */
if (curr->r.rd != next->r.rd && !reg_is_dead(list, idx, curr->r.rd))
return;
} else {
/* sll rY, rX, 16
* ...
* sra rY, rY, 16 */
to_change = curr;
to_nop = next;
}
idx2 = find_prev_writer(list, offset, curr->r.rt);
if (idx2 >= 0) {
/* Note that PSX games sometimes do casts after
* a LHU or LBU; in this case we can change the
* load opcode to a LH or LB, and the cast can
* be changed to a MOV or a simple NOP. */
ldop = &list[idx2];
if (next->r.rd != ldop->i.rt &&
!reg_is_dead(list, idx, ldop->i.rt))
ldop = NULL;
else if (curr->r.imm == 16 && ldop->i.op == OP_LHU)
ldop->i.op = OP_LH;
else if (curr->r.imm == 24 && ldop->i.op == OP_LBU)
ldop->i.op = OP_LB;
else
ldop = NULL;
if (ldop) {
if (next->r.rd == ldop->i.rt) {
to_change->opcode = 0;
} else if (reg_is_dead(list, idx, ldop->i.rt) &&
!reg_is_read_or_written(list, idx2 + 1, idx, next->r.rd)) {
/* The target register of the SRA is dead after the
* LBU/LHU; we can change the target register of the
* LBU/LHU to the one of the SRA. */
v[ldop->i.rt].known = 0;
v[ldop->i.rt].sign = 0;
ldop->i.rt = next->r.rd;
to_change->opcode = 0;
} else {
to_change->i.op = OP_META;
to_change->m.op = OP_META_MOV;
to_change->m.rd = next->r.rd;
to_change->m.rs = ldop->i.rt;
}
if (to_nop->r.imm == 24)
pr_debug("Convert LBU+SLL+SRA to LB\n");
else
pr_debug("Convert LHU+SLL+SRA to LH\n");
v[ldop->i.rt].known = 0;
v[ldop->i.rt].sign = 0xffffff80 << (24 - curr->r.imm);
}
}
if (!ldop) {
pr_debug("Convert SLL/SRA #%u to EXT%c\n",
curr->r.imm, curr->r.imm == 24 ? 'C' : 'S');
to_change->m.rs = curr->r.rt;
to_change->m.op = to_nop->r.imm == 24 ? OP_META_EXTC : OP_META_EXTS;
to_change->i.op = OP_META;
}
to_nop->opcode = 0;
}
static void
lightrec_remove_useless_lui(struct block *block, unsigned int offset,
const struct constprop_data *v)
{
struct opcode *list = block->opcode_list,
*op = &block->opcode_list[offset];
int reader;
if (!op_flag_sync(op->flags) && is_known(v, op->i.rt) &&
v[op->i.rt].value == op->i.imm << 16) {
pr_debug("Converting duplicated LUI to NOP\n");
op->opcode = 0x0;
return;
}
if (op->i.imm != 0 || op->i.rt == 0 || is_delay_slot(list, offset))
return;
reader = find_next_reader(list, offset + 1, op->i.rt);
if (reader <= 0)
return;
if (opcode_writes_register(list[reader].c, op->i.rt) ||
reg_is_dead(list, reader, op->i.rt)) {
pr_debug("Removing useless LUI 0x0\n");
if (list[reader].i.rs == op->i.rt)
list[reader].i.rs = 0;
if (list[reader].i.op == OP_SPECIAL &&
list[reader].i.rt == op->i.rt)
list[reader].i.rt = 0;
op->opcode = 0x0;
}
}
static void lightrec_lui_to_movi(struct block *block, unsigned int offset)
{
struct opcode *ori, *lui = &block->opcode_list[offset];
int next;
if (lui->i.op != OP_LUI)
return;
next = find_next_reader(block->opcode_list, offset + 1, lui->i.rt);
if (next > 0) {
ori = &block->opcode_list[next];
switch (ori->i.op) {
case OP_ORI:
case OP_ADDI:
case OP_ADDIU:
if (ori->i.rs == ori->i.rt && ori->i.imm) {
ori->flags |= LIGHTREC_MOVI;
lui->flags |= LIGHTREC_MOVI;
}
break;
}
}
}
static void lightrec_modify_lui(struct block *block, unsigned int offset)
{
union code c, *lui = &block->opcode_list[offset].c;
bool stop = false, stop_next = false;
unsigned int i;
for (i = offset + 1; !stop && i < block->nb_ops; i++) {
c = block->opcode_list[i].c;
stop = stop_next;
if ((opcode_is_store(c) && c.i.rt == lui->i.rt)
|| (!opcode_is_load(c) && opcode_reads_register(c, lui->i.rt)))
break;
if (opcode_writes_register(c, lui->i.rt)) {
if (c.i.op == OP_LWL || c.i.op == OP_LWR) {
/* LWL/LWR only partially write their target register;
* therefore the LUI should not write a different value. */
break;
}
pr_debug("Convert LUI at offset 0x%x to kuseg\n",
(i - 1) << 2);
lui->i.imm = kunseg(lui->i.imm << 16) >> 16;
break;
}
if (has_delay_slot(c))
stop_next = true;
}
}
static int lightrec_transform_branches(struct lightrec_state *state,
struct block *block)
{
struct opcode *op;
unsigned int i;
s32 offset;
for (i = 0; i < block->nb_ops; i++) {
op = &block->opcode_list[i];
switch (op->i.op) {
case OP_J:
if (is_delay_slot(block->opcode_list, i)) {
/* Jumps in delay slots cannot be converted to
* branches, as they have a different behaviour
* there. */
continue;
}
/* Transform J opcode into BEQ $zero, $zero if possible. */
offset = (s32)((block->pc & 0xf0000000) >> 2 | op->j.imm)
- (s32)(block->pc >> 2) - (s32)i - 1;
if (offset == (s16)offset) {
pr_debug("Transform J into BEQ $zero, $zero\n");
op->i.op = OP_BEQ;
op->i.rs = 0;
op->i.rt = 0;
op->i.imm = offset;
}
fallthrough;
default:
break;
}
}
return 0;
}
static inline bool is_power_of_two(u32 value)
{
return popcount32(value) == 1;
}
static void lightrec_patch_known_zero(struct opcode *op,
const struct constprop_data *v)
{
switch (op->i.op) {
case OP_SPECIAL:
switch (op->r.op) {
case OP_SPECIAL_JR:
case OP_SPECIAL_JALR:
case OP_SPECIAL_MTHI:
case OP_SPECIAL_MTLO:
if (is_known_zero(v, op->r.rs))
op->r.rs = 0;
break;
default:
if (is_known_zero(v, op->r.rs))
op->r.rs = 0;
fallthrough;
case OP_SPECIAL_SLL:
case OP_SPECIAL_SRL:
case OP_SPECIAL_SRA:
if (is_known_zero(v, op->r.rt))
op->r.rt = 0;
break;
case OP_SPECIAL_SYSCALL:
case OP_SPECIAL_BREAK:
case OP_SPECIAL_MFHI:
case OP_SPECIAL_MFLO:
break;
}
break;
case OP_CP0:
switch (op->r.rs) {
case OP_CP0_MTC0:
case OP_CP0_CTC0:
if (is_known_zero(v, op->r.rt))
op->r.rt = 0;
break;
default:
break;
}
break;
case OP_CP2:
if (op->r.op == OP_CP2_BASIC) {
switch (op->r.rs) {
case OP_CP2_BASIC_MTC2:
case OP_CP2_BASIC_CTC2:
if (is_known_zero(v, op->r.rt))
op->r.rt = 0;
break;
default:
break;
}
}
break;
case OP_BEQ:
case OP_BNE:
if (is_known_zero(v, op->i.rt))
op->i.rt = 0;
fallthrough;
case OP_REGIMM:
case OP_BLEZ:
case OP_BGTZ:
case OP_ADDI:
case OP_ADDIU:
case OP_SLTI:
case OP_SLTIU:
case OP_ANDI:
case OP_ORI:
case OP_XORI:
case OP_META_MULT2:
case OP_META_MULTU2:
case OP_META:
if (is_known_zero(v, op->m.rs))
op->m.rs = 0;
break;
case OP_SB:
case OP_SH:
case OP_SWL:
case OP_SW:
case OP_SWR:
case OP_META_SWU:
if (is_known_zero(v, op->i.rt))
op->i.rt = 0;
fallthrough;
case OP_LB:
case OP_LH:
case OP_LWL:
case OP_LW:
case OP_LBU:
case OP_LHU:
case OP_LWR:
case OP_LWC2:
case OP_SWC2:
case OP_META_LWU:
if (is_known(v, op->i.rs)
&& kunseg(v[op->i.rs].value) == 0)
op->i.rs = 0;
break;
default:
break;
}
}
static void lightrec_reset_syncs(struct block *block)
{
struct opcode *op, *list = block->opcode_list;
unsigned int i;
s32 offset;
for (i = 0; i < block->nb_ops; i++)
list[i].flags &= ~LIGHTREC_SYNC;
for (i = 0; i < block->nb_ops; i++) {
op = &list[i];
if (has_delay_slot(op->c)) {
if (op_flag_local_branch(op->flags)) {
offset = i + 1 - op_flag_no_ds(op->flags) + (s16)op->i.imm;
list[offset].flags |= LIGHTREC_SYNC;
}
if (op_flag_emulate_branch(op->flags) && i + 2 < block->nb_ops)
list[i + 2].flags |= LIGHTREC_SYNC;
}
}
}
static void maybe_remove_load_delay(struct opcode *op)
{
if (op_flag_load_delay(op->flags) && opcode_is_load(op->c))
op->flags &= ~LIGHTREC_LOAD_DELAY;
}
static int lightrec_transform_ops(struct lightrec_state *state, struct block *block)
{
struct opcode *op, *list = block->opcode_list;
struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
unsigned int i;
bool local;
int idx;
u8 tmp;
for (i = 0; i < block->nb_ops; i++) {
op = &list[i];
lightrec_consts_propagate(block, i, v);
lightrec_patch_known_zero(op, v);
/* Transform all opcodes detected as useless to real NOPs
* (0x0: SLL r0, r0, #0) */
if (op->opcode != 0 && is_nop(op->c)) {
pr_debug("Converting useless opcode "X32_FMT" to NOP\n",
op->opcode);
op->opcode = 0x0;
}
if (!op->opcode)
continue;
switch (op->i.op) {
case OP_BEQ:
if (op->i.rs == op->i.rt ||
(is_known(v, op->i.rs) && is_known(v, op->i.rt) &&
v[op->i.rs].value == v[op->i.rt].value)) {
if (op->i.rs != op->i.rt)
pr_debug("Found always-taken BEQ\n");
op->i.rs = 0;
op->i.rt = 0;
} else if (v[op->i.rs].known & v[op->i.rt].known &
(v[op->i.rs].value ^ v[op->i.rt].value)) {
pr_debug("Found never-taken BEQ\n");
if (!op_flag_no_ds(op->flags))
maybe_remove_load_delay(&list[i + 1]);
local = op_flag_local_branch(op->flags);
op->opcode = 0;
op->flags = 0;
if (local)
lightrec_reset_syncs(block);
} else if (op->i.rs == 0) {
op->i.rs = op->i.rt;
op->i.rt = 0;
}
break;
case OP_BNE:
if (v[op->i.rs].known & v[op->i.rt].known &
(v[op->i.rs].value ^ v[op->i.rt].value)) {
pr_debug("Found always-taken BNE\n");
op->i.op = OP_BEQ;
op->i.rs = 0;
op->i.rt = 0;
} else if (is_known(v, op->i.rs) && is_known(v, op->i.rt) &&
v[op->i.rs].value == v[op->i.rt].value) {
pr_debug("Found never-taken BNE\n");
if (!op_flag_no_ds(op->flags))
maybe_remove_load_delay(&list[i + 1]);
local = op_flag_local_branch(op->flags);
op->opcode = 0;
op->flags = 0;
if (local)
lightrec_reset_syncs(block);
} else if (op->i.rs == 0) {
op->i.rs = op->i.rt;
op->i.rt = 0;
}
break;
case OP_BLEZ:
if (v[op->i.rs].known & BIT(31) &&
v[op->i.rs].value & BIT(31)) {
pr_debug("Found always-taken BLEZ\n");
op->i.op = OP_BEQ;
op->i.rs = 0;
op->i.rt = 0;
}
break;
case OP_BGTZ:
if (v[op->i.rs].known & BIT(31) &&
v[op->i.rs].value & BIT(31)) {
pr_debug("Found never-taken BGTZ\n");
if (!op_flag_no_ds(op->flags))