Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Implement a modified Harvard architecture, with separate instruction and data caches but single memory. #15

Open
rjlv2 opened this issue Nov 15, 2018 · 1 comment
Open

Implement a modified Harvard architecture, with separate instruction and data caches but single memory. #15

rjlv2 opened this issue Nov 15, 2018 · 1 comment

Comments

@rjlv2
Copy link
Contributor

rjlv2 commented Nov 15, 2018

No description provided.

@phillipstanleymarbell phillipstanleymarbell transferred this issue from another repository May 5, 2019
@rjlv2 rjlv2 changed the title Implement a modified Harvard architecture, treating the separate instruction and data memory as cache Implement a modified Harvard architecture, with separate instruction and data caches but single memory. May 5, 2019
@rjlv2
Copy link
Contributor Author

rjlv2 commented May 5, 2019

Simulation was working in e9f6f8f. But could not get it run on the FPGA.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@rjlv2