Does PLCT-GEM5 support saving checkpoint of vector registers?

[LandonWong]

Does plct-gem5 support saving and restoring vector registers in checkpoint? If supported, in which file are the changes made?

Thanks,

[huxuan0307]

I'm sorry that I have no idea about how to use checkpoints in gem5 right now. Maybe you can try to save and restore risc-v checkpoint on non-vector workloads. And then, use the same way to save and restore checkpoint on vector workloads. I will figure out checkpoints in a few weeks.

[LandonWong]

Thanks. In gem5 SE mode, we can save and restore the current state of CPU and memory to *.cpt (CPU state) and *.pmem (Memory contents). Where *.cpt contains values of general purpose registers, float registers and vector registers (none now).
I think it may need some efforts to support saving and restoring vector registers: porting that logic to the PLCT rvv CPU model (x86 and arm already realized vector checkpoint).
I would appreciate it if you could share with me if there are plans to support it, many thanks!