From 4a9e982caaa9fec6f3c2b9ecc5633895ab090169 Mon Sep 17 00:00:00 2001 From: Frank Laub Date: Sun, 29 Dec 2024 02:08:37 -0800 Subject: [PATCH] Fixes for CI --- zirgen/circuit/rv32im/v2/dsl/pack.zir | 2 +- zirgen/circuit/rv32im/v2/emu/preflight.cpp | 2 +- zirgen/circuit/rv32im/v2/emu/sha.h | 2 + zirgen/circuit/rv32im/v2/test/BUILD.bazel | 52 +++++---------- zirgen/circuit/rv32im/v2/test/defs.bzl | 63 +++++++++++++++++++ .../circuit/rv32im/v2/test/risc0-simulate.cpp | 47 ++++++++++++++ zirgen/circuit/rv32im/v2/test/run_test.py | 26 ++++++++ .../rv32im/v2/test/test_riscv_bins.cpp | 51 --------------- 8 files changed, 157 insertions(+), 88 deletions(-) create mode 100644 zirgen/circuit/rv32im/v2/test/defs.bzl create mode 100644 zirgen/circuit/rv32im/v2/test/risc0-simulate.cpp create mode 100644 zirgen/circuit/rv32im/v2/test/run_test.py delete mode 100644 zirgen/circuit/rv32im/v2/test/test_riscv_bins.cpp diff --git a/zirgen/circuit/rv32im/v2/dsl/pack.zir b/zirgen/circuit/rv32im/v2/dsl/pack.zir index 82d03daf..3165419c 100644 --- a/zirgen/circuit/rv32im/v2/dsl/pack.zir +++ b/zirgen/circuit/rv32im/v2/dsl/pack.zir @@ -3,7 +3,7 @@ import bits; import arr; -import po2; +import u32; // We have 3 functions here: // 1) Pack an array of N bits into N/P elements diff --git a/zirgen/circuit/rv32im/v2/emu/preflight.cpp b/zirgen/circuit/rv32im/v2/emu/preflight.cpp index d3dfe41c..e2d30b47 100644 --- a/zirgen/circuit/rv32im/v2/emu/preflight.cpp +++ b/zirgen/circuit/rv32im/v2/emu/preflight.cpp @@ -327,7 +327,7 @@ PreflightTrace preflightSegment(const Segment& in, size_t segmentSize) { // Now, go back and update memory transactions to wrap around for (auto& txn : ret.txns) { - if (txn.prevCycle == -1) { + if (static_cast(txn.prevCycle) == -1) { // If first cycle for word, set to 'prevCycle' to final cycle txn.prevCycle = preflightContext.prevCycle[txn.word]; } else { diff --git a/zirgen/circuit/rv32im/v2/emu/sha.h b/zirgen/circuit/rv32im/v2/emu/sha.h index 024eaa3d..7b8a62ee 100644 --- a/zirgen/circuit/rv32im/v2/emu/sha.h +++ b/zirgen/circuit/rv32im/v2/emu/sha.h @@ -14,6 +14,8 @@ #pragma once +#include + namespace zirgen::rv32im_v2 { // 1 to 1 state from inst_sha diff --git a/zirgen/circuit/rv32im/v2/test/BUILD.bazel b/zirgen/circuit/rv32im/v2/test/BUILD.bazel index b051bb9a..259f238d 100644 --- a/zirgen/circuit/rv32im/v2/test/BUILD.bazel +++ b/zirgen/circuit/rv32im/v2/test/BUILD.bazel @@ -1,18 +1,14 @@ load("@zirgen//bazel/toolchain/rv32im-linux:defs.bzl", "risc0_cc_kernel_binary") +load(":defs.bzl", "riscv_test_suite") cc_test( name = "test_parallel", - srcs = [ - "test_parallel.cpp", - ], + srcs = ["test_parallel.cpp"], data = [ "//zirgen/circuit/rv32im/v2/emu/test:guest", "//zirgen/circuit/rv32im/v2/kernel", - "@zirgen//zirgen/circuit/rv32im/shared/test:riscv_test_bins", - ], - deps = [ - "//zirgen/circuit/rv32im/v2/run", ], + deps = ["//zirgen/circuit/rv32im/v2/run"], ) risc0_cc_kernel_binary( @@ -26,28 +22,9 @@ risc0_cc_kernel_binary( cc_test( name = "test_p2", - srcs = [ - "test_p2.cpp", - ], - data = [ - ":test_p2_kernel", - ], - deps = [ - "//zirgen/circuit/rv32im/v2/run", - ], -) - -cc_test( - name = "test_riscv_bins", - srcs = [ - "test_riscv_bins.cpp", - ], - data = [ - "//zirgen/circuit/rv32im/shared/test:riscv_test_bins", - ], - deps = [ - "//zirgen/circuit/rv32im/v2/run", - ], + srcs = ["test_p2.cpp"], + data = [":test_p2_kernel"], + deps = ["//zirgen/circuit/rv32im/v2/run"], ) risc0_cc_kernel_binary( @@ -61,13 +38,18 @@ risc0_cc_kernel_binary( cc_test( name = "test_sha", - srcs = [ - "test_sha.cpp", - ], - data = [ - ":test_sha_kernel", - ], + srcs = ["test_sha.cpp"], + data = [":test_sha_kernel"], + deps = ["//zirgen/circuit/rv32im/v2/run"], +) + +cc_binary( + name = "risc0-simulate", + srcs = ["risc0-simulate.cpp"], deps = [ + "//risc0/core", "//zirgen/circuit/rv32im/v2/run", ], ) + +riscv_test_suite() diff --git a/zirgen/circuit/rv32im/v2/test/defs.bzl b/zirgen/circuit/rv32im/v2/test/defs.bzl new file mode 100644 index 00000000..7164ebe9 --- /dev/null +++ b/zirgen/circuit/rv32im/v2/test/defs.bzl @@ -0,0 +1,63 @@ +INST_TESTS = [ + "add", + "addi", + "and", + "andi", + "auipc", + "beq", + "bge", + "bgeu", + "blt", + "bltu", + "bne", + "jal", + "jalr", + "lb", + "lbu", + "lh", + "lhu", + "lui", + "lw", + "or", + "ori", + "sb", + "sh", + "simple", + "sll", + "slli", + "slt", + "slti", + "sltiu", + "sltu", + "sra", + "srai", + "srl", + "srli", + "sub", + "sw", + "xor", + "xori", + "div", + "divu", + "mul", + "mulh", + "mulhsu", + "mulhu", + "rem", + "remu", +] + +def riscv_test_suite(): + for test in INST_TESTS: + native.py_test( + # tags = ["manual"], + name = test + "_test", + srcs = ["run_test.py"], + main = "run_test.py", + args = [test], + data = [ + "//zirgen/circuit/rv32im/shared/test:riscv_test_bins", + ":risc0-simulate", + ], + size = "large", + ) diff --git a/zirgen/circuit/rv32im/v2/test/risc0-simulate.cpp b/zirgen/circuit/rv32im/v2/test/risc0-simulate.cpp new file mode 100644 index 00000000..6992aae3 --- /dev/null +++ b/zirgen/circuit/rv32im/v2/test/risc0-simulate.cpp @@ -0,0 +1,47 @@ +// Copyright 2024 RISC Zero, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "risc0/core/log.h" +#include "zirgen/circuit/rv32im/v2/platform/constants.h" +#include "zirgen/circuit/rv32im/v2/run/run.h" + +using namespace zirgen::rv32im_v2; + +int main(int argc, char* argv[]) { + risc0::setLogLevel(2); + if (argc < 2) { + LOG(1, "usage: risc0-simulate "); + exit(1); + } + + LOG(1, "File = " << argv[1]); + try { + size_t cycles = 10000; + + TestIoHandler io; + + // Load image + auto image = MemoryImage::fromRawElf(argv[1]); + // Do executions + auto segments = execute(image, io, cycles, cycles); + // Do 'run' (preflight + expansion) + for (const auto& segment : segments) { + runSegment(segment, cycles); + } + } catch (const std::runtime_error& err) { + LOG(1, "Failed: " << err.what()); + exit(1); + } + return 0; +} diff --git a/zirgen/circuit/rv32im/v2/test/run_test.py b/zirgen/circuit/rv32im/v2/test/run_test.py new file mode 100644 index 00000000..aa23af2c --- /dev/null +++ b/zirgen/circuit/rv32im/v2/test/run_test.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python +# Copyright 2022 RISC Zero, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import subprocess +import sys + +sys.exit( + subprocess.run( + [ + "zirgen/circuit/rv32im/v2/test/risc0-simulate", + "zirgen/circuit/rv32im/shared/test/" + sys.argv[1], + ] + ).returncode +) diff --git a/zirgen/circuit/rv32im/v2/test/test_riscv_bins.cpp b/zirgen/circuit/rv32im/v2/test/test_riscv_bins.cpp deleted file mode 100644 index e441e38b..00000000 --- a/zirgen/circuit/rv32im/v2/test/test_riscv_bins.cpp +++ /dev/null @@ -1,51 +0,0 @@ -// Copyright 2024 RISC Zero, Inc. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include - -#include "zirgen/circuit/rv32im/v2/platform/constants.h" -#include "zirgen/circuit/rv32im/v2/run/run.h" - -using namespace zirgen::rv32im_v2; - -void runOneTest(const std::string& name) { - std::string kernel = "zirgen/circuit/rv32im/shared/test/" + name; - size_t cycles = 10000; - - TestIoHandler io; - - // Load image - auto image = MemoryImage::fromRawElf(kernel); - // Do executions - auto segments = execute(image, io, cycles, cycles); - // Do 'run' (preflight + expansion) - for (const auto& segment : segments) { - runSegment(segment, cycles); - } -} - -std::vector names = { - "add", "addi", "and", "andi", "auipc", "beq", "bge", "bgeu", "blt", "bltu", - "bne", "div", "divu", "jal", "jalr", "lb", "lbu", "lh", "lhu", "lui", - "lw", "mul", "mulh", "mulhsu", "mulhu", "or", "ori", "rem", "remu", "sb", - "sh", "sll", "slli", "slt", "slti", "sltiu", "sltu", "sra", "srai", "srl", - "srli", "sub", "sw", "test", "xor", "xori"}; - -const std::string kernelName = "zirgen/circuit/rv32im/shared/test/rem"; - -int main() { - for (const std::string& name : names) { - runOneTest(name); - } -}