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+# Meeting Agenda 2025-01-31: CX TG ad hoc meeting: Extension Logic Interface Workshop
+
+When/where: 2025-01-31 7a-10a PT, Zoom
+
+This is an ad hoc 2-3 hour TG meeting "workshop" to survey various
+RISC-V extension/coprocessor logic interfaces and their user communities.
+
+## Purpose
+
+The TG will create ISA and non-ISA specifications that enable practical
+reuse, within a system, of multiple composable custom extensions (CXs),
+CX libraries, and modular CX unit (CXU) hardware. The TG deliverables
+include an optional logic interface spec. Previously (2019-2024) Soft
+CPU SIG [4] designed such an interface [5], CXU-LI. Now the CX TG will
+draft a new extension logic interface spec, informed by this, and by
+other RISC-V extension logic interfaces, to be discussed in this workshop.
+
+The meeting will consist of a series of ~25 min talks (incl. Q&A). Each
+talk will showcase one extension logic interface: its purpose,
+highlights, signaling (channels, port maps), state model, kinds of
+custom instructions supported, what architectural state (e.g., vector
+registers) is accessible to extensions, any pipeline issues, and also,
+the logic interface’s current ecosystem, user community, CPU cores
+that support it, and exemplary uses in industry.
+
+## Meeting agenda (details TBD)
+
+- Extension logic interface presentations: ROCC, CV-X-IF, SCAIE-V, CXU-LI (2 hours)
+- Discussion (0-1 hours)