From 871d9453eb4440c1cd39941a67bbf4160f7b23e7 Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 27 Sep 2024 08:31:20 +0800 Subject: [PATCH 1/2] refactor: Move halt out of dcsr Suggested in https://github.com/riscv-software-src/riscv-isa-sim/pull/1816#pullrequestreview-2331806142. --- riscv/csrs.cc | 1 - riscv/csrs.h | 1 - riscv/execute.cc | 4 ++-- riscv/processor.cc | 2 +- riscv/processor.h | 1 + 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 7ea1e4fa11..f2511e7cd8 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1345,7 +1345,6 @@ dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr): ebreaku(false), ebreakvs(false), ebreakvu(false), - halt(false), v(false), cause(0), ext_cause(0), diff --git a/riscv/csrs.h b/riscv/csrs.h index 4055d86272..278bdb3713 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -696,7 +696,6 @@ class dcsr_csr_t: public csr_t { bool ebreaku; bool ebreakvs; bool ebreakvu; - bool halt; bool v; uint8_t cause; uint8_t ext_cause; diff --git a/riscv/execute.cc b/riscv/execute.cc index 5b8e52382c..c117230d72 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -216,8 +216,8 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_DEBUGINT, 0); } else if (halt_request == HR_GROUP) { enter_debug_mode(DCSR_CAUSE_GROUP, 0); - } else if (state.dcsr->halt) { - state.dcsr->halt = false; + } else if (halt) { + halt = false; enter_debug_mode(DCSR_CAUSE_HALT, 0); } } diff --git a/riscv/processor.cc b/riscv/processor.cc index c4d8c0694c..3b9161296e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -186,7 +186,7 @@ void processor_t::reset() { xlen = isa.get_max_xlen(); state.reset(this, isa.get_max_isa()); - state.dcsr->halt = halt_on_reset; + halt = halt_on_reset; halt_on_reset = false; if (any_vector_extensions()) VU.reset(); diff --git a/riscv/processor.h b/riscv/processor.h index 4f22cbdee5..2a9d4f4e7e 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -384,6 +384,7 @@ class processor_t : public abstract_device_t FILE *log_file; std::ostream sout_; // needed for socket command interface -s, also used for -d and -l, but not for --log bool halt_on_reset; + bool halt; bool in_wfi; bool check_triggers_icount; std::vector impl_table; From 5c814c71340118f1d6259acf4a876abfe7344d9c Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 27 Sep 2024 08:38:45 +0800 Subject: [PATCH 2/2] refactor: Merge halt and halt_on_reset variables in processor_t --- riscv/execute.cc | 4 ++-- riscv/processor.cc | 2 -- riscv/processor.h | 1 - 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/riscv/execute.cc b/riscv/execute.cc index c117230d72..1fa6111f7a 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -216,8 +216,8 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_DEBUGINT, 0); } else if (halt_request == HR_GROUP) { enter_debug_mode(DCSR_CAUSE_GROUP, 0); - } else if (halt) { - halt = false; + } else if (halt_on_reset) { + halt_on_reset = false; enter_debug_mode(DCSR_CAUSE_HALT, 0); } } diff --git a/riscv/processor.cc b/riscv/processor.cc index 3b9161296e..9260045bd3 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -186,8 +186,6 @@ void processor_t::reset() { xlen = isa.get_max_xlen(); state.reset(this, isa.get_max_isa()); - halt = halt_on_reset; - halt_on_reset = false; if (any_vector_extensions()) VU.reset(); in_wfi = false; diff --git a/riscv/processor.h b/riscv/processor.h index 2a9d4f4e7e..4f22cbdee5 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -384,7 +384,6 @@ class processor_t : public abstract_device_t FILE *log_file; std::ostream sout_; // needed for socket command interface -s, also used for -d and -l, but not for --log bool halt_on_reset; - bool halt; bool in_wfi; bool check_triggers_icount; std::vector impl_table;