From 3f0a9e14c544b173ad3c8d0ce811c800bc85bc88 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 14 Sep 2023 08:57:06 -0700 Subject: [PATCH 01/30] AR: Remove comment about privspec/CSR behavior From Greg: "... why is this non-normative comment even necessary? It's directly consistent with 1.12, and it's compatible with 1.13 which allows for trapping and just doesn't require it. In other words, wrt 1.13, this trapping mandate by Debug 1.0 doesn't conflict with Priv 1.13. And that allows Debug 1.0 to come along and tighten what is allowed by 1.13." --- Sdtrig.tex | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Sdtrig.tex b/Sdtrig.tex index 3a08b357..a0306ec8 100644 --- a/Sdtrig.tex +++ b/Sdtrig.tex @@ -358,12 +358,4 @@ \section{Trigger Registers} Attempts to access an unimplemented Trigger Register raise an illegal instruction exception. -\begin{commentary} - Privileged spec v1.12 requires accesses to unimplemented CSRs to raise - illegal instruction exceptions, but that may change in the future. Even if - it does change, the behavior here overrides it for Sdtrig CSRs for backwards - compatibility. This is even true if Sdtrig is not implemented at all, so the - discovery algorithm in Section~\ref{sec:trigger} still works. -\end{commentary} - \input{hwbp_registers.tex} From 2ace90c1601953bfa52778e6b18ef295f9903870 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 14 Sep 2023 09:15:01 -0700 Subject: [PATCH 02/30] AR: Clarify what debuggers can assume about MRs --- debug_module.tex | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/debug_module.tex b/debug_module.tex index ea9f1b39..f870005f 100644 --- a/debug_module.tex +++ b/debug_module.tex @@ -321,7 +321,9 @@ \section{Message Registers} Only registers whose description explicitly says they may be MRs may be implemented as MRs instead of traditional registers. \RdmDataZero through \RdmDataEleven may be MRs, used to let the debugger pass arguments to abstract -commands, and let the DM pass results from abstract commands back. +commands, and let the DM pass results from abstract commands back. Debuggers +must not assume that they'll be able to read back a value that they wrote to a +register that may be an MR. A traditional dual-ported register contains a single value, which can be read/written through both ports. A MR has two ports: PortA and PortB. It From 2cd44e588b7fb42212f6ab13e2898bb1395f7b26 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Sat, 16 Sep 2023 12:36:18 +0300 Subject: [PATCH 03/30] Address review comments on `debug_defines.h` --- README.md | 2 +- debug_register_printers.c => debug_reg_printer.c | 8 ++++---- debug_register_printers.h => debug_reg_printer.h | 0 registers.py | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) rename debug_register_printers.c => debug_reg_printer.c (92%) rename debug_register_printers.h => debug_reg_printer.h (100%) diff --git a/README.md b/README.md index a85697a5..e8081ac3 100755 --- a/README.md +++ b/README.md @@ -20,7 +20,7 @@ There are two other interesting make targets: 1. `make debug_defines` creates a C header and implementation files containing constants for addresses and fields of all the registers and abstract commands, as well as function and structures used to decode register values. - An implementation of such decoder can be seen in `debug_register_printers.c/h`. + An implementation of such decoder can be seen in `debug_reg_printer.c/h`. 2. `make chisel` creates scala files for DM registers and abstract commands with the same information. diff --git a/debug_register_printers.c b/debug_reg_printer.c similarity index 92% rename from debug_register_printers.c rename to debug_reg_printer.c index 7ba56b6c..677cca7d 100644 --- a/debug_register_printers.c +++ b/debug_reg_printer.c @@ -5,7 +5,7 @@ #include #include -#include "debug_register_printers.h" +#include "debug_reg_printer.h" static unsigned int get_len_or_sprintf(char *buf, unsigned int curr, const char *format, ...) { @@ -23,7 +23,7 @@ static unsigned int get_len_or_sprintf(char *buf, unsigned int curr, const char return (unsigned int)length; } -static unsigned int print_value(char *buf, unsigned int offset, uint64_t value) +static unsigned int print_number(char *buf, unsigned int offset, uint64_t value) { const char * const format = value > 9 ? "0x%" PRIx64 : "%" PRIx64; @@ -38,7 +38,7 @@ static unsigned int riscv_debug_reg_field_value_to_s(char *buf, unsigned int off NULL; if (!field_value_name) - return print_value(buf, offset, field_value); + return print_number(buf, offset, field_value); return get_len_or_sprintf(buf, offset, "%s", field_value_name); } @@ -82,7 +82,7 @@ unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_or riscv_debug_reg_info_t reg = get_riscv_debug_reg_info(reg_ordinal); length += get_len_or_sprintf(buf, length, "%s=", reg.name); - length += print_value(buf, length, value); + length += print_number(buf, length, value); if (reg.get_fields_head) length += riscv_debug_reg_fields_to_s(buf, length, reg.get_fields_head(context), diff --git a/debug_register_printers.h b/debug_reg_printer.h similarity index 100% rename from debug_register_printers.h rename to debug_reg_printer.h diff --git a/registers.py b/registers.py index 6c23baf5..95d8ac7c 100755 --- a/registers.py +++ b/registers.py @@ -118,7 +118,7 @@ def getter(f, getter_name, next_getter_name): syms = f.symbols() all_valid = ' && '.join(map(is_valid, syms)) field = f.c_info(to_c).replace('\n', '\n\t\t') - return (f"riscv_debug_reg_field_list_t {getter_name}(riscv_debug_reg_ctx_t context)\n" + + return (f"static riscv_debug_reg_field_list_t {getter_name}(riscv_debug_reg_ctx_t context)\n" + "{\n\t" + add_indent((f"assert({all_valid});\n" if syms else "") + f"riscv_debug_reg_field_list_t result = {{\n" + From b4a51a37559eb2c93af595041305a9202387f623 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 18 Sep 2023 12:04:42 -0700 Subject: [PATCH 04/30] AR: Clarify unimplemented Sdtrig. If Sdext is implemented and Sdtrig is not implemented, then accessing any of the Sdtrig CSRs must raise an illegal instruction exception. (This is already said in privspec 1.12, but that might change in the future.) --- Sdext.tex | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Sdext.tex b/Sdext.tex index c622ec59..c843b8e9 100644 --- a/Sdext.tex +++ b/Sdext.tex @@ -12,6 +12,9 @@ \chapter{Sdext (ISA Extension)} implement everything described in this section that is not explicitly listed as optional. +If Sdext is implemented and Sdtrig is not implemented, then accessing any of the +Sdtrig CSRs must raise an illegal instruction exception. + \section{Debug Mode} \label{debugmode} Debug Mode is a special processor mode used only when a hart is halted for From 51fc0955d4893142cba6e3e183c0207fa230146f Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 19 Sep 2023 16:44:40 -0700 Subject: [PATCH 05/30] AR: tcontrol.mie applies to all traps, not just breakpoints Reverts #723, which would result in mepc etc. being clobbered if a breakpoint trigger would fire in the most privileged mode. Specifically, consider: 1. icount is set so that it'll trigger on the first instruction of an exception handler. 2. Code takes an exception, saving mepc etc. 3. Now icount fires causing a breakpoint exception, clobbering mepc. --- introduction.tex | 2 ++ xml/hwbp_registers.xml | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/introduction.tex b/introduction.tex index 21dcbe93..b6ca85c4 100644 --- a/introduction.tex +++ b/introduction.tex @@ -222,6 +222,8 @@ \subsubsection{Incompatible Changes During 1.0 Stable} command is available as argument to the next abstract command. \PR{728} \item It may not be possible to read the contents of the Program Buffer using the {\tt progbuf} registers. \PR{731} +\item \RcsrTcontrol fields apply to all traps, not just breakpoint traps. This + reverts \PR{723}. \PR{880} \end{steps} \section{About This Document} diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index bf1e28d9..8a5a7fa4 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -196,7 +196,7 @@ regarding triggers with action=0 firing in M-mode trap handlers. See Section~\ref{sec:nativetrigger} for more details. - When a breakpoint trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of + When any trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of \FcsrTcontrolMte. @@ -211,7 +211,7 @@ Triggers do match/fire while the hart is in M-mode. - When a breakpoint trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt + When any trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte. From 0563d2f8642e01ac96c490f08f1d6f6946a3e549 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 20 Sep 2023 16:46:18 -0700 Subject: [PATCH 06/30] AR: Clarify mcontext/hcontext. It was a bit confusing before. Hopefully now it's more clear how they relate, and why you might want each one. --- xml/hwbp_registers.xml | 51 ++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index bf1e28d9..6f6ed69c 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -218,28 +218,15 @@ - This optional register is only accessible in S/HS-mode, M-mode and - Debug Mode. + This optional register may be implemented only if the H extension is + implemented. If it is implemented, \RcsrMcontext must also be implemented. - Accessibility of this CSR is controlled by \Rmstateenzero[57] - in the Smstateen extension. + This register is only accessible in HS-Mode, M-mode and Debug Mode. If + Smstateen is implemented, then accessibility of in HS-Mode is + controlled by \Rmstateenzero[57]. - If the H extension is not implemented then this register is not - implemented, though the underlying state may be accessible via - the optional \RcsrMcontext alias. - - - Hypervisor mode software can write a context number to this register, - which can be used to set triggers that only fire in that specific - context. - - An implementation may tie any number of upper bits in this field to - 0. If the H extension is not implemented, it's recommended to implement - no more than 6 bits on RV32 and 13 on RV64 (as visible through the - \RcsrMcontext register). If the H extension is implemented, - it's recommended to implement no more than 7 bits on RV32 - and 14 on RV64. - + This register is an alias of the \RcsrMcontext register, providing + access to the \FcsrMcontextHcontext field from HS-Mode. @@ -262,8 +249,28 @@ - This optional register is an alias for \RcsrHcontext and is only - accessible in M-mode and Debug mode. + This register must be implemented if \RcsrHcontext is implemented, and + is optional otherwise. It is only accessible in M-mode and Debug mode. + + \begin{commentary} + \FcsrMcontextHcontext is primarily useful to set triggers on + hypervisor systems that only fire when a given VM is executing. It + is also useful in systems where M-Mode implements something like a + hypervisor directly. + \end{commentary} + + + M-Mode or HS-Mode (using \RcsrHcontext) software can write a context + number to this register, which can be used to set triggers that only + fire in that specific context. + + An implementation may tie any number of upper bits in this field to + 0. If the H extension is not implemented, it's recommended to implement + no more than 6 bits on RV32 and 13 on RV64 (as visible through the + \RcsrMcontext register). If the H extension is implemented, + it's recommended to implement no more than 7 bits on RV32 + and 14 on RV64. + From 3ef1852c8171bbfdc73bbe7d7e52e676ae445842 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 20 Sep 2023 12:57:34 -0700 Subject: [PATCH 07/30] AR: List which extensions were considered. I added a hint as to how they were considered as LaTeX comments, because I want to keep that info but don't want to word it nicely/completely enough to actually have it as part of the spec text. --- introduction.tex | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/introduction.tex b/introduction.tex index 21dcbe93..4c7ffa78 100644 --- a/introduction.tex +++ b/introduction.tex @@ -98,8 +98,25 @@ \section{Terminology} \section{Context} -This document is written to work with all RISC-V ISA extensions ratified -through 2021. +\begin{steps}{This specification attempts to support all RISC-V ISA extensions +that have, roughly, been ratified through the first half of 2023. In +particular, though, this specification specifically addresses features in the +following extensions:} +\item A % Mention atomics in debug mode section +\item C % Mentioned in single-word progbuf context +\item D % Access register abstract register numbers. +\item F % Access register abstract register numbers. +\item H % Various trigger bits +\item Sm1p13 % E.g. exceptions +\item Ss1p13 % Mention S-Mode in various trigger stuff +\item Smstateen % Mentioned in hcontext register description. +\item V % Mentioned in debug mode entry section +\item Zawrs % we refer to wrs.sto and wrs.nto +\item Zcmp % Mention cm.push, cm.pop in Sdtrig +\item Zicbom % Mention cbo.clean, cbo.flush, and cbo.inval in Cache Operations +\item Zicboz % Mention cbo.zero in Cache Operations +\item Zicbop % Mention prefetch instructions in Cache Operations +\end{steps} \subsection{Versions} From 182beaacd506675051f51f9bc85110dd1181f2eb Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 26 Sep 2023 11:34:49 -0700 Subject: [PATCH 08/30] dscratch[01] are DXLEN bits wide. See https://lists.riscv.org/g/tech-debug/message/1387 --- xml/core_registers.xml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xml/core_registers.xml b/xml/core_registers.xml index 0f1f6a93..93728987 100755 --- a/xml/core_registers.xml +++ b/xml/core_registers.xml @@ -328,11 +328,13 @@ Optional scratch register that can be used by implementations that need it. A debugger must not write to this register unless \RdmHartinfo explicitly mentions it (the Debug Module may use this register internally). + Optional scratch register that can be used by implementations that need it. A debugger must not write to this register unless \RdmHartinfo explicitly mentions it (the Debug Module may use this register internally). + From 276b60abb763f6298d7fe57276f405f242157c63 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 26 Sep 2023 11:45:26 -0700 Subject: [PATCH 09/30] Fix debugger examples: use transfer with write Addresses #857. --- debugger_implementation.tex | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/debugger_implementation.tex b/debugger_implementation.tex index 6f0a9fb1..250aede0 100644 --- a/debugger_implementation.tex +++ b/debugger_implementation.tex @@ -210,7 +210,7 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf} \hline Write & \RdmDataZero & address & \\ \hline - Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\ + Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\ \hline Write & \RdmCommand & \FacAccessregisterRegno = 0x1008 & Read \Szero \\ \hline @@ -233,7 +233,7 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf} \hline Write & \RdmDataZero & address & \\ \hline - Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\ + Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1008 & Write \Szero, then execute program buffer \\ \hline Write & \RdmCommand & \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Read \Sone, then execute program buffer \\ \hline @@ -355,11 +355,11 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf} \hline Write & \RdmDataZero & address & \\ \hline - Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\ + Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\ \hline Write & \RdmDataZero & value & \\ \hline - Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\ + Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\ \hline \end{tabular} \medskip @@ -378,11 +378,11 @@ \subsubsection{Using Program Buffer} \label{deb:mrprogbuf} \hline Write & \RdmDataZero & address & \\ \hline - Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\ + Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterRegno = 0x1008 & Write \Szero \\ \hline Write & \RdmDataZero & value0 & \\ \hline - Write & \RdmCommand & \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\ + Write & \RdmCommand & \FacAccessregisterTransfer, \FacAccessregisterWrite, \FacAccessregisterPostexec, \FacAccessregisterRegno = 0x1009 & Write \Sone, then execute program buffer \\ \hline Write & \RdmAbstractauto & \FdmAbstractautoAutoexecdata[0] & Set \FdmAbstractautoAutoexecdata[0] \\ \hline From 1aab67486ba26bd06f7ecffe392fa021d5458afc Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 18 Sep 2023 09:40:46 -0700 Subject: [PATCH 10/30] AR: Remove Message Registers. These were first introduced in #728. Hopefully I got everything. --- debug_module.tex | 43 ++++----------------------------------- introduction.tex | 7 +------ xml/abstract_commands.xml | 4 ---- xml/dm_registers.xml | 6 +----- 4 files changed, 6 insertions(+), 54 deletions(-) diff --git a/debug_module.tex b/debug_module.tex index f870005f..1eee2ff0 100644 --- a/debug_module.tex +++ b/debug_module.tex @@ -311,41 +311,6 @@ \section{Halt Groups, Resume Groups, and External Triggers} \label{hrgroups} explicitly allowed. In that case it must be possible to discover the groups by using \RdmDmcsTwo even if it's not possible to change the configuration. -\section{Message Registers} -\label{sec:mr} - -Message Registers (MRs) are registers that implement fewer features than a -traditional register. They support just enough features to pass messages back -and forth. - -Only registers whose description explicitly says they may be MRs may be -implemented as MRs instead of traditional registers. \RdmDataZero through -\RdmDataEleven may be MRs, used to let the debugger pass arguments to abstract -commands, and let the DM pass results from abstract commands back. Debuggers -must not assume that they'll be able to read back a value that they wrote to a -register that may be an MR. - -A traditional dual-ported register contains a single value, which can be -read/written through both ports. A MR has two ports: PortA and PortB. It -contains two values: ValueA and ValueB. Only one of these values has defined -contents at any one time. - -\begin{steps}{For an MR:} - \item A write to PortA updates ValueA with the written value, and makes - ValueB \unspecified. - \item A write to PortB updates ValueB with the written value, and makes - ValueA \unspecified. - \item A read from PortA returns ValueB. - \item A read from PortB returns ValueA. -\end{steps} - -\begin{commentary} - A regular register can be used to implement an MR. In some FPGAs it is - cheaper to trade off storage for muxes, and in that case the storage can be - duplicated (one set of bits for sending and one for receiving) to avoid - having to implement muxes to read/write data from/to the correct side. -\end{commentary} - \section{Abstract Commands} \label{abstractcommands} The DM supports a set of abstract commands, most of which @@ -375,12 +340,12 @@ \section{Abstract Commands} \label{abstractcommands} unavailable, or because they encounter an error during execution. If the command takes arguments, the debugger -must write them to the {\tt data} MRs before writing to \RdmCommand. If a +must write them to the {\tt data} registers before writing to \RdmCommand. If a command returns results, the Debug Module must ensure they are placed -in the {\tt data} MRs before \FdmAbstractcsBusy is cleared. -Which {\tt data} MRs are used for the arguments is +in the {\tt data} registers before \FdmAbstractcsBusy is cleared. +Which {\tt data} registers are used for the arguments is described in Table~\ref{tab:datareg}. In all cases the least-significant word -is placed in the lowest-numbered {\tt data} MR. The argument width +is placed in the lowest-numbered {\tt data} register. The argument width depends on the command being executed, and is DXLEN where not explicitly specified. diff --git a/introduction.tex b/introduction.tex index 21dcbe93..68da96eb 100644 --- a/introduction.tex +++ b/introduction.tex @@ -67,8 +67,6 @@ \section{Terminology} \item[Minimal RISC-V Debug Specification] A subset of the full Debug Specification that allows for very small implementations. See Chapter~\ref{chap:dm}. - \item[MR] - Message Register, described in Section~\ref{sec:mr}. \item[NAPOT] Naturally Aligned Power-Of-Two. \item[NMI] @@ -216,10 +214,7 @@ \subsubsection{Incompatible Changes During 1.0 Stable} called 1.0 stable.} \item \FcsrItriggerNmi was moved from \RcsrEtrigger to \RcsrItrigger, and is now subject to the mode bits in that trigger. -\item DM {\tt data} registers are now Message Registers (see -Section~\ref{sec:mr}). Debuggers must not assume they can read back the same -value that they wrote, and must not assume that the result of the last abstract -command is available as argument to the next abstract command. \PR{728} +\item \PR{728} introduced Message Registers, which were later removed in \PR{878}. \item It may not be possible to read the contents of the Program Buffer using the {\tt progbuf} registers. \PR{731} \end{steps} diff --git a/xml/abstract_commands.xml b/xml/abstract_commands.xml index 8a277dbf..402b074e 100644 --- a/xml/abstract_commands.xml +++ b/xml/abstract_commands.xml @@ -258,10 +258,6 @@ {\tt arg1} (which contains the address used) by the number of bytes encoded in \FacAccessmemoryAamsize. - Implementations that allow this bit to be 1 must implement the - relevant {\tt data} registers as traditional registers instead of - MRs. - Supporting this variant is optional, but highly recommended for performance reasons. diff --git a/xml/dm_registers.xml b/xml/dm_registers.xml index 149a644e..2b370b2e 100755 --- a/xml/dm_registers.xml +++ b/xml/dm_registers.xml @@ -394,9 +394,6 @@ If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map dedicated to shadowing the {\tt data} registers. - If this value is non-zero, then the {tt data} registers must be - traditional registers and not MRs. - Since there are at most 12 {\tt data} registers, the value in this register must be 12 or smaller. @@ -640,8 +637,7 @@ - \RdmDataZero through \RdmDataEleven may be Message Registers, whose - behavior is described in Section~\ref{sec:mr}. These registers may + \RdmDataZero through \RdmDataEleven are registers that may be read or changed by abstract commands. \FdmAbstractcsDatacount indicates how many of them are implemented, starting at \RdmDataZero, counting up. Table~\ref{tab:datareg} shows how abstract commands use these From d404fd9438199597195f59961ba2fc180ac741af Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 28 Sep 2023 13:17:49 -0700 Subject: [PATCH 11/30] Don't build serial.tex. It's way outdated, and by removing it here, it doesn't show up in debug_defines.h anymore. --- Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/Makefile b/Makefile index 1f2794b7..461a7ce7 100755 --- a/Makefile +++ b/Makefile @@ -12,7 +12,6 @@ REGISTERS_TEX += dm_registers.tex REGISTERS_TEX += sample_registers.tex REGISTERS_TEX += abstract_commands.tex REGISTERS_TEX += sw_registers.tex -REGISTERS_TEX += serial.tex REGISTERS_CHISEL += dm_registers.scala REGISTERS_CHISEL += abstract_commands.scala From 2e78518ddca02b19567e6bdde765be5e91deb450 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 28 Sep 2023 13:18:15 -0700 Subject: [PATCH 12/30] Tighten up `make clean` Now it doesn't remove debug_reg_printer.h anymore, which is part of the repo so shouldn't be removed. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 461a7ce7..a1530991 100755 --- a/Makefile +++ b/Makefile @@ -91,7 +91,7 @@ chisel: $(REGISTERS_CHISEL) clean: rm -f $(DRAFT).pdf *.aux $(DRAFT).toc $(DRAFT).log $(REGISTERS_TEX) \ - $(REGISTERS_TEX:=.inc) *.o *_no128.S *.h \ + $(REGISTERS_TEX:=.inc) *.o *_no128.S debug_defines.[ch] \ $(DRAFT).hst $(DRAFT).pyg debug_defines.* *.scala \ $(NOTES).pdf $(NOTES).toc $(NOTES).log $(NOTES).hst $(NOTES).pyg \ *.idx *.ind *.ilg *.lot *.lof *.out From 6a5800cf5d344619218ed93565c1b59849e085f3 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 2 Oct 2023 09:04:52 -0700 Subject: [PATCH 13/30] AR: Clarify section/chapter in Sdext. Addresses #894 --- Sdext.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Sdext.tex b/Sdext.tex index c843b8e9..d3ab4aa4 100644 --- a/Sdext.tex +++ b/Sdext.tex @@ -9,7 +9,7 @@ \chapter{Sdext (ISA Extension)} of the rest. In order to be compatible with this specification an implementation must -implement everything described in this section that is not explicitly listed as +implement everything described in this chapter that is not explicitly listed as optional. If Sdext is implemented and Sdtrig is not implemented, then accessing any of the @@ -25,7 +25,7 @@ \section{Debug Mode} \label{debugmode} \begin{steps}{When executing code due to an abstract command, the hart stays in Debug Mode and the following apply:} \item All implemented instructions operate just as they do in M-mode, unless - an exception is mentioned in this section. + an exception is mentioned in this list. \item All operations are executed with machine mode privilege, except that additional Debug Mode CSRs are accessible and \FcsrMstatusMprv in \Rmstatus may be ignored according to \FcsrDcsrMprven. From a83e118153caf8def48475d929f7abfff9cf9230 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 2 Oct 2023 12:58:02 -0700 Subject: [PATCH 14/30] AR: Clarify why icount matches on every trap. --- Sdext.tex | 2 +- xml/hwbp_registers.xml | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Sdext.tex b/Sdext.tex index c843b8e9..02469093 100644 --- a/Sdext.tex +++ b/Sdext.tex @@ -141,7 +141,7 @@ \subsection{Step Bit In Dcsr} \label{stepBit} instead the instruction is treated as a {\tt nop}. This includes {\tt wfi}, {\tt wrs.sto}, and {\tt wrs.nto}. -\subsection{Icount Trigger} +\subsection{Icount Trigger} \label{stepIcount} Native debuggers won't have access to \RcsrDcsr, but can use the \RcsrIcount trigger by setting \FcsrIcountCount to 1. diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index 85e126c3..b86ac1a2 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -1009,6 +1009,19 @@ If more than one of the above events occur during a single instruction execution, the trigger still only matches once for that instruction. + \begin{commentary} + For use in single step, icount must match for traps where the + instruction will not be reexecuted after the handler, such as + illegal instructions that are emulated by privileged software and + the instruction being emulated never retires. Ideally, icount would + not match for traps where the instruction will later be retried by + the handler, such as page faults where privileged software modifies + the page tables and returns to the faulting instruction which + ultimately retires. Trying to distinguish the two cases leads to + complex rules, so instead the rule is simply that all traps match. + See also Section~\ref{stepIcount}. + \end{commentary} + When \FcsrIcountCount is greater than 1 and the trigger matches, then \FcsrIcountCount is decremented by 1. From 9590e02e21a1a1cbcb6b23b4e66edf9b0027c703 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 4 Oct 2023 07:58:58 -0700 Subject: [PATCH 15/30] AR: Clarify what tmexttrigger.intctl is for (#898) * AR: Clarify what tmexttrigger.intctl is for Addresses #891. * Add missing article Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com> Signed-off-by: Tim Newsome --------- Signed-off-by: Tim Newsome Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com> --- xml/hwbp_registers.xml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index b86ac1a2..435ef802 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -1303,6 +1303,12 @@ An implementation may either ignore the signal altogether when it cannot fire (dropping the trigger event) or it may hold the action as pending and fire the trigger once it is legal to do so. + + \begin{commentary} + \FcsrTmexttriggerIntctl is intended to be used by the {\tt clicinttrig} + mechanism from the Core-Local Interrupt Controller (CLIC) RISC-V + Privileged Architecture Extensions. + \end{commentary} From 9ddcbcb1014f6381aa2bfd67c70f382eb70cadac Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 4 Oct 2023 09:29:44 -0700 Subject: [PATCH 16/30] AR: Define mcontrol* triggers and multiple accesses (#883) mcontrol: Behavior is undefined because it's deprecated. mcontrol6: If a trigger reports hit=before then some memory accesses may have been performed. If it reports immediately after, then all accesses have already been performed. --- xml/hwbp_registers.xml | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index 435ef802..be316436 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -385,6 +385,10 @@ though the load will not update its destination register. Debuggers should consider this when setting such breakpoints on, for example, memory-mapped I/O addresses. + + If an instruction matches this trigger and the instruction performs + multiple memory accesses, it is \unspecified which memory accesses + have completed before the trigger fires. @@ -748,15 +752,23 @@ - The trigger fired just before the instruction that triggered it was - retired, but after all preceding instructions are retired. + The trigger fired before the instruction that matched it was + retired, but after all preceding instructions are retired. This + explicitly allows for instructions to be partially executed. \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to the virtual address of the instruction that matched. - If a load operation matched and \FcsrMcontrolSixSelect=1 then a - memory access has been performed (including any side effects of - performing such an access) even though the load has not updated its - destination register. + An instruction that caused a trigger to fire might be executed + partially. In that case not all memory accesses may have been + performed, and some registers may not have been updated. Executing + that instruction again must have the same result as fully executing + it the first time would have, except for any effects due to + non-idempotent memory. Implementations should avoid partial + instruction execution, but it might be unavoidable for instructions + that perform a large number of operations. + + For vector instructions, the vstart mechanism can be used to handle + partial execution without duplicating memory accesses. @@ -773,6 +785,9 @@ \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to the virtual address of the next instruction that must be executed to preserve the program flow. + + If the instruction performed multiple memory accesses, all of them + have been completed. From 79e33fb7840af72b648d0c62d5e5aa988f67a958 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 4 Oct 2023 09:57:03 -0700 Subject: [PATCH 17/30] AR: Clarify triggers and multiple state changes Incorporate more feedback from AR. Moved this into a separate Sdtrig section, since the discussion could also apply to instructions that cause triggers beside memory access ones. (E.g. an instruction that combines memory accesses with a trigger, and itrigger.) Follow up to #883. --- Sdtrig.tex | 18 ++++++++++++++++++ xml/hwbp_registers.xml | 16 +++------------- 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/Sdtrig.tex b/Sdtrig.tex index a0306ec8..10ab4a57 100644 --- a/Sdtrig.tex +++ b/Sdtrig.tex @@ -319,6 +319,24 @@ \subsection{Cache Operations} \end{steps} \end{commentary} +\section{Multiple State Change Instructions} \label{sec:multistate} + +An instruction that performs multiple architectural state changes (e.g., +register updates and/or memory accesses) might cause a trigger to fire at an +intermediate point in its execution. As a result, architectural state changes up +to that point might have been performed, while subsequent state changes, +starting from the event that activated the trigger, might not have been. The +definition of such an instruction will specify the order in which architectural +state changes take place. Alternatively, it may state that partial execution is +not allowed, implying that a mid-execution trigger must prevent any +architectural state changes from occurring. + +Debuggers won't be aware if an instruction has been partially executed. When +they resume execution, they will execute the same instruction once more. +Therefore, it's crucial that partially executing the instruction and then +executing it again leaves the hart in a state closely resembling the state it +would have been in if the instruction had only been executed once. + \section{Trigger Registers} These registers are CSRs, accessible using the RISC-V {\tt csr} opcodes and diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index be316436..9ebf2df0 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -754,21 +754,11 @@ The trigger fired before the instruction that matched it was retired, but after all preceding instructions are retired. This - explicitly allows for instructions to be partially executed. + explicitly allows for instructions to be partially executed, as + described in Section \ref{sec:multistate}. + \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to the virtual address of the instruction that matched. - - An instruction that caused a trigger to fire might be executed - partially. In that case not all memory accesses may have been - performed, and some registers may not have been updated. Executing - that instruction again must have the same result as fully executing - it the first time would have, except for any effects due to - non-idempotent memory. Implementations should avoid partial - instruction execution, but it might be unavoidable for instructions - that perform a large number of operations. - - For vector instructions, the vstart mechanism can be used to handle - partial execution without duplicating memory accesses. From 4aad021ee3f3f6e4548f91a862e769005e1e8e7a Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 4 Oct 2023 09:59:51 -0700 Subject: [PATCH 18/30] Revert "AR: Clarify triggers and multiple state changes" Accidentally pushed to master instead of a feature branch. This reverts commit 79e33fb7840af72b648d0c62d5e5aa988f67a958. --- Sdtrig.tex | 18 ------------------ xml/hwbp_registers.xml | 16 +++++++++++++--- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/Sdtrig.tex b/Sdtrig.tex index 10ab4a57..a0306ec8 100644 --- a/Sdtrig.tex +++ b/Sdtrig.tex @@ -319,24 +319,6 @@ \subsection{Cache Operations} \end{steps} \end{commentary} -\section{Multiple State Change Instructions} \label{sec:multistate} - -An instruction that performs multiple architectural state changes (e.g., -register updates and/or memory accesses) might cause a trigger to fire at an -intermediate point in its execution. As a result, architectural state changes up -to that point might have been performed, while subsequent state changes, -starting from the event that activated the trigger, might not have been. The -definition of such an instruction will specify the order in which architectural -state changes take place. Alternatively, it may state that partial execution is -not allowed, implying that a mid-execution trigger must prevent any -architectural state changes from occurring. - -Debuggers won't be aware if an instruction has been partially executed. When -they resume execution, they will execute the same instruction once more. -Therefore, it's crucial that partially executing the instruction and then -executing it again leaves the hart in a state closely resembling the state it -would have been in if the instruction had only been executed once. - \section{Trigger Registers} These registers are CSRs, accessible using the RISC-V {\tt csr} opcodes and diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index 9ebf2df0..be316436 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -754,11 +754,21 @@ The trigger fired before the instruction that matched it was retired, but after all preceding instructions are retired. This - explicitly allows for instructions to be partially executed, as - described in Section \ref{sec:multistate}. - + explicitly allows for instructions to be partially executed. \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to the virtual address of the instruction that matched. + + An instruction that caused a trigger to fire might be executed + partially. In that case not all memory accesses may have been + performed, and some registers may not have been updated. Executing + that instruction again must have the same result as fully executing + it the first time would have, except for any effects due to + non-idempotent memory. Implementations should avoid partial + instruction execution, but it might be unavoidable for instructions + that perform a large number of operations. + + For vector instructions, the vstart mechanism can be used to handle + partial execution without duplicating memory accesses. From 1b81755561c8155b236f132cad083ecbec8c5d0b Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 4 Oct 2023 09:57:03 -0700 Subject: [PATCH 19/30] AR: Clarify triggers and multiple state changes Incorporate more feedback from AR. Moved this into a separate Sdtrig section, since the discussion could also apply to instructions that cause triggers beside memory access ones. (E.g. an instruction that combines memory accesses with a trigger, and itrigger.) Follow up to #883. --- Sdtrig.tex | 18 ++++++++++++++++++ xml/hwbp_registers.xml | 16 +++------------- 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/Sdtrig.tex b/Sdtrig.tex index a0306ec8..10ab4a57 100644 --- a/Sdtrig.tex +++ b/Sdtrig.tex @@ -319,6 +319,24 @@ \subsection{Cache Operations} \end{steps} \end{commentary} +\section{Multiple State Change Instructions} \label{sec:multistate} + +An instruction that performs multiple architectural state changes (e.g., +register updates and/or memory accesses) might cause a trigger to fire at an +intermediate point in its execution. As a result, architectural state changes up +to that point might have been performed, while subsequent state changes, +starting from the event that activated the trigger, might not have been. The +definition of such an instruction will specify the order in which architectural +state changes take place. Alternatively, it may state that partial execution is +not allowed, implying that a mid-execution trigger must prevent any +architectural state changes from occurring. + +Debuggers won't be aware if an instruction has been partially executed. When +they resume execution, they will execute the same instruction once more. +Therefore, it's crucial that partially executing the instruction and then +executing it again leaves the hart in a state closely resembling the state it +would have been in if the instruction had only been executed once. + \section{Trigger Registers} These registers are CSRs, accessible using the RISC-V {\tt csr} opcodes and diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index be316436..9ebf2df0 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -754,21 +754,11 @@ The trigger fired before the instruction that matched it was retired, but after all preceding instructions are retired. This - explicitly allows for instructions to be partially executed. + explicitly allows for instructions to be partially executed, as + described in Section \ref{sec:multistate}. + \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to the virtual address of the instruction that matched. - - An instruction that caused a trigger to fire might be executed - partially. In that case not all memory accesses may have been - performed, and some registers may not have been updated. Executing - that instruction again must have the same result as fully executing - it the first time would have, except for any effects due to - non-idempotent memory. Implementations should avoid partial - instruction execution, but it might be unavoidable for instructions - that perform a large number of operations. - - For vector instructions, the vstart mechanism can be used to handle - partial execution without duplicating memory accesses. From aaab8fbb70db93edb5a84ac9b5607e30a462ffd1 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 3 Oct 2023 10:17:49 -0700 Subject: [PATCH 20/30] AR: Update priority table from latest privspec Addresses #892. --- Sdtrig.tex | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/Sdtrig.tex b/Sdtrig.tex index a0306ec8..45800e64 100644 --- a/Sdtrig.tex +++ b/Sdtrig.tex @@ -114,36 +114,36 @@ \section{Priority} \begin{table}[H] \centering -\begin{tabular}{|l|r|l|l|} +\begin{tabulary}{\textwidth}{|l|p{.7in}|p{2.3in}|p{2.5in}|} \hline - Priority & Exception & Description & Trigger \\ - & Code & & \\ + Priority & Exception Code & Description & Trigger \\ \hline {\em Highest} & 3 & & etrigger \\ & 3 & & icount \\ & 3 & & itrigger \\ - & 3 & & mcontrol/mcontrol6 after \\ - & & & \hspace{2em}(on previous instruction) \\ + & 3 & & mcontrol/mcontrol6 after (on previous instruction) \\ \hline & 3 & Instruction address breakpoint & mcontrol/mcontrol6 execute address before \\ \hline - & 12 & Instruction page fault & \\ \hline - & 1 & Instruction access fault & \\ \hline + & 12, 20, 1 & During instruction address translation: + First encountered page fault, guest-page fault, or access fault & \\ \hline + & 1 & With physical address for instruction: + Instruction access fault & \\ \hline & 3 & & mcontrol/mcontrol6 execute data before \\ \hline & 2 & Illegal instruction & \\ + & 22 & Virtual instruction & \\ & 0 & Instruction address misaligned & \\ - & 8, 9, 11 & Environment call & \\ + & 8, 9, 10, 11 & Environment call & \\ & 3 & Environment break & \\ - & 3 & Load/Store/AMO address breakpoint & mcontrol/mcontrol6 load/store address before \\ - & 3 & & mcontrol/mcontrol6 store data before \\ \hline - & 6 & Store/AMO address misaligned & \\ - & 4 & Load address misaligned & \\ \hline - & 15 & Store/AMO page fault & \\ - & 13 & Load page fault & \\ \hline - & 7 & Store/AMO access fault & \\ - & 5 & Load access fault & \\ - {\em Lowest} & 3 & & mcontrol/mcontrol6 load data before \\ - \hline -\end{tabular} + & 3 & Load/Store/AMO address breakpoint & mcontrol/mcontrol6 load/store address/data before \\ \hline + & 4, 6 & Optionally: Load/Store/AMO address misaligned & \\ \hline + & 13, 15, 21, 23, 5, 7 & During address translation for an explicit memory access: + First encountered page fault, guest-page fault, or access fault & \\ \hline + & 5, 7 & With physical address for an explicit memory access: + Load/store/AMO access fault & \\ \hline + & 4, 6 & If not higher priority: + Load/store/AMO address misaligned & \\ \hline + {\em Lowest} & 3 & & mcontrol/mcontrol6 load data before \\ \hline +\end{tabulary} \caption{Synchronous exception priority in decreasing priority order.} \label{tab:priority} \end{table} From 9f3fd6ffec9c0db5d74cf40880fac4b1cecf7fb5 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 5 Oct 2023 13:09:57 -0700 Subject: [PATCH 21/30] Add people with git PRs to credits. Add everyone who had a PR merged that changed the spec itself. --- preface.tex | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/preface.tex b/preface.tex index b1094f66..30fbdd3f 100644 --- a/preface.tex +++ b/preface.tex @@ -22,6 +22,7 @@ \chapter{Preface} Mark Beal, Alex Bradbury, Chuanhua Chang, +Yen Hao Chen, Zhong-Ho Chen, Monte Dalrymple, Paul Donahue, @@ -38,6 +39,8 @@ \chapter{Preface} Scott Johnson, L. J. Madar, Grigorios Magklis, +Daniel Mangum, +Alexis Marquet, Jan Matyas, Kai Meinhard, Jean-Luc Nagel, @@ -50,9 +53,12 @@ \chapter{Preface} Ken Pettit, Darius Rad, Joe Rahmeh, +Josh Scheid, +Vedvyas Shanbhogue, Gavin Stark, Ben Staveley, Wesley Terpstra, +Tommy Thorn, Megan Wachs, Jan-Willem van de Waerdt, Philipp Wagner, @@ -61,4 +67,5 @@ \chapter{Preface} Andrew Waterman, Thomas Wicki, Andy Wright, -and Bryan Wyatt. \ No newline at end of file +Bryan Wyatt, +and Florian Zaruba. From b699db63c31a6d817cf84f3274cd4bc3f9eb2cc5 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 9 Oct 2023 09:36:40 -0700 Subject: [PATCH 22/30] AR: Clarify itrigger behavior. Specifically, make clear that itrigger fires *after* the original exception has finished updating all the CSRs. Hopefully resolves #890. --- xml/hwbp_registers.xml | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index 9ebf2df0..60045764 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -1145,11 +1145,13 @@ interrupt. (E.g.\ it does not fire when a timer interrupt occurs but that interrupt is not enabled in \Rmie.) - When the trigger fires, all CSRs are updated for the interrupt trap as defined by the - Privileged Spec, and the requested action is taken just before the - first instruction of the trap handler is executed. - If the trigger fires with \FcsrItriggerAction=0 then zero is written to the - {\tt tval} CSR on the breakpoint trap (see ~\ref{sec:nativetrigger}). + When the trigger matches, it fires after the trap occurs, just before + the first instruction of the trap handler is executed. If + \FcsrItriggerAction=0, the standard CSRs are updated for taking the + breakpoint trap, and zero is written to the relevant {\tt tval} CSR. If + the breakpoint trap does not go to a higher privilege mode, this will + lose CSR information for the original trap. See + Section~\ref{sec:nativetrigger} for more information about this case. If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this trigger, it only matches when the conditions set there are satisfied. @@ -1224,11 +1226,13 @@ back \RcsrTdataTwo after writing it to confirm the requested functionality is actually supported. - When the trigger fires, all CSRs are updated for the exception as defined by the - Privileged Spec, and the requested action is taken just before the - first instruction of the trap handler is executed. - If the trigger fires with \FcsrEtriggerAction=0 then zero is written to the - {\tt tval} CSR on the breakpoint trap (see ~\ref{sec:nativetrigger}). + When the trigger matches, it fires after the trap occurs, just before + the first instruction of the trap handler is executed. If + \FcsrEtriggerAction=0, the standard CSRs are updated for taking the + breakpoint trap, and zero is written to the relevant {\tt tval} CSR. If + the breakpoint trap does not go to a higher privilege mode, this will + lose CSR information for the original trap. See + Section~\ref{sec:nativetrigger} for more information about this case. If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this trigger, it only matches when the conditions set there are satisfied. From 92835a85352d2b5e087ca953c164181367078fe8 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 11 Oct 2023 11:17:06 -0700 Subject: [PATCH 23/30] AR: Clarify itrigger and trigger number translation itrigger numbers relate to the value written to *cause when the trap is taken. Addresses #889. --- xml/hwbp_registers.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml index 60045764..1c63843a 100755 --- a/xml/hwbp_registers.xml +++ b/xml/hwbp_registers.xml @@ -1132,19 +1132,19 @@ This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 4. - This trigger may fire on any of the interrupts configurable in \Rmie - (described in the Privileged Spec) or the NMI. The interrupts to fire on are - configured by setting the same bit in \RcsrTdataTwo as would be set in - \Rmie to enable the interrupt. + This trigger can fire when an interrupt trap is taken. + + It can be enabled for individual interrupt numbers by setting the bit + corresponding to the interrupt number in \RcsrTdataTwo. The interrupt + number is interpreted in the mode that the trap handler executes in. + (E.g. virtualized interrupt numbers are not the same in every mode.) + In addition the trigger can be enabled for non-maskable interrupts using + \FcsrItriggerNmi. Hardware may only support a subset of interrupts for this trigger. A debugger must read back \RcsrTdataTwo after writing it to confirm the requested functionality is actually supported. - The trigger only fires if the hart takes a trap because of the - interrupt. (E.g.\ it does not fire when a timer interrupt occurs but that - interrupt is not enabled in \Rmie.) - When the trigger matches, it fires after the trap occurs, just before the first instruction of the trap handler is executed. If \FcsrItriggerAction=0, the standard CSRs are updated for taking the From 51f5a29c0126d69f314079fb4f1197876aca7622 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 12 Oct 2023 13:06:07 -0700 Subject: [PATCH 24/30] Rebuild PDF. --- riscv-debug-stable.pdf | Bin 1067144 -> 1070176 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/riscv-debug-stable.pdf b/riscv-debug-stable.pdf index 2be7c165015498e0d4c1daa65e4a9b013a3bdcd6..5fa59040205f6d1bbdd31cd30d2f42ced9d25401 100644 GIT binary patch delta 398438 zcmY(JQ*b2=u&ra;nb@``wr!ge+dEDsPIjz`ZQHhO+vfext-4j`R;`DA>X)wW>i$+o zBna=83df59^Qve8OWI@hc#;{z;K|lxSbHRV$pHO#IYmu$w|>@9P6rj zW-eH?*!UM3SQ1l%GYXDfmnvS$EB=H9Ia#EkO|qV783plvvh4ApM~-=xrMqIW$vMe+ z7b93es0zy!n(4?=A}$aDQ?x^Wz#0?|?2q~7=&;C_Z73lCnsR-evuUx8(`#X7x+r=f&a+myL~Zmu5w<_Vl^`6;BnuE~E?Fb+ z;qYHP4yY`bLfllr=`d-IP~$LCCzTOz;B8$IFA#b-zK~Cy5l|%m;`|{tJ+BTlkuoOI z>oW{?PKs9}+?|#NmORn%LIpa~~)u+W> z`qNoOo~?5Ep(UW?D!FuKt}_BC*FJ@e&--LDIi)Rf%giBzop@+`WjeFTy%RTM?LL z7_nW$|B~&iTIf>l?L1|**SYtSEIMRF|IYF*V;O4f3I#GyU$d>HEN%%}u_dLy20CB5 zOgVUDO24rB%`9kG+}x2b$Zj`M&dTbbsZVdsHJDe((#9C-G;^-$FD0w5ZQTn2>UyRd zD=ze8cjQ+uNR&sbgPQUx><$)noA^mKUE5R{ynZXDm-6ef|CzZN6l*Kt%wE!V%i=ff zQpB@#xf(7mcI)lZIs!N5mqxGZe6q)x<+OmcDQ-WuB_G+4mUL;jD)%VTT}W*07_NI2 zoL_Pua$ktJQa^@hD~L(LcW9CaG*1u}kRhZXS~*vKX3%(DJc4vvKLX6dy_4M=FATKx zG-ukR-~JWDZZ2MM+L?}@zBji|*gZ-1*7ZEe7dKQ~j&wg)fNa8frC@!^7cddc8zTkB z)BFag>@&=}Ti8tjI#{*dST!!wjEd7LGqq@b zb#x=-J$U{z-^R4{Vbd)Q-d5*4SZ{X2_Pg;66c*IcelSZ zrQdR`#(OcM|NZ{`3-x{u5OHeV-oBRh#6&0wOQi7k*UEGX#bNzjiZjuwo5dGt!*#$5 z(SXUXwfvskvwIA=^J7742yBeLkzoTXKRs)zGt-hMc^fx;OK)z=;|fR4lo+SI%)Pyh z@XLQbvO==D{M8u>(EFJLTAEjm&zsnO@2lv{7ly2iCR}_bKjLKmCJEo3buxz6$;rpF z80i+5aRt-JC5(^XHh$>>aW^Wf`hu_s-_}L#rvz&{ja`4`^6h5^(EMUoZPIbsKv0f0DXrIP7J@7nq5Fba(~b;hGm z8%Wu#IEbPGpL?Ud?Ic{nWRH|E!F&CoByzV%mh}C}5z@L8QsE>4#40%9ZuKN0x^T4Y zCM^a^+E94Eh?}x|%b6pKX=XvCOey$yDWc)$c!Fbt&4ub!`dB};VP}5j zXA@xiu*lBA&=lZ#Yg`32l@wj?&4uXKgoEO5F5hsLVUsXob}d+dj$nCQcEe# z(wI|1pesO1$5agXgs^H*P`4UMmC;)8cYNPAp4Ri8LPDBD02;p~WsPA}0lL%U z#{Gi|eiu4Z`A36|f42d>1M-xS>b`!jzpAqeuhHl)2Tl zXan37JNqBPD$6VxvVkA;ZlfW#nKwNTX7jj-8>*26V~1jC(D*A11Uj zHj(}0XQN$(#IvWxf-h{03Ds?>!84nje3&3h4ilo{jpt>wcKc@cE*W^%9pnn)FQT(n z`PTKxjxkC82_d_T(jC@P0{&tr6EV3(VR^iSE0b&r%2E2X%$%_R>rCc2+?B+p3gc~n zE$??aWan;i`muDS2P~6iT^rx2_rwzMsd!ZX%jIF@-R5x7zOT~T>HJSZn03D?Eh5x{ zP#b$ICF0H*)^^#zh1T5#RQ^Vlk82Bv;z7NxonevgO%Wbe#XkH)+9Ix8iaaI2l4=D} zkt+H)ER)9NvFQb=U1qh~B-6_yeoP)f@M9aWB-Km%lP5F)`sd9y;7O{NOy&2%UG7o? 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