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[rpsene]

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[benhur1899]

Can The RISC-V Instruction Set Manual Volume I: Unprivileged ISA be viewed as one single specification?

[wmat]

Is this what you're looking for? https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf

[benhur1899]

Thanks a lot! But what I want to know is that if this volume book can be seen as one single RV specification? Or it just a compilation of RV specifications? What's the definition of a RV specification?

[gfavor]

Currently there is not one document that contains ALL ratified extensions. There are the Unpriv and Priv documents, various not-yet-integrated ISA extension specs, and various Non-ISA extension specs. On the ISA side the near-term goal is to integrate all ISA specs into two (Unpriv and Priv) spec documents. Regarding definition of a spec, each architecture extension (whether ISA or Non-ISA) has a specification. I would distinguish that from integrating ISA specs together into ISA spec *documents*. Although many people will loosely refer to the Priv document, for example, as the "Priv spec" insofar as it contains Privileged Architecture specs. Greg Greg

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On Fri, Feb 16, 2024 at 10:16 AM benhur1899 ***@***.***> wrote: Thanks a lot! But what I want to know is that if this volume book can be seen as one single RV specification? Or it just a compilation of RV specifications? What's the definition of a RV specification? — Reply to this email directly, view it on GitHub <#986 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ALLX6GVH4ATM2KTGHXV2TJ3YT6PALAVCNFSM6AAAAAAVUK45L2VHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4DIOJVG43DS> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.*** com>

[benhur1899]

Thanks a lot! Got it!

[Zoro210]

In the translation process, after finding the leaf page, we will check for the SUM and MXR bit of m-status register. How can the supervisor access the mstatus?

[chili-chips-ba]

We are curious the hear your expert take on this question about RISC-V support for misaligned accesses in the ISS context.

Also is there a standardized designation to convey whether misaligned accesses are supported in hardware, or implemented via software traps? It is not Zam, is it?