Releases: riscv/riscv-isa-manual
Releases · riscv/riscv-isa-manual
riscv-isa-release-157641b-2024-03-12
This release was created by: aswaterman
Release of RISC-V ISA, built from commit 157641b, is now available.
What's Changed
- fix typo for hypervisor by @chihminchao in #1252
- Clarify behavior of CSR access side effects by @aswaterman in #1256
Full Changelog: riscv-isa-release-7ba890b-2024-03-07...riscv-isa-release-157641b-2024-03-12
Contributors
aswaterman and chihminchao
Assets 6
riscv-isa-release-7ba890b-2024-03-07
This release was created by: wmat
Release of RISC-V ISA, built from commit 7ba890b, is now available.
What's Changed
Full Changelog: riscv-isa-release-722fb43-2024-03-05...riscv-isa-release-7ba890b-2024-03-07
Contributors
wmat
Assets 6
riscv-isa-release-722fb43-2024-03-05
This release was created by: aswaterman
Release of RISC-V ISA, built from commit 722fb43, is now available.
What's Changed
- Update Smrnmi to account for Smdbltrp extension by @aswaterman in #1248
Full Changelog: riscv-isa-release-4571fc3-2024-03-05...riscv-isa-release-722fb43-2024-03-05
Contributors
aswaterman
Assets 6
riscv-isa-release-4571fc3-2024-03-05
This release was created by: wmat
Release of RISC-V ISA, built from commit 4571fc3, is now available.
What's Changed
Full Changelog: riscv-isa-release-078b469-2024-03-05...riscv-isa-release-4571fc3-2024-03-05
Contributors
wmat
Assets 6
riscv-isa-release-078b469-2024-03-05
This release was created by: wmat
Release of RISC-V ISA, built from commit 078b469, is now available.
What's Changed
- Add marchid for Coreblocks by @piotro888 in #1190
- Add Sstc.adoc to privileged spec. by @wmat in #1230
New Contributors
- @piotro888 made their first contribution in #1190
Full Changelog: riscv-isa-release-e53b98a-2024-02-29...riscv-isa-release-078b469-2024-03-05
Contributors
wmat and piotro888
Assets 6
riscv-isa-release-e53b98a-2024-02-29
This release was created by: wmat
Release of RISC-V ISA, built from commit e53b98a, is now available.
What's Changed
Full Changelog: riscv-isa-release-c9ad1c8-2024-02-29...riscv-isa-release-e53b98a-2024-02-29
Contributors
wmat
Assets 6
riscv-isa-release-c9ad1c8-2024-02-29
This release was created by: wmat
Release of RISC-V ISA, built from commit c9ad1c8, is now available.
What's Changed
- Pulling in changes from main. by @wmat in #1237
- Zc - Code Size Reduction chapter integration. by @wmat in #1216
Full Changelog: riscv-isa-release-61b2ce9-2024-02-29...riscv-isa-release-c9ad1c8-2024-02-29
Contributors
wmat
Assets 6
riscv-isa-release-61b2ce9-2024-02-29
This release was created by: wmat
Release of RISC-V ISA, built from commit 61b2ce9, is now available.
What's Changed
- fix typo by @Phantom1003 in #1138
- Fix typo by @lpha-z in #1145
- Fix journal name typo by @visitorckw in #1146
- Fix typo and missing by @yf13 in #1152
- Fix wrong bit length of rd field by @404allen404 in #1153
- Define hardware error exception cause code by @aswaterman in #1105
- Specify SFENCE/HFENCE requirements when changing PBMTE by @aswaterman in #1111
- Bump supervisor ISA version to 1.13-draft by @aswaterman in #1110
- Clarify constraints on when tval might be zeroed by @aswaterman in #1108
- Define the RV32-only medelegh CSR by @aswaterman in #1109
- delete user-mode interrupt notes in mtvec register section by @yf13 in #1159
- Fix typo: "Sv38" => "Sv48" by @OccupyMars2025 in #1162
- Application to RISC-V on adding new marchid for CV-Wally from Harvey … by @stineje in #1164
- Fix MODE field description of mtvec register by @HepoH3 in #1165
- Add PMM field to *envcfg and mseccfg by @aswaterman in #1170
- Specify that the supervisor physical address is divided by 4 KiB by @charlie-rivos in #1177
- Add marchid for Boa-RISC-V (on the correct branch this time) by @robotman2412 in #1182
- Add marchid for WIV64 by @StartForKiller in #1183
- marchid allocation request for RV6 by @kiclu in #1184
- Add marchid for ApogeoRV by @GabbedT in #1185
- Add marchid for MicroRV32 by @saahm in #1188
- Delete word with inconsistency by @demin-han in #1189
- fix broken alloy link by @kbroch-rivosinc in #1202
- Redefine MXL to be read-only by @aswaterman in #1204
- Add note to guide trap handler design by @ved-rivos in #1208
- Clarifications to the Addressing and Memory Protection section by @ved-rivos in #1142
- Attempts to access non-existent CSRs are reserved by @aswaterman in #1207
- Remove Zam; define misaligned atomicity granule PMA by @aswaterman in #1206
- Incorporate Svadu and Svade specs by @aswaterman in #1209
- Add a QEMU architecture ID by @palmer-dabbelt in #1213
- Add clarifying non-normative comments about [m]time by @aswaterman in #1210
- Don't conflate hart and system by @pdonahue-ventana in #1215
- Hardware Error exception priority by @ved-rivos in #1223
- added KianV RISC-V marchID by @splinedrive in #1228
- Zawrs - Wait-on-Reservation-Set chapter integration. by @wmat in #1217
- Fixes for H extension status diagrams by @sorear in #1238
- a typo by @OccupyMars2025 in #1240
- Fix typo: Quotation mark formatting mismatch in intro.adoc. by @Yakkhini in #1243
- Adding Base Cache Management Operation ISA Extensions chapter. by @wmat in #1226
- Clarify when SFENCE.W.INVAL/SFENCE.INVAL.IR are legal by @aswaterman in #1246
- Explicitly allow side effects for a failed SC by @sorear in #1239
- Add new Action to Release a new ISA when merging a PR by @rpsene in #1247
- Update merge-and-release.yml by @rpsene in #1250
New Contributors
- @Phantom1003 made their first contribution in #1138
- @lpha-z made their first contribution in #1145
- @visitorckw made their first contribution in #1146
- @yf13 made their first contribution in #1152
- @404allen404 made their first contribution in #1153
- @OccupyMars2025 made their first contribution in #1162
- @stineje made their first contribution in #1164
- @HepoH3 made their first contribution in #1165
- @robotman2412 made their first contribution in #1182
- @StartForKiller made their first contribution in #1183
- @kiclu made their first contribution in #1184
- @GabbedT made their first contribution in #1185
- @saahm made their first contribution in #1188
- @demin-han made their first contribution in #1189
- @kbroch-rivosinc made their first contribution in #1202
- @splinedrive made their first contribution in #1228
- @Yakkhini made their first contribution in #1243
Full Changelog: 2023-10-02...riscv-isa-release-61b2ce9-2024-02-29
Contributors
wmat, sorear, and 23 other contributors
Assets 6
2023-10-02
What's Changed
- A-ext chapter: 64-bit word => doubleword; 32-bit word => word by @ved-rivos in #1052
- fix satp.asid width by @nananapo in #1055
- Fix format errors in c-st-ext.adoc by @nananapo in #1058
- Change "Reserved" to "Designated" in RVC HINT instructions table by @nananapo in #1059
- Update reg-based-ldnstr.adoc by @tariqkurd-repo in #1066
- fix missing " in misa description by @nananapo in #1065
- fix formatting by @tariqkurd-repo in #1069
- Make "Conditional Branches" wavdrom consistent by @charlie-rivos in #1071
- Correct Name of LR/SC Instructions rl bit by @charlie-rivos in #1073
- Make "Integer Register-Immediate Operations" Consistent by @charlie-rivos in #1072
- Resolve incorrect formatting in CS format by @charlie-rivos in #1074
- priv-1.13: clarify that MXLEN >= SXLEN; constrain SXLEN >= UXLEN by @aswaterman in #1028
Zmmulis now version 1.0 (ratified) by @a4lg in #1077C.XORis not RV64/RV128 only by @a4lg in #1076- Fix C.ADDI16SP immediate by @charlie-rivos in #1079
- Counters are now ratified (with version 2.0) by @a4lg in #1083
- Add
*.htmltobuild/.gitignoreby @a4lg in #1089 - Add
*.pdf.tmpto build/.gitignore by @a4lg in #1091 - Mark Zfa as Frozen and Version 1.0 by @palmer-dabbelt in #1096
- Update supervisor.adoc by @tariqkurd-repo in #1101
- Update f-st-ext.adoc by @fourcolor in #1106
- Add OP-V to base opcode map (AsciiDoc port) by @a4lg in #1118
- Clarify ordering rules when PBMT=IO is used on main-memory regions by @aswaterman in #1112
- Add missing words by @KubaO in #1122
- Clarify REM wording by @hdelassus in #1123
- apply compression for adoc pdf outputs by @jnk0le in #1125
- Fix MIE register bitfield caption by @KubaO in #1126
- update marchid.md for cve2 by @davideschiavone in #1130
- Standardize on no hyphen in illegal instruction exception by @aswaterman in #1131
- Hyphenate "virtual-/illegal-instruction exception" by @aswaterman in #1133
- M implies Zmmul by @nick-knight in #1121
- Don't describe WFI as a hint by @aswaterman in #1107
- Allow Misaligned Stores with Page Fault to partially succeed by @ingallsj in #1119
- Fix typos by @kianmeng in #1136
New Contributors
- @nananapo made their first contribution in #1055
- @charlie-rivos made their first contribution in #1071
- @fourcolor made their first contribution in #1106
- @KubaO made their first contribution in #1122
- @hdelassus made their first contribution in #1123
- @jnk0le made their first contribution in #1125
- @kianmeng made their first contribution in #1136
Full Changelog: riscv-isa-release-1239329-2023-05-23...2023-10-02
Contributors
kianmeng, aswaterman, and 13 other contributors
Assets 7
2023-10-02
What's Changed
- A-ext chapter: 64-bit word => doubleword; 32-bit word => word by @ved-rivos in #1052
- fix satp.asid width by @nananapo in #1055
- Fix format errors in c-st-ext.adoc by @nananapo in #1058
- Change "Reserved" to "Designated" in RVC HINT instructions table by @nananapo in #1059
- Update reg-based-ldnstr.adoc by @tariqkurd-repo in #1066
- fix missing " in misa description by @nananapo in #1065
- fix formatting by @tariqkurd-repo in #1069
- Make "Conditional Branches" wavdrom consistent by @charlie-rivos in #1071
- Correct Name of LR/SC Instructions rl bit by @charlie-rivos in #1073
- Make "Integer Register-Immediate Operations" Consistent by @charlie-rivos in #1072
- Resolve incorrect formatting in CS format by @charlie-rivos in #1074
- priv-1.13: clarify that MXLEN >= SXLEN; constrain SXLEN >= UXLEN by @aswaterman in #1028
Zmmulis now version 1.0 (ratified) by @a4lg in #1077C.XORis not RV64/RV128 only by @a4lg in #1076- Fix C.ADDI16SP immediate by @charlie-rivos in #1079
- Counters are now ratified (with version 2.0) by @a4lg in #1083
- Add
*.htmltobuild/.gitignoreby @a4lg in #1089 - Add
*.pdf.tmpto build/.gitignore by @a4lg in #1091 - Mark Zfa as Frozen and Version 1.0 by @palmer-dabbelt in #1096
- Update supervisor.adoc by @tariqkurd-repo in #1101
- Update f-st-ext.adoc by @fourcolor in #1106
- Add OP-V to base opcode map (AsciiDoc port) by @a4lg in #1118
- Clarify ordering rules when PBMT=IO is used on main-memory regions by @aswaterman in #1112
- Add missing words by @KubaO in #1122
- Clarify REM wording by @hdelassus in #1123
- apply compression for adoc pdf outputs by @jnk0le in #1125
- Fix MIE register bitfield caption by @KubaO in #1126
- update marchid.md for cve2 by @davideschiavone in #1130
- Standardize on no hyphen in illegal instruction exception by @aswaterman in #1131
- Hyphenate "virtual-/illegal-instruction exception" by @aswaterman in #1133
- M implies Zmmul by @nick-knight in #1121
- Don't describe WFI as a hint by @aswaterman in #1107
- Allow Misaligned Stores with Page Fault to partially succeed by @ingallsj in #1119
- Fix typos by @kianmeng in #1136
New Contributors
- @nananapo made their first contribution in #1055
- @charlie-rivos made their first contribution in #1071
- @fourcolor made their first contribution in #1106
- @KubaO made their first contribution in #1122
- @hdelassus made their first contribution in #1123
- @jnk0le made their first contribution in #1125
- @kianmeng made their first contribution in #1136
Full Changelog: riscv-isa-release-1239329-2023-05-23...2023-10-02
Contributors
kianmeng, aswaterman, and 13 other contributors