diff --git a/src/riscv-zabha.adoc b/src/riscv-zabha.adoc
index 7dabf7e..0bed425 100644
--- a/src/riscv-zabha.adoc
+++ b/src/riscv-zabha.adoc
@@ -1,9 +1,9 @@
 = Byte and Halfword Atomic Memory Operations (Zabha)
 :description: Byte and Halfword Atomic Memory Operations (Zabha)
 :company: RISC-V.org
-:revdate: 1/2024
+:revdate: 4/2024
 :revnumber: 1.0
-:revremark: This document is in Frozen state. See http://riscv.org/spec-state for details.
+:revremark: This document is in Ratified state. See http://riscv.org/spec-state for details.
 :url-riscv: http://riscv.org
 :doctype: book
 :preface-title: Preamble
@@ -39,14 +39,10 @@ endif::[]
 == Preamble
 
 [WARNING]
-.This document is in the link:http://riscv.org/spec-state[Frozen state]
+.This document is in the link:http://riscv.org/spec-state[Ratified state]
 ====
-Change is extremely unlikely. A high threshold will be used, and a change will
-only occur because of some truly critical issue being identified during the
-public review cycle. Any other desired or needed changes can be the subject of a
-follow-on new extension. This draft specification will change before being
-accepted as standard, so implementations made to this draft specification will
-likely not conform to the future standard.
+No changes are allowed. Any desired or needed changes can be the subject of a
+follow-on new extension. Ratified extensions are never revised.
 ====
 
 === Copyright and license information