Add support for the Zvknh[ab] extensions #235
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…iscv#191) * V extension general framework and configuration setting instructions * Update model/riscv_insts_vext_utils.sail fix a typo Co-authored-by: Nicolas Brunie <[email protected]> Signed-off-by: BrighterW <[email protected]> * Update model/riscv_insts_vext_vset.sail * Revisions after Nov 22 meeting * Update effect matching for functions in riscv_vlen.sail * Fix code formatting issues * Update model/riscv_insts_vext_utils.sail Co-authored-by: Jessica Clarke <[email protected]> Signed-off-by: Xinlai Wan <[email protected]> * Fix coding style issues * Update vset instructions Signed-off-by: BrighterW <[email protected]> Signed-off-by: Xinlai Wan <[email protected]> Co-authored-by: Nicolas Brunie <[email protected]> Co-authored-by: Jessica Clarke <[email protected]>
* Add vector load / store instructions * Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code * Update vstart setting in vector load / store instructions * Remove unnecessary assert statements in vector instructions * Fix bugs in vleff instructions and revise coding styles * Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure
* Add vector arithmetic & mask instructions * Update vector EEW and EMUL checking function * Add vector instruction illegal check functions * Adjust code formatting for vector instruction illegal check functions Merge approved by team at tech-golden-model meeting on 2023-03-14.
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Updated the PR:
This update is adjusting the implementation to match the Spike implenentation and as a follow-up. |
* Add vector floating-point instructions * Update vector floating-point conversion instructions * Update copyright headers for vector extension code --------- Co-authored-by: xwan <[email protected]>
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* Add vector mask and reduction instructions * Fix register overlap check in vector mask instructions --------- Co-authored-by: xwan <[email protected]>
To support the implementation of Zvknh[ab] extensions in SAIL, this creates the necessary infrastructure(i.e., a file to hold it, and the extension macro), preparing the tree for the Zvknh[ab] implementation. Signed-off-by: Charalampos Mitrodimas <[email protected]>
The "vsha2c[hl].vv" instruction performs two rounds of Vector SHA-2 compression. * "vsha2cl.vv" uses the two most significant message schedule words from the element group in "vs1". * "vsha2cl.vv" uses the two least significant message schedule words from the element group in "vs1" Reserved encodings: * Zvknha: SEW is any value other than 32. * Zvknhb: SEW is any value other than 32 or 64. Signed-off-by: Charalampos Mitrodimas <[email protected]>
The "vsha2ms.vv" instruction performs a Vector SHA-2 message schedule. Reserved encodings: * Zvknha: SEW is any value other than 32. * Zvknhb: SEW is any value other than 32 or 64. Signed-off-by: Charalampos Mitrodimas <[email protected]>
Signed-off-by: Charalampos Mitrodimas <[email protected]>
Signed-off-by: Charalampos Mitrodimas <[email protected]>
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Implements the Zvknh[ab] (NIST Suite: Vector SHA-2 Secure Hash) extension, as of version Draft: 20230303
The following instructions are included:
All instructions were tested with VLEN=128(SHA-256) & VLEN=256(SHA-512) and results were compared with QEMU results of each instruction.
Current revision is rebased with the latest changes of
vector-devbranch.